Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360298
L. Maresca, I. Matacena, M. Riccio, A. Irace, G. Breglio, S. Daliento
Silicon carbide (SiC) metal-oxide-semiconductor field effect transistor (MOSFETs) are gradually replacing silicon power devices in many applications because of the higher performances of the material. Even if the technology for SiC MOSFET has been improved in the last years, the very high interface SiO2/SiC trap density is still a problem that affects the present SiC MOSFET generations. This issue is still not addressed in technology computer aided design (TCAD) simulations supporting the devices development. In this work we demonstrate how an accurate calibration of the TCAD model of a commercial SiC MOSFET is only possible by considering a non-uniform trap distribution along the SiO2 SiC interface.
{"title":"TCAD model calibration for the SiC/SiO2 interface trap distribution of a planar SiC MOSFET","authors":"L. Maresca, I. Matacena, M. Riccio, A. Irace, G. Breglio, S. Daliento","doi":"10.1109/WiPDAAsia49671.2020.9360298","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360298","url":null,"abstract":"Silicon carbide (SiC) metal-oxide-semiconductor field effect transistor (MOSFETs) are gradually replacing silicon power devices in many applications because of the higher performances of the material. Even if the technology for SiC MOSFET has been improved in the last years, the very high interface SiO2/SiC trap density is still a problem that affects the present SiC MOSFET generations. This issue is still not addressed in technology computer aided design (TCAD) simulations supporting the devices development. In this work we demonstrate how an accurate calibration of the TCAD model of a commercial SiC MOSFET is only possible by considering a non-uniform trap distribution along the SiO2 SiC interface.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130231081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360255
Adam Elwailly, M. Xiao, Yuhao Zhang, H. Wong
For the first time, we systematically study the design space of vertical Ga2O3 junctionless FinFET for 600V to 5kV ratings using TCAD simulation with experimentally calibrated parameters. Two scenarios are investigated, namely with “excellent” and “poor” gate oxide/channel interfaces. “Excellent” and “poor” interfaces result in no and severe surface mobility degradation, respectively. It is found that, for the “excellent” case, fin width (W) should be made as small as possible for optimal design. For the “poor” case, optimal W is $sim$200nm because ION degrades when W<200nm. However, this can be alleviated by adopting a gradual channel doping scheme, which gives a$sim$30% boost in ION in the 600V application with a thinned wafer.
{"title":"Design Space of Vertical Ga2 O3 Junctionless FinFET and its Enhancement with Gradual Channel Doping","authors":"Adam Elwailly, M. Xiao, Yuhao Zhang, H. Wong","doi":"10.1109/WiPDAAsia49671.2020.9360255","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360255","url":null,"abstract":"For the first time, we systematically study the design space of vertical Ga2O3 junctionless FinFET for 600V to 5kV ratings using TCAD simulation with experimentally calibrated parameters. Two scenarios are investigated, namely with “excellent” and “poor” gate oxide/channel interfaces. “Excellent” and “poor” interfaces result in no and severe surface mobility degradation, respectively. It is found that, for the “excellent” case, fin width (W) should be made as small as possible for optimal design. For the “poor” case, optimal W is $sim$200nm because ION degrades when W<200nm. However, this can be alleviated by adopting a gradual channel doping scheme, which gives a$sim$30% boost in ION in the 600V application with a thinned wafer.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128733995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360256
He Du, F. Iannuzzo
The demand for highly reliable SiC MOSFETs is growing in the field applications, especially considering the short-circuit conditions. With the development of faster protection, short-circuit faults may occur many times within its expected service life, which only causes short-circuit degradation, rather than destructive failure. Based on finite element method simulation and experimental waveforms, this paper investigates the thermal and mechanical behavior of SiC MOSFET during short-circuit conditions, aiming to propose a package-level strategy to mitigate this short-circuit degradation and the results indicate that the front package design with sintered copper foil could be an effective approach.
{"title":"A Mitigation Strategy for the Short-Circuit Degradation in SiC MOSFETs","authors":"He Du, F. Iannuzzo","doi":"10.1109/WiPDAAsia49671.2020.9360256","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360256","url":null,"abstract":"The demand for highly reliable SiC MOSFETs is growing in the field applications, especially considering the short-circuit conditions. With the development of faster protection, short-circuit faults may occur many times within its expected service life, which only causes short-circuit degradation, rather than destructive failure. Based on finite element method simulation and experimental waveforms, this paper investigates the thermal and mechanical behavior of SiC MOSFET during short-circuit conditions, aiming to propose a package-level strategy to mitigate this short-circuit degradation and the results indicate that the front package design with sintered copper foil could be an effective approach.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"02 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127451305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360299
Yuma Murakawa, T. Hikihara
Variety of power sources are distributed in power systems at various classes of voltage, current, and power output capacities. They must be cooperatively used through parallel connected DC-DC converters for high efficiency and reliability. This paper proposes a passivity-based control for the regulation of parallel connected boost and buck converters. It is shown that the application of passivity-based control for each converter guarantees asymptotic stability of the whole system. The stability of the system is discussed through simulation and experiment. Transient and steady-state characteristics are examined depending on the setting of feedback gain.
{"title":"Regulation of Parallel Connected Boost and Buck Converters by Passivity-Based Control","authors":"Yuma Murakawa, T. Hikihara","doi":"10.1109/WiPDAAsia49671.2020.9360299","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360299","url":null,"abstract":"Variety of power sources are distributed in power systems at various classes of voltage, current, and power output capacities. They must be cooperatively used through parallel connected DC-DC converters for high efficiency and reliability. This paper proposes a passivity-based control for the regulation of parallel connected boost and buck converters. It is shown that the application of passivity-based control for each converter guarantees asymptotic stability of the whole system. The stability of the system is discussed through simulation and experiment. Transient and steady-state characteristics are examined depending on the setting of feedback gain.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122428600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the emerging technology of wide-band-gap power semiconductors and modern ferrite materials, the switching frequency of dc-dc converters based on gallium nitride (GaN) devices can be further pushed to megahertz range and achieve higher power density. A high step-down gain, high efficiency non-isolated dc-dc converter is proposed for front-end dc-dc converters used in data centers. The proposed converter is composed of three active switches, two synchronous rectifiers, two clamping capacitors and two inductors. Compared with the conventional buck converters, the proposed converter has higher voltage gain and lower voltage stresses across the active switches. A 300W/1 MHz GaN-based experimental prototype is built and tested to verify the correctness and validity, demonstrating a peak efficiency of 93.3% and full-load efficiency of 90.7%.
{"title":"A Novel Non-isolated GaN-based DC-DC Converter with High Step-Down Gain","authors":"Longyang Yu, Chengzi Yang, Shuting Feng, Feifei Yan, Xiang Zhou, Laili Wang","doi":"10.1109/WiPDAAsia49671.2020.9360280","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360280","url":null,"abstract":"With the emerging technology of wide-band-gap power semiconductors and modern ferrite materials, the switching frequency of dc-dc converters based on gallium nitride (GaN) devices can be further pushed to megahertz range and achieve higher power density. A high step-down gain, high efficiency non-isolated dc-dc converter is proposed for front-end dc-dc converters used in data centers. The proposed converter is composed of three active switches, two synchronous rectifiers, two clamping capacitors and two inductors. Compared with the conventional buck converters, the proposed converter has higher voltage gain and lower voltage stresses across the active switches. A 300W/1 MHz GaN-based experimental prototype is built and tested to verify the correctness and validity, demonstrating a peak efficiency of 93.3% and full-load efficiency of 90.7%.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123867252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360252
N. Satoh, A. Doi, H. Yamamoto
Power semiconductor devices are progressing towards high-withstand voltage using wide bandgap semiconductor materials as well as having the ability to flow a significant amount of current by multi-parallel integration using the microfabrication technique. A power semiconductor device under a bias voltage applied condition by a scanning probe microscope (SPM) was successfully observed, combined with atomic force microscopy (AFM), Kelvin probe force microscopy (KFM), and scanning capacitance force microscopy (SCFM). Using the SPM analysis, both, a high spatial-resolution and high sensitivity was achieved.
{"title":"Investigation of power semiconductor devices under applying voltage by multi-purpose scanning probe microscope","authors":"N. Satoh, A. Doi, H. Yamamoto","doi":"10.1109/WiPDAAsia49671.2020.9360252","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360252","url":null,"abstract":"Power semiconductor devices are progressing towards high-withstand voltage using wide bandgap semiconductor materials as well as having the ability to flow a significant amount of current by multi-parallel integration using the microfabrication technique. A power semiconductor device under a bias voltage applied condition by a scanning probe microscope (SPM) was successfully observed, combined with atomic force microscopy (AFM), Kelvin probe force microscopy (KFM), and scanning capacitance force microscopy (SCFM). Using the SPM analysis, both, a high spatial-resolution and high sensitivity was achieved.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121420061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360275
Ajit Kanale, B. Baliga
Gallium Nitride FETs have poor short-circuit withstand capability at high DC bus voltages with on-state gate drive voltage. In this paper, the BaSIC(DMM) topology that employs a low voltage Si depletion-mode MOSFET (DMM) in series with source of the GaN FET is demonstrated to suppress the peak short-circuit current and extend the SC withstand time. Experimental results are provided for commercially available 600 V Cascode GaN FETs. The SC withstand time was increased from 0.33 $mu$ s to 4.35 $mu$ s at a drain bias of 400 V with gate bias of 8 V, an improvement by a factor of 13x. Under normal power circuit operating conditions, the BaSIC(DMM) topology produces a 29 % increase in on-resistance and almost no change in switching losses.
{"title":"Achieving Short Circuit Capability for 600 V GaN FETs Using a Gate-Source-Shorted Si Depletion-Mode MOSFET in Series with the Source","authors":"Ajit Kanale, B. Baliga","doi":"10.1109/WiPDAAsia49671.2020.9360275","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360275","url":null,"abstract":"Gallium Nitride FETs have poor short-circuit withstand capability at high DC bus voltages with on-state gate drive voltage. In this paper, the BaSIC(DMM) topology that employs a low voltage Si depletion-mode MOSFET (DMM) in series with source of the GaN FET is demonstrated to suppress the peak short-circuit current and extend the SC withstand time. Experimental results are provided for commercially available 600 V Cascode GaN FETs. The SC withstand time was increased from 0.33 $mu$ s to 4.35 $mu$ s at a drain bias of 400 V with gate bias of 8 V, an improvement by a factor of 13x. Under normal power circuit operating conditions, the BaSIC(DMM) topology produces a 29 % increase in on-resistance and almost no change in switching losses.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129129550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360264
Hajime Takayama, T. Okuda, T. Hikihara
Wide-bandgap power devices are expected to open the way to achieve an integrated power circuit with higher power density. However, the large surge voltage and ringing caused by the fast switching will lose the reliability of the device and increase electromagnetic interference (EMI) problems. In this paper, we propose a digital active gate driver for SiC power MOSFETs. Active gate drive is one of the solutions to achieve high-frequency switching without the above drawbacks. The digital active gate driver is designed based on the architecture of a digital-to-analog converter. The gate-source voltage waveform of the MOSFET is adjusted flexibly with a multi-bit gate signal sequence. It is experimentally verified that the proposed driver suppresses the surge voltage of SiC MOSFET during turn-off.
{"title":"A Study on Suppressing Surge Voltage of SiC MOSFET Using Digital Active Gate Driver","authors":"Hajime Takayama, T. Okuda, T. Hikihara","doi":"10.1109/WiPDAAsia49671.2020.9360264","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360264","url":null,"abstract":"Wide-bandgap power devices are expected to open the way to achieve an integrated power circuit with higher power density. However, the large surge voltage and ringing caused by the fast switching will lose the reliability of the device and increase electromagnetic interference (EMI) problems. In this paper, we propose a digital active gate driver for SiC power MOSFETs. Active gate drive is one of the solutions to achieve high-frequency switching without the above drawbacks. The digital active gate driver is designed based on the architecture of a digital-to-analog converter. The gate-source voltage waveform of the MOSFET is adjusted flexibly with a multi-bit gate signal sequence. It is experimentally verified that the proposed driver suppresses the surge voltage of SiC MOSFET during turn-off.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125213059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360286
Ryosuke Ishido, Yuta Okawauchi, K. Nakahara, Shinya Shirai, Masayoshi Yamamoto
A current/voltage hybrid source gate driver (HGD) has been newly developed to achieve high-speed switching (SW) with no gate overdrive. The HGD is applied to drive SiC MOSFETs in an inductive-load buck converter. The driver successfully reduces the SW transient time and power loss by 18%-43%, depending on operation conditions.
{"title":"Current and Voltage Hybrid Source Gate Driver for Maximizing the Switching Capability of SiC MOSFETs","authors":"Ryosuke Ishido, Yuta Okawauchi, K. Nakahara, Shinya Shirai, Masayoshi Yamamoto","doi":"10.1109/WiPDAAsia49671.2020.9360286","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360286","url":null,"abstract":"A current/voltage hybrid source gate driver (HGD) has been newly developed to achieve high-speed switching (SW) with no gate overdrive. The HGD is applied to drive SiC MOSFETs in an inductive-load buck converter. The driver successfully reduces the SW transient time and power loss by 18%-43%, depending on operation conditions.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131499787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-23DOI: 10.1109/WiPDAAsia49671.2020.9360261
Sayan Mukherjee, S. Kanaga, N. Dasgupta, A. DasGupta
The performances of GaN-based HEMTs as RF power amplifiers are limited by reliability issues such as current collapse. C-doping in GaN buffers reduces butter leakage and improves breakdown voltage but at the same time, introduces acceptor traps leading to current collapse. In this paper, butter trapping effects have been studied for different AlInN/GaN HEMTs in light of drain lag transients. Three different GaN butter structures have been considered. Initially, HEMT having unintentionally doped GaN butter is fabricated, and its experimental results are used for simulation validation. Then, simulation models are extended for HEMTs having C-doped buffers. In the simulations, acceptor type of traps are considered in the doped GaN butter layers. Self-heating effects are also taken into account. The drain lag turn-on mixed-mode 2D TCAD simulations are carried out to analyze the dynamic responses. An optimum butter structure is proposed based on transient results. A two-layer butter having an unintentionally doped GaN layer near the channel and C-doping in the rest shows minimum butter trapping effects. The optimum thickness of the unintentionally doped layer is estimated as 400 nm. Further simulations reveal the impact of C-doped layer thickness and trap concentrations in drain lag transients.
{"title":"optimization of C Doped Buffer Layer to Minimize Current Collapse in A10.83 I n0.17 N/GaN HEMT by Studying Drain Lag Transients","authors":"Sayan Mukherjee, S. Kanaga, N. Dasgupta, A. DasGupta","doi":"10.1109/WiPDAAsia49671.2020.9360261","DOIUrl":"https://doi.org/10.1109/WiPDAAsia49671.2020.9360261","url":null,"abstract":"The performances of GaN-based HEMTs as RF power amplifiers are limited by reliability issues such as current collapse. C-doping in GaN buffers reduces butter leakage and improves breakdown voltage but at the same time, introduces acceptor traps leading to current collapse. In this paper, butter trapping effects have been studied for different AlInN/GaN HEMTs in light of drain lag transients. Three different GaN butter structures have been considered. Initially, HEMT having unintentionally doped GaN butter is fabricated, and its experimental results are used for simulation validation. Then, simulation models are extended for HEMTs having C-doped buffers. In the simulations, acceptor type of traps are considered in the doped GaN butter layers. Self-heating effects are also taken into account. The drain lag turn-on mixed-mode 2D TCAD simulations are carried out to analyze the dynamic responses. An optimum butter structure is proposed based on transient results. A two-layer butter having an unintentionally doped GaN layer near the channel and C-doping in the rest shows minimum butter trapping effects. The optimum thickness of the unintentionally doped layer is estimated as 400 nm. Further simulations reveal the impact of C-doped layer thickness and trap concentrations in drain lag transients.","PeriodicalId":432666,"journal":{"name":"2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130338940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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