Matthias Beckert, M. Neukirchner, R. Ernst, Stefan M. Petters
Virtualization techniques for hard real-time systems typically employ TDMA scheduling to achieve temporal isolation among partitions. The processing of user-level interrupt handlers is only performed within appropriate time slots, thus significantly increasing interrupt latencies. We propose a novel approach permitting execution of user-level interrupt handlers during time slots of other partitions hence reducing interrupt latencies. Sufficient temporal independence among partitions, as required by safety standards, is maintained through a monitoring mechanism, which bounds the interference of user-level interrupt handlers in other partitions. We show correctness of the approach and evaluate its performance in a hypervisor implementation.
{"title":"Sufficient temporal independence and improved interrupt latencies in a real-time hypervisor","authors":"Matthias Beckert, M. Neukirchner, R. Ernst, Stefan M. Petters","doi":"10.1145/2593069.2593222","DOIUrl":"https://doi.org/10.1145/2593069.2593222","url":null,"abstract":"Virtualization techniques for hard real-time systems typically employ TDMA scheduling to achieve temporal isolation among partitions. The processing of user-level interrupt handlers is only performed within appropriate time slots, thus significantly increasing interrupt latencies. We propose a novel approach permitting execution of user-level interrupt handlers during time slots of other partitions hence reducing interrupt latencies. Sufficient temporal independence among partitions, as required by safety standards, is maintained through a monitoring mechanism, which bounds the interference of user-level interrupt handlers in other partitions. We show correctness of the approach and evaluate its performance in a hypervisor implementation.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130647968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Runtime monitoring of aging effects in pipeline circuits is the key to dynamic reliability management techniques which can maximize the performance and energy-efficiency under a reliability envelope without imposing worst-case margin. The existing monitoring techniques are, however, severely limited: for sensor-based techniques, monitoring accuracy is significantly compromised due to the mismatches in aging conditions between sensors and the target circuits, as well as random variation of aging effects; for in-situ techniques, measurement results are sensitive to environmental variations during test phases, also severely reducing monitoring accuracy. We propose a new technique that enables accurate in-situ aging monitoring even under large environmental variations by (i) scaling the supply voltage for temperature-insensitive delay and (ii) reconfiguring target paths into ring oscillators, whose oscillation periods are measured and compared to pre-aging measurement to estimate aging-induced delay degradations. With additional accuracy-improving strategies, the technique achieves highly-accurate monitoring with an error of 15.5% across the temperature variations in self-test phases from 0°C to 80°C, exhibiting >30× improvement in accuracy as compared to the conventional technique operating at nominal supply voltage.
{"title":"Robust and in-situ self-testing technique for monitoring device aging effects in pipeline circuits","authors":"Jiangyi Li, Mingoo Seok","doi":"10.1145/2593069.2593205","DOIUrl":"https://doi.org/10.1145/2593069.2593205","url":null,"abstract":"Runtime monitoring of aging effects in pipeline circuits is the key to dynamic reliability management techniques which can maximize the performance and energy-efficiency under a reliability envelope without imposing worst-case margin. The existing monitoring techniques are, however, severely limited: for sensor-based techniques, monitoring accuracy is significantly compromised due to the mismatches in aging conditions between sensors and the target circuits, as well as random variation of aging effects; for in-situ techniques, measurement results are sensitive to environmental variations during test phases, also severely reducing monitoring accuracy. We propose a new technique that enables accurate in-situ aging monitoring even under large environmental variations by (i) scaling the supply voltage for temperature-insensitive delay and (ii) reconfiguring target paths into ring oscillators, whose oscillation periods are measured and compared to pre-aging measurement to estimate aging-induced delay degradations. With additional accuracy-improving strategies, the technique achieves highly-accurate monitoring with an error of 15.5% across the temperature variations in self-test phases from 0°C to 80°C, exhibiting >30× improvement in accuracy as compared to the conventional technique operating at nominal supply voltage.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126497637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chi-Yuan Liu, H. Chiang, Yao-Wen Chang, J. H. Jiang
EUV flare and CMP metal thickness are two main manufacturability concerns for nanometer process technology. The two dummification objectives, however, are conflicting with each other in nature, but existing works only tackle them separately, leading to problem-prone solutions because optimizing one would deteriorate the other. This paper presents the first work that simultaneously considers both concerns during manufacturability optimization. Given a system's point spread function, our proposed method first finds an initial solution with better-than-state-of-the-art EUV flare uniformity, then followed by gradient-guided optimization to iteratively refine density uniformity. Experimental results show the effectiveness of our method.
{"title":"Simultaneous EUV flare variation minimization and CMP control with coupling-aware dummification","authors":"Chi-Yuan Liu, H. Chiang, Yao-Wen Chang, J. H. Jiang","doi":"10.1145/2593069.2593215","DOIUrl":"https://doi.org/10.1145/2593069.2593215","url":null,"abstract":"EUV flare and CMP metal thickness are two main manufacturability concerns for nanometer process technology. The two dummification objectives, however, are conflicting with each other in nature, but existing works only tackle them separately, leading to problem-prone solutions because optimizing one would deteriorate the other. This paper presents the first work that simultaneously considers both concerns during manufacturability optimization. Given a system's point spread function, our proposed method first finds an initial solution with better-than-state-of-the-art EUV flare uniformity, then followed by gradient-guided optimization to iteratively refine density uniformity. Experimental results show the effectiveness of our method.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128114422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. Kozhikkottu, Abhisek Pan, Vijay S. Pai, S. Dey, A. Raghunathan
Multithreaded programs are commonly written and optimized for homogeneous multi-core processors assuming equal performance from all the cores. This assumption greatly simplifies the partitioning and balancing of an application's workload across threads; however, it no longer holds when the frequencies of the cores differ due to within-die variations, leading to a degradation in performance. We observe that, in addition to the frequency of the core that it executes on, the performance of a thread is also dependent on the share of shared system resources, such as last-level cache, that it receives. We propose variation-aware cache partitioning as an approach to redress the variation-induced imbalance in the execution times of threads, thereby improving the performance of multi-threaded programs. We discuss the challenges involved in realizing our proposal, including synchronization (e.g., barriers) across threads, which results in faster threads being limited by slower threads, the complex and non-linear relationship between a thread's performance and the cache capacity allocated to it, and the fact that different program phases, can respond quite differently to varying cache capacity. We propose a runtime scheme to perform spatio-temporal cache partitioning while considering both chip characteristics (frequency variations) and program characteristics. We evaluate the proposed technique by applying it to an ensemble of variation-impacted multi-cores executing multi-threaded programs from the PAR-SEC and SPEC-OMP suites, and demonstrate that it results in an average performance improvement of 15% by mitigating the impact of frequency variations.
{"title":"Variation aware cache partitioning for multithreaded programs","authors":"V. Kozhikkottu, Abhisek Pan, Vijay S. Pai, S. Dey, A. Raghunathan","doi":"10.1145/2593069.2593240","DOIUrl":"https://doi.org/10.1145/2593069.2593240","url":null,"abstract":"Multithreaded programs are commonly written and optimized for homogeneous multi-core processors assuming equal performance from all the cores. This assumption greatly simplifies the partitioning and balancing of an application's workload across threads; however, it no longer holds when the frequencies of the cores differ due to within-die variations, leading to a degradation in performance. We observe that, in addition to the frequency of the core that it executes on, the performance of a thread is also dependent on the share of shared system resources, such as last-level cache, that it receives. We propose variation-aware cache partitioning as an approach to redress the variation-induced imbalance in the execution times of threads, thereby improving the performance of multi-threaded programs. We discuss the challenges involved in realizing our proposal, including synchronization (e.g., barriers) across threads, which results in faster threads being limited by slower threads, the complex and non-linear relationship between a thread's performance and the cache capacity allocated to it, and the fact that different program phases, can respond quite differently to varying cache capacity. We propose a runtime scheme to perform spatio-temporal cache partitioning while considering both chip characteristics (frequency variations) and program characteristics. We evaluate the proposed technique by applying it to an ensemble of variation-impacted multi-cores executing multi-threaded programs from the PAR-SEC and SPEC-OMP suites, and demonstrate that it results in an average performance improvement of 15% by mitigating the impact of frequency variations.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125432545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Low-density parity-check (LDPC) is widely accepted as the baseline error-correction codes offering strong error-correcting capability for future NAND flash-based SSDs. However, LDPC incurs read performance overhead because of its complex decoding procedure. To mitigate such overhead, we propose the error-correcting cache (EC-Cache) that exploits the “error locality” of NAND flash. Error locality means that the majority of errors in reads to the same NAND flash page appear in the same positions until the page is erased. By caching detected errors, EC-Cache can correct a significant portion of errors present in a requested flash page before the associated LDPC decoding process begins. EC-Cache can greatly speed up LDPC decoding because LDPC's latency is directly correlated to the number of errors present in the input data. Experimental results show that EC-Cache achieves up to 2.6× SSD read performance gain.
{"title":"EC-Cache: Exploiting error locality to optimize LDPC in NAND flash-based SSDs","authors":"Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li","doi":"10.1145/2593069.2593130","DOIUrl":"https://doi.org/10.1145/2593069.2593130","url":null,"abstract":"Low-density parity-check (LDPC) is widely accepted as the baseline error-correction codes offering strong error-correcting capability for future NAND flash-based SSDs. However, LDPC incurs read performance overhead because of its complex decoding procedure. To mitigate such overhead, we propose the error-correcting cache (EC-Cache) that exploits the “error locality” of NAND flash. Error locality means that the majority of errors in reads to the same NAND flash page appear in the same positions until the page is erased. By caching detected errors, EC-Cache can correct a significant portion of errors present in a requested flash page before the associated LDPC decoding process begins. EC-Cache can greatly speed up LDPC decoding because LDPC's latency is directly correlated to the number of errors present in the input data. Experimental results show that EC-Cache achieves up to 2.6× SSD read performance gain.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125708688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tianshu Wei, Taeyoung Kim, Sangyoung Park, Qidong Zhu, S. Tan, N. Chang, S. Ula, Mehdi Maasoumy
As the building stock consumes 40% of the U.S. primary energy consumption, it is critically important to improve building energy efficiency. This involves reducing the total energy consumption of buildings, reducing the peak energy demand, and leveraging renewable energy sources, etc. To achieve such goals, hybrid energy supply has becoming popular, where multiple energy sources such as grid electricity, on-site fuel cell generators, solar, wind, and battery storage are scheduled together to improve energy efficiency. In this work, we focus on the application and management of battery storage for energy-efficient buildings. We will first introduce a system-level approach to co-schedule the usage of battery storage (in addition to grid electricity) with the control of building HVAC (heating, ventilation, and air conditioning) system, to reduce the total building energy cost, including the electricity consumption charge, the peak demand charge, and the battery cost. Then, in a separate formulation, we will introduce another system-level study to reduce the energy cost of EV charging and other fixed building energy load through the usage of battery storage and solar PV. Finally, we will present an ARM processor based programmable embedded battery management system (BMS), which monitors battery status, controls charging and discharging at the circuit level, and provides battery protection. The system also works with off-the-shelf battery management IC (Texas Instrument BMS sensor IC) from industry. Comparing to conventional BMS, this software module based BMS is a more suitable solution for energy efficient buildings due to its high flexibility, scalability, and reusability. We will introduce an industrial building testbed with battery storage and solar PV at the University of California, Riverside, and present initial field tests and simulation results for above approaches.
由于建筑消耗了美国40%的一次能源消耗，因此提高建筑能源效率至关重要。这包括减少建筑物的总能耗，减少高峰能源需求，以及利用可再生能源等。为了实现这一目标，混合能源供应开始流行，其中多种能源，如电网电力，现场燃料电池发电机，太阳能，风能和电池存储一起安排，以提高能源效率。在本工作中，我们重点研究了节能建筑中电池储能的应用和管理。我们将首先引入一种系统级的方法，将电池储能(除电网电力外)的使用与建筑暖通空调(采暖、通风和空调)系统的控制共同调度，以降低建筑总能源成本，包括电力消耗费用、峰值需求费用和电池成本。然后，在一个单独的公式中，我们将介绍另一个系统层面的研究，通过使用电池存储和太阳能光伏来降低电动汽车充电和其他固定建筑能源负荷的能源成本。最后，我们将介绍一个基于ARM处理器的可编程嵌入式电池管理系统(BMS)，该系统可以监控电池状态，控制电路级的充放电，并提供电池保护。该系统还可与业界现成的电池管理IC(德州仪器BMS传感器IC)配合使用。与传统的管理管理系统相比，这种基于软件模块的管理管理系统具有较高的灵活性、可扩展性和可重用性，更适合节能建筑。我们将在加州大学河滨分校(University of California, Riverside)引入一个具有电池存储和太阳能光伏的工业建筑测试平台，并介绍上述方法的初步现场测试和模拟结果。
{"title":"Battery management and application for energy-efficient buildings","authors":"Tianshu Wei, Taeyoung Kim, Sangyoung Park, Qidong Zhu, S. Tan, N. Chang, S. Ula, Mehdi Maasoumy","doi":"10.1145/2593069.2596670","DOIUrl":"https://doi.org/10.1145/2593069.2596670","url":null,"abstract":"As the building stock consumes 40% of the U.S. primary energy consumption, it is critically important to improve building energy efficiency. This involves reducing the total energy consumption of buildings, reducing the peak energy demand, and leveraging renewable energy sources, etc. To achieve such goals, hybrid energy supply has becoming popular, where multiple energy sources such as grid electricity, on-site fuel cell generators, solar, wind, and battery storage are scheduled together to improve energy efficiency. In this work, we focus on the application and management of battery storage for energy-efficient buildings. We will first introduce a system-level approach to co-schedule the usage of battery storage (in addition to grid electricity) with the control of building HVAC (heating, ventilation, and air conditioning) system, to reduce the total building energy cost, including the electricity consumption charge, the peak demand charge, and the battery cost. Then, in a separate formulation, we will introduce another system-level study to reduce the energy cost of EV charging and other fixed building energy load through the usage of battery storage and solar PV. Finally, we will present an ARM processor based programmable embedded battery management system (BMS), which monitors battery status, controls charging and discharging at the circuit level, and provides battery protection. The system also works with off-the-shelf battery management IC (Texas Instrument BMS sensor IC) from industry. Comparing to conventional BMS, this software module based BMS is a more suitable solution for energy efficient buildings due to its high flexibility, scalability, and reusability. We will introduce an industrial building testbed with battery storage and solar PV at the University of California, Riverside, and present initial field tests and simulation results for above approaches.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121554705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a comprehensive analysis of radiation-induced soft errors of SRAMs designed in SOI FinFET technology. For this purpose, we propose a cross layer approach starting from a 3D simulation of particle interactions in FinFET structures up to circuit level analysis by considering the layout of the memory array. This approach enables us to consider the effect of different factors such as supply voltage and process variation on Soft Error Rate (SER) of FinFET SRAM memory arrays. Our analysis shows that proton-induced soft errors are becoming important and comparable to the SER induced by alpha-particles especially for low supply voltages (low power applications). Moreover, we observe that the ratio of Multiple Bit Upset (MBU) to Single Event Upset (SEU) for alpha-particle radiation is much higher than that of proton.
{"title":"Radiation-induced soft error analysis of SRAMs in SOI FinFET technology: A device to circuit approach","authors":"S. Kiamehr, T. Osiecki, M. Tahoori, S. Nassif","doi":"10.1145/2593069.2593196","DOIUrl":"https://doi.org/10.1145/2593069.2593196","url":null,"abstract":"This paper presents a comprehensive analysis of radiation-induced soft errors of SRAMs designed in SOI FinFET technology. For this purpose, we propose a cross layer approach starting from a 3D simulation of particle interactions in FinFET structures up to circuit level analysis by considering the layout of the memory array. This approach enables us to consider the effect of different factors such as supply voltage and process variation on Soft Error Rate (SER) of FinFET SRAM memory arrays. Our analysis shows that proton-induced soft errors are becoming important and comparable to the SER induced by alpha-particles especially for low supply voltages (low power applications). Moreover, we observe that the ratio of Multiple Bit Upset (MBU) to Single Event Upset (SEU) for alpha-particle radiation is much higher than that of proton.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131450515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Phase change memory is becoming one of the most promising candidates to replace DRAM as main memory in deep silicon regime. Multi-level cell (MLC) PCM outperforms single level cell (SLC) in terms of capacity while suffering from a weaker cell endurance. Wear leveling strategies are proposed to enhance the endurance but encounters more challenges with the aggravating process variation. Due to endurance variations, balanced write traffic cannot fully exploit the PCM endurance since the weak parts will be worn out sooner than others. In this work, considering process variation, we propose an SLC-enabled wear leveling scheme through dynamic and adaptive mode transformation from MLC to SLC. Instead of redistributing write operations, the proposed scheme dynamically transforms weak and write-dense parts into SLC mode for endurance benefits. The experimental results show that the proposed scheme can improve the endurance by 215% with 4% storage overhead while maintaining the capacity advantage of MLC, compared with the most related work.
{"title":"SLC-enabled wear leveling for MLC PCM considering process variation","authors":"Mengying Zhao, Lei Jiang, Youtao Zhang, C. Xue","doi":"10.1145/2593069.2593217","DOIUrl":"https://doi.org/10.1145/2593069.2593217","url":null,"abstract":"Phase change memory is becoming one of the most promising candidates to replace DRAM as main memory in deep silicon regime. Multi-level cell (MLC) PCM outperforms single level cell (SLC) in terms of capacity while suffering from a weaker cell endurance. Wear leveling strategies are proposed to enhance the endurance but encounters more challenges with the aggravating process variation. Due to endurance variations, balanced write traffic cannot fully exploit the PCM endurance since the weak parts will be worn out sooner than others. In this work, considering process variation, we propose an SLC-enabled wear leveling scheme through dynamic and adaptive mode transformation from MLC to SLC. Instead of redistributing write operations, the proposed scheme dynamically transforms weak and write-dense parts into SLC mode for endurance benefits. The experimental results show that the proposed scheme can improve the endurance by 215% with 4% storage overhead while maintaining the capacity advantage of MLC, compared with the most related work.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132054351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three-dimensional (3D) integration technology has been proposed as a promising technology to provide small footprint, reduced wire-length, and the capability of heterogeneous integration. In particular, 3D IC is a good candidate to address the design issues in conventional analog/digital mixed-signal IC designs. In this work, we focus on modeling and analyzing the impacts of through silicon vias (TSVs) on mixed-signal ICs. Based on the analysis, a set of design methodologies for 3D mixed-signal ICs are proposed. The design methodologies are verified with a case study, in which a 12-bit successive approximation register analog-to-digital converter (SAR ADC) is re-designed by partitioning it into three stacked layers for 3D integration. The experimental results show that, compared to the traditional 2D counterpart, our 3D SAR ADC with optimized TSV placement can achieve significant area and power reduction, and performance improvement. Specifically, due to the isolation of substrate noise disturbance in our 3D design, the signal-to-noise-plus-distortion ratio (SNDR) is improved from 68.74 dB to 74.12 dB.
三维集成技术具有占地面积小、缩短线长和异构集成能力等优点，是一种很有前途的集成技术。特别是，3D集成电路是解决传统模拟/数字混合信号集成电路设计问题的一个很好的候选人。在这项工作中，我们专注于建模和分析透硅过孔(tsv)对混合信号集成电路的影响。在此基础上，提出了一套三维混合信号集成电路的设计方法。通过一个案例研究验证了设计方法，其中通过将12位连续逼近寄存器模数转换器(SAR ADC)划分为三个堆叠层进行3D集成，重新设计了该设计方法。实验结果表明，与传统的2D SAR ADC相比，优化了TSV布局的3D SAR ADC可以显著减少面积和功耗，并提高性能。具体来说，由于在我们的3D设计中隔离了衬底噪声干扰，信噪比(SNDR)从68.74 dB提高到74.12 dB。
{"title":"Design methodologies for 3D mixed signal integrated circuits: A practical 12-bit SAR ADC design case","authors":"Wulong Liu, Guoqing Chen, Xuefeng Han, Yu Wang, Yuan Xie, Huazhong Yang","doi":"10.1145/2593069.2593122","DOIUrl":"https://doi.org/10.1145/2593069.2593122","url":null,"abstract":"Three-dimensional (3D) integration technology has been proposed as a promising technology to provide small footprint, reduced wire-length, and the capability of heterogeneous integration. In particular, 3D IC is a good candidate to address the design issues in conventional analog/digital mixed-signal IC designs. In this work, we focus on modeling and analyzing the impacts of through silicon vias (TSVs) on mixed-signal ICs. Based on the analysis, a set of design methodologies for 3D mixed-signal ICs are proposed. The design methodologies are verified with a case study, in which a 12-bit successive approximation register analog-to-digital converter (SAR ADC) is re-designed by partitioning it into three stacked layers for 3D integration. The experimental results show that, compared to the traditional 2D counterpart, our 3D SAR ADC with optimized TSV placement can achieve significant area and power reduction, and performance improvement. Specifically, due to the isolation of substrate noise disturbance in our 3D design, the signal-to-noise-plus-distortion ratio (SNDR) is improved from 68.74 dB to 74.12 dB.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134177827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai
In digital microfluidic biochips, cross-contamination of different biomolecule droplets is a major issue. Washing operations are introduced to clean the cross-contamination sites. Existing works have oversimplified assumptions on the washing behavior, which either assume unrealistic infinite washing capacity, or ignore the execution time constraint and/or the routing conflicts between functional and washing droplets. This paper presents the first practical droplet routing flow, which considers realistic issues including the finite washing capacity constraint, and the routing conflicts between washing and functional droplets. Effectiveness of the presented method are validated by real-life biochemical applications.
{"title":"Practical functional and washing droplet routing for cross-contamination avoidance in digital microfluidic biochips","authors":"Qin Wang, Yiren Shen, Hailong Yao, Tsung-Yi Ho, Yici Cai","doi":"10.1145/2593069.2593189","DOIUrl":"https://doi.org/10.1145/2593069.2593189","url":null,"abstract":"In digital microfluidic biochips, cross-contamination of different biomolecule droplets is a major issue. Washing operations are introduced to clean the cross-contamination sites. Existing works have oversimplified assumptions on the washing behavior, which either assume unrealistic infinite washing capacity, or ignore the execution time constraint and/or the routing conflicts between functional and washing droplets. This paper presents the first practical droplet routing flow, which considers realistic issues including the finite washing capacity constraint, and the routing conflicts between washing and functional droplets. Effectiveness of the presented method are validated by real-life biochemical applications.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130826771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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