Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579872
I. Kammoun, A. Cipriano, J. Belfiore
We consider single-input multiple-output non-coherent communication over the flat fading Rayleigh channel. At the transmitter we propose an architecture based on the unitary space-time codes obtained via exponential mapping (Kammoun, I and Belfiore, J, 2003). At the receiver we implemented a simple low-complexity decoding algorithm inspired from the optimal GLRT decoder. The performance of the sub-optimal decoder is very close to the optimal GLRT decoder. The unitary non-coherent codes are considered as points over the Grassmann manifold G/sub T, M/ (/spl Copf/).
{"title":"A non-coherent SIMO architecture based on Grassmann codes","authors":"I. Kammoun, A. Cipriano, J. Belfiore","doi":"10.1109/SIPS.2005.1579872","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579872","url":null,"abstract":"We consider single-input multiple-output non-coherent communication over the flat fading Rayleigh channel. At the transmitter we propose an architecture based on the unitary space-time codes obtained via exponential mapping (Kammoun, I and Belfiore, J, 2003). At the receiver we implemented a simple low-complexity decoding algorithm inspired from the optimal GLRT decoder. The performance of the sub-optimal decoder is very close to the optimal GLRT decoder. The unitary non-coherent codes are considered as points over the Grassmann manifold G/sub T, M/ (/spl Copf/).","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114883645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579897
F. Lamberti, B. Montrucchio, A. Gamba
Vascularization is defined as the sprouting of new blood vessels by expansion of the endothelium by proliferation, migration and remodeling. Vascularization is fundamental to healing, reproduction as well as embryonic development. It also plays a key role in tumor growth, tumor metastasis and other pathological processes. Understanding biological phenomena driving the creation of vascular structures is therefore essential for clinical treatment of cancer and other vascularization-related diseases. Recently, an analytical model capable of mimicking the process of in-vitro vascular network creation from randomly seeded endothelial cells has also been proposed. This paper presents the development of a novel neural network based segmentation technique working on phase contrast microscopy snap photographs of cultured endothelial cells which allows for cell structures geometry quantitative analysis thus constituting a key instrument in the development of computerized tools for vascularization parameters measurement as well as supporting also analytical model deployment and validation.
{"title":"Quantitative analysis of vascular structures geometry using neural networks","authors":"F. Lamberti, B. Montrucchio, A. Gamba","doi":"10.1109/SIPS.2005.1579897","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579897","url":null,"abstract":"Vascularization is defined as the sprouting of new blood vessels by expansion of the endothelium by proliferation, migration and remodeling. Vascularization is fundamental to healing, reproduction as well as embryonic development. It also plays a key role in tumor growth, tumor metastasis and other pathological processes. Understanding biological phenomena driving the creation of vascular structures is therefore essential for clinical treatment of cancer and other vascularization-related diseases. Recently, an analytical model capable of mimicking the process of in-vitro vascular network creation from randomly seeded endothelial cells has also been proposed. This paper presents the development of a novel neural network based segmentation technique working on phase contrast microscopy snap photographs of cultured endothelial cells which allows for cell structures geometry quantitative analysis thus constituting a key instrument in the development of computerized tools for vascularization parameters measurement as well as supporting also analytical model deployment and validation.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114976736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579835
R. Hossain, M. Wesseling, C. Leopold
Within a recent project at Siemens Communication, we developed a new programming concept called virtual radio engine (VRE), with the goal to provide an efficient development environment for software defined radio (SDR) applications. VRE separates the development process into two steps: first, the application is described in a hardware-independent way using the VRE programming language, and then the implementation is done (to a great part) automatically by the VRE code generator system. As the hardware underlying SDR requires parallel architectures of different kinds to achieve the required high performance within a low power consumption budget, hardware-specific requirements are excluded from the VRE program. Instead, a separate hardware description file supplements the program. Therefore, the application can be described without any prior knowledge of the target hardware, and the same program can be implemented on different parallel hardware platforms. This paper concentrates on the VRE programming language and the graphic representation of VRE programs using Simulink. Special emphasis is given to the representation of different types of control flow.
{"title":"Application description concept with system level hardware abstraction","authors":"R. Hossain, M. Wesseling, C. Leopold","doi":"10.1109/SIPS.2005.1579835","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579835","url":null,"abstract":"Within a recent project at Siemens Communication, we developed a new programming concept called virtual radio engine (VRE), with the goal to provide an efficient development environment for software defined radio (SDR) applications. VRE separates the development process into two steps: first, the application is described in a hardware-independent way using the VRE programming language, and then the implementation is done (to a great part) automatically by the VRE code generator system. As the hardware underlying SDR requires parallel architectures of different kinds to achieve the required high performance within a low power consumption budget, hardware-specific requirements are excluded from the VRE program. Instead, a separate hardware description file supplements the program. Therefore, the application can be described without any prior knowledge of the target hardware, and the same program can be implemented on different parallel hardware platforms. This paper concentrates on the VRE programming language and the graphic representation of VRE programs using Simulink. Special emphasis is given to the representation of different types of control flow.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123661689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579923
Jung-Yeol Oh, M. Lim
This paper proposes the modified radix-2/sup 4/ and the radix-4/sup 2/ FFT algorithms and efficient pipeline FFT architectures based on those algorithms for OFDM systems. The proposed pipeline FFT architectures have the same number of multipliers as that of the conventional R2/sup 2/SDF and R4SDC. However, the multiplication complexity and the ROMs for storing twiddle factors could be reduced by more than 30% and 50% respectively by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 /spl mu/m CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area and power efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.
{"title":"Area and power efficient pipeline FFT algorithm","authors":"Jung-Yeol Oh, M. Lim","doi":"10.1109/SIPS.2005.1579923","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579923","url":null,"abstract":"This paper proposes the modified radix-2/sup 4/ and the radix-4/sup 2/ FFT algorithms and efficient pipeline FFT architectures based on those algorithms for OFDM systems. The proposed pipeline FFT architectures have the same number of multipliers as that of the conventional R2/sup 2/SDF and R4SDC. However, the multiplication complexity and the ROMs for storing twiddle factors could be reduced by more than 30% and 50% respectively by replacing one half of the programmable multipliers by the newly proposed CSD constant multipliers. From the synthesis simulations of a standard 0.35 /spl mu/m CMOS SAMSUNG process, a proposed CSD constant complex multiplier achieved more than 60% area and power efficiency when compared to the conventional programmable complex multiplier. This promoted efficiency could be used to the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117187672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579878
M. Elassal, A. Baker, M. Bayoumi
In this paper we present low power maximum a posteriori (MAP) decoder architectures using dual supply voltages. The architecture leverages an application specific integrated circuits (ASIC) structure, where the architecture components that require a higher performance are powered from a high supply voltages V/sub ddH/, and the less demanding components are powered from a low supply voltage V/sub ddL/. Salient features of this architecture include: (a) high level of parallelism, (b) reduced power consumption without affecting the architecture performance, and (c) a tradeoff between the decoding time delay and the number of state metric banks, branch metric banks, and state metric update kernels respectively. The power consumption reduction of the dual-supply voltage over the single-supply voltage has been estimated and the memory access frequencies as well. The proposed architecture achieves approximate 35-40% power reduction from the single-supply architecture.
{"title":"A low power VLSI design paradigm for iterative decoders","authors":"M. Elassal, A. Baker, M. Bayoumi","doi":"10.1109/SIPS.2005.1579878","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579878","url":null,"abstract":"In this paper we present low power maximum a posteriori (MAP) decoder architectures using dual supply voltages. The architecture leverages an application specific integrated circuits (ASIC) structure, where the architecture components that require a higher performance are powered from a high supply voltages V/sub ddH/, and the less demanding components are powered from a low supply voltage V/sub ddL/. Salient features of this architecture include: (a) high level of parallelism, (b) reduced power consumption without affecting the architecture performance, and (c) a tradeoff between the decoding time delay and the number of state metric banks, branch metric banks, and state metric update kernels respectively. The power consumption reduction of the dual-supply voltage over the single-supply voltage has been estimated and the memory access frequencies as well. The proposed architecture achieves approximate 35-40% power reduction from the single-supply architecture.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123993469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579909
N. Hurley, N. Harte, C. Fearon, S. Rickard
This paper presents preliminary work on a hardware implementation of a source separation algorithm employing time-frequency masking methods. DUET (degenerate unmixing estimation technique) has previously been shown to achieve excellent source separation in real time in software. The current work is a move towards a hardware realization of DUET that will allow integration of the algorithm into consumer devices. Initial stages involve investigating the performance of DUET when implemented in fixed-point arithmetic and a consideration of algorithmic changes to make DUET more amenable to implementation on a DSP processor. Performance is compared for floating-point and fixed-point implementations. A weighted K-means clustering algorithm is presented as an alternative to gradient descent methods for peak tracking and demonstrated to achieve excellent performance without adversely affecting computational load. Preliminary performance figures are given for an implementation on a TMS320VC5510 DSK.
{"title":"Blind source separation of speech in hardware","authors":"N. Hurley, N. Harte, C. Fearon, S. Rickard","doi":"10.1109/SIPS.2005.1579909","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579909","url":null,"abstract":"This paper presents preliminary work on a hardware implementation of a source separation algorithm employing time-frequency masking methods. DUET (degenerate unmixing estimation technique) has previously been shown to achieve excellent source separation in real time in software. The current work is a move towards a hardware realization of DUET that will allow integration of the algorithm into consumer devices. Initial stages involve investigating the performance of DUET when implemented in fixed-point arithmetic and a consideration of algorithmic changes to make DUET more amenable to implementation on a DSP processor. Performance is compared for floating-point and fixed-point implementations. A weighted K-means clustering algorithm is presented as an alternative to gradient descent methods for peak tracking and demonstrated to achieve excellent performance without adversely affecting computational load. Preliminary performance figures are given for an implementation on a TMS320VC5510 DSK.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125030876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579940
M. Elnamaky, M. Ahmed-Ouameur, D. Massicotte
The estimation of channel delays along with their respective complex channel coefficients of different users constitutes the first stage in the detection process at the receiving base station in a DS-CDMA communication system. A multiuser steepest Wiener LMS (MS-WLMS) like structure algorithm along with smoothing/prediction filters to improve tracking quality is suggested. This paper presents a customized and fixed-point hardware parallel implementation of the proposed algorithm for WCDMA uplink transmission in third generation (3G) wireless system. Additional speedup in the execution time is achieved over the well known maximum likelihood channel estimation for DS-CDMA. It is also shown that our solution could achieve the real-time requirements of 3GPP standards applied in WCDMA systems.
{"title":"FPGA implementation for channel estimations based on Wiener LMS for DS-CDMA","authors":"M. Elnamaky, M. Ahmed-Ouameur, D. Massicotte","doi":"10.1109/SIPS.2005.1579940","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579940","url":null,"abstract":"The estimation of channel delays along with their respective complex channel coefficients of different users constitutes the first stage in the detection process at the receiving base station in a DS-CDMA communication system. A multiuser steepest Wiener LMS (MS-WLMS) like structure algorithm along with smoothing/prediction filters to improve tracking quality is suggested. This paper presents a customized and fixed-point hardware parallel implementation of the proposed algorithm for WCDMA uplink transmission in third generation (3G) wireless system. Additional speedup in the execution time is achieved over the well known maximum likelihood channel estimation for DS-CDMA. It is also shown that our solution could achieve the real-time requirements of 3GPP standards applied in WCDMA systems.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128977765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579905
Y. Hsiao, Cheng-Long Chuang, Chun-Hung Mo, Cheng-Chih Chien, Joe-Air Jiang
In this paper, a novel cut-strategy is presented for solving the problems of multiple biosequence alignment. Sequence comparison is the most important primitive operation for analyzing of the bioinformatics data. The most fundamental method for alignment of several biosequences is the dynamic programming (DP) technique. The DP method is capable of finding optimal alignments for a set of sequences. However, when the length of the sequences increased, the DP method is impracticable due to the computational complexity is extremely high. Therefore, a new method is proposed in this paper for reducing the computational cost of the DP technique. By recursively finding the structural features of the biosequences, the proposed method can divide the biosequences into very small alignment problem, which can be directly solved by DP, or other applicable methods that can produce the results of alignment faster. By utilizing the object-oriented programming technique, the proposed method also provides low memory space consumption during execution. Moreover, the proposed algorithm has been implemented in an x86 demonstration program, and compares the effective and efficient performance with other known method.
{"title":"A novel statistical cut-strategy for DP-based multiple biosequence alignment","authors":"Y. Hsiao, Cheng-Long Chuang, Chun-Hung Mo, Cheng-Chih Chien, Joe-Air Jiang","doi":"10.1109/SIPS.2005.1579905","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579905","url":null,"abstract":"In this paper, a novel cut-strategy is presented for solving the problems of multiple biosequence alignment. Sequence comparison is the most important primitive operation for analyzing of the bioinformatics data. The most fundamental method for alignment of several biosequences is the dynamic programming (DP) technique. The DP method is capable of finding optimal alignments for a set of sequences. However, when the length of the sequences increased, the DP method is impracticable due to the computational complexity is extremely high. Therefore, a new method is proposed in this paper for reducing the computational cost of the DP technique. By recursively finding the structural features of the biosequences, the proposed method can divide the biosequences into very small alignment problem, which can be directly solved by DP, or other applicable methods that can produce the results of alignment faster. By utilizing the object-oriented programming technique, the proposed method also provides low memory space consumption during execution. Moreover, the proposed algorithm has been implemented in an x86 demonstration program, and compares the effective and efficient performance with other known method.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128850045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579881
R. Aguilar-Ponce, J. Tessier, A. Baker, C. Emmela, J. Das, J. L. Tecpanecatl-Xihuitl, A. Kumar, M. Bayoumi
Object detection is a crucial step in visual surveillance. Traditionally, object detection has been performed purely in software in surveillance systems. The problem of object detection, however, becomes critical in the upcoming wireless visual sensors because of size and power constraints. The need for low-power, small size, hardware implementations is greatly felt. This paper introduces a VLSI architecture for Wronskian change detector (WCD). Object detection is done through background subtraction. WCD offers regularity, low complexity and accuracy as well as global illumination changes independency. WCD can be employed in automated visual surveillance on buildings and adjacent parking lots. WCD replaces each pixel by a vector containing luminance value of the pixel and its surrounding area. A linear dependency test is applied to each vector to determine if a change has occurred. WCD is mapped into a 12-processing element array with a fixed window value of 3/spl times/3. Design of each processing element is discussed in detail. Based on extensive search, no VLSI implementation of WCD has been reported previously.
{"title":"VLSI architecture for an object change detector for visual sensors","authors":"R. Aguilar-Ponce, J. Tessier, A. Baker, C. Emmela, J. Das, J. L. Tecpanecatl-Xihuitl, A. Kumar, M. Bayoumi","doi":"10.1109/SIPS.2005.1579881","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579881","url":null,"abstract":"Object detection is a crucial step in visual surveillance. Traditionally, object detection has been performed purely in software in surveillance systems. The problem of object detection, however, becomes critical in the upcoming wireless visual sensors because of size and power constraints. The need for low-power, small size, hardware implementations is greatly felt. This paper introduces a VLSI architecture for Wronskian change detector (WCD). Object detection is done through background subtraction. WCD offers regularity, low complexity and accuracy as well as global illumination changes independency. WCD can be employed in automated visual surveillance on buildings and adjacent parking lots. WCD replaces each pixel by a vector containing luminance value of the pixel and its surrounding area. A linear dependency test is applied to each vector to determine if a change has occurred. WCD is mapped into a 12-processing element array with a fixed window value of 3/spl times/3. Design of each processing element is discussed in detail. Based on extensive search, no VLSI implementation of WCD has been reported previously.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579959
Q. Qi, C. Chakrabarti
In ad-hoc networks formed by battery powered nodes, the network lifetime can be significantly enhanced by incorporating the battery properties in the routing protocol. In this paper, we propose such a routing mechanism BCRM, that enhances the network lifetime by letting some of the nodes recover part of their lost charge. This is done by putting the selected set of nodes to sleep. We integrate BCRM into well-known on-demand protocols such as DSR, MBCR and MMBCR, and evaluate their performance. Simulation results show that BCRM based protocols can improve network lifetime significantly with slight degradation in throughput.
{"title":"Improving the battery performance of ad-hoc routing protocols","authors":"Q. Qi, C. Chakrabarti","doi":"10.1109/SIPS.2005.1579959","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579959","url":null,"abstract":"In ad-hoc networks formed by battery powered nodes, the network lifetime can be significantly enhanced by incorporating the battery properties in the routing protocol. In this paper, we propose such a routing mechanism BCRM, that enhances the network lifetime by letting some of the nodes recover part of their lost charge. This is done by putting the selected set of nodes to sleep. We integrate BCRM into well-known on-demand protocols such as DSR, MBCR and MMBCR, and evaluate their performance. Simulation results show that BCRM based protocols can improve network lifetime significantly with slight degradation in throughput.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121327455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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