Pub Date : 2005-11-02DOI: 10.1109/SIPS.2005.1579836
J. Delahaye, J. Palicot, P. Leray
This paper presents a functional model based on a hierarchical architecture template meeting with software defined radio system requirements (SDR Systems). The concepts and mechanisms required to design future reconfigurable system architectures are addressed in the paper. The definition of the new features requested in such architectures is based on a functional analysis of a multi-standards transmitter (i.e. UMTS/FDD uplink, GSM uplink, and 802.11g OFDM mode). Taking into account this application analysis we propose a hierarchical modeling based on a double path. In addition to a classical data path for processing, a configuration management path has been integrated. This model aims at helping the design and management of a heterogeneous dynamically reconfigurable hardware architecture for SDR terminals.
{"title":"A hierarchical modeling approach in software defined radio system design","authors":"J. Delahaye, J. Palicot, P. Leray","doi":"10.1109/SIPS.2005.1579836","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579836","url":null,"abstract":"This paper presents a functional model based on a hierarchical architecture template meeting with software defined radio system requirements (SDR Systems). The concepts and mechanisms required to design future reconfigurable system architectures are addressed in the paper. The definition of the new features requested in such architectures is based on a functional analysis of a multi-standards transmitter (i.e. UMTS/FDD uplink, GSM uplink, and 802.11g OFDM mode). Taking into account this application analysis we propose a hierarchical modeling based on a double path. In addition to a classical data path for processing, a configuration management path has been integrated. This model aims at helping the design and management of a heterogeneous dynamically reconfigurable hardware architecture for SDR terminals.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122885704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-11-02DOI: 10.1109/SIPS.2005.1579849
A. Brokalakis, A. Kakarountas, C. Goutis
Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter cryptographic primitive is proposed. It presents the highest performance (in terms of throughput) among competitive academic and commercial implementations. Using a Virtex-II device, a 1.94 Gbps throughput is achieved, while the memory usage remains low (8 BlockRAMs) and the CLB coverage moderate.
{"title":"A high-throughput area efficient FPGA implementation of AES-128 Encryption","authors":"A. Brokalakis, A. Kakarountas, C. Goutis","doi":"10.1109/SIPS.2005.1579849","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579849","url":null,"abstract":"Advanced Encryption Standard (AES) is used nowadays extensively in many network and multimedia applications to address security issues. In this paper, a high throughput area efficient FPGA implementation of the latter cryptographic primitive is proposed. It presents the highest performance (in terms of throughput) among competitive academic and commercial implementations. Using a Virtex-II device, a 1.94 Gbps throughput is achieved, while the memory usage remains low (8 BlockRAMs) and the CLB coverage moderate.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124209517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-11-01DOI: 10.1109/SIPS.2005.1579874
J. Nsenga, B. Bougard, G. Lenoir, A. Dejonghe, F. Catthoor
The need for higher data rates in wireless system has driven most of the recent wireless research arena. However, the increase of the system transmission rate implies higher system energy consumption. This creates a serious problem in the case of battery-powered devices such as wireless terminals. Therefore, a power management policy is necessary to dynamically trade off the system transmission rate and its energy consumption. In previous work, cross-layer energy-aware radio link control has been applied on OFDM-based WLAN transceivers. Such systems are designed for operating in indoor environment, where they can provide high throughput under low mobility conditions. Thus, the cross-layer energy-aware radio link control relies on a constant average path loss. However, in a wireless indoor environment, the average path loss can encounter significant random changes if, for instance, unpredictable object appears suddenly between the transmitter and the receiver, or simply if one or both terminal moves. The average path loss variation can reach up to 40 dB in some cases. Consequently, the power management stability can be dramatically affected. This paper aims at analyzing the sensitivity of the cross-layer energy radio link control due to such real-time average path loss variation. We also propose a more robust approach to ensure the stability of the considered radio link control strategy against random average path loss changes. From the simulation results, we have proven that the proposed radio link control approach can reduce the relative sub-optimal energy consumption per bit down to 5% compared with perfect calibration, which implies a factor 6 reduction in the sub-optimal energy consumed per bit regarding the existing radio link control.
{"title":"Sensitivity of energy-aware radio link control to imperfect average path loss knowledge","authors":"J. Nsenga, B. Bougard, G. Lenoir, A. Dejonghe, F. Catthoor","doi":"10.1109/SIPS.2005.1579874","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579874","url":null,"abstract":"The need for higher data rates in wireless system has driven most of the recent wireless research arena. However, the increase of the system transmission rate implies higher system energy consumption. This creates a serious problem in the case of battery-powered devices such as wireless terminals. Therefore, a power management policy is necessary to dynamically trade off the system transmission rate and its energy consumption. In previous work, cross-layer energy-aware radio link control has been applied on OFDM-based WLAN transceivers. Such systems are designed for operating in indoor environment, where they can provide high throughput under low mobility conditions. Thus, the cross-layer energy-aware radio link control relies on a constant average path loss. However, in a wireless indoor environment, the average path loss can encounter significant random changes if, for instance, unpredictable object appears suddenly between the transmitter and the receiver, or simply if one or both terminal moves. The average path loss variation can reach up to 40 dB in some cases. Consequently, the power management stability can be dramatically affected. This paper aims at analyzing the sensitivity of the cross-layer energy radio link control due to such real-time average path loss variation. We also propose a more robust approach to ensure the stability of the considered radio link control strategy against random average path loss changes. From the simulation results, we have proven that the proposed radio link control approach can reduce the relative sub-optimal energy consumption per bit down to 5% compared with perfect calibration, which implies a factor 6 reduction in the sub-optimal energy consumed per bit regarding the existing radio link control.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133291422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-11-01DOI: 10.1109/SIPS.2005.1579848
N. Symth, M. McLoone, J. McCanny
This paper proposes a novel processor architecture that provides a reconfigurable computing platform for modular exponentiation used in RSA and Diffle-Hellman public-key cryptography. The processor can operate autonomously to perform all operations required for modular exponentiation. A parallel-processing pipeline offers the versatility to perform any large-integer arithmetic. The processor can perform modular exponentiation using classical exponentiation, Montgomery multiplication and Barrett reduction. Hardware exponent receding is used to improve the efficiency of square-and-multiply algorithms by 15%. The performance of the processor is competitive in comparison to fixed functionality hardware implementations and is significantly faster than general purpose public-key cryptographic processors previously reported in the literature.
{"title":"Reconfigurable processor for public-key cryptography","authors":"N. Symth, M. McLoone, J. McCanny","doi":"10.1109/SIPS.2005.1579848","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579848","url":null,"abstract":"This paper proposes a novel processor architecture that provides a reconfigurable computing platform for modular exponentiation used in RSA and Diffle-Hellman public-key cryptography. The processor can operate autonomously to perform all operations required for modular exponentiation. A parallel-processing pipeline offers the versatility to perform any large-integer arithmetic. The processor can perform modular exponentiation using classical exponentiation, Montgomery multiplication and Barrett reduction. Hardware exponent receding is used to improve the efficiency of square-and-multiply algorithms by 15%. The performance of the processor is competitive in comparison to fixed functionality hardware implementations and is significantly faster than general purpose public-key cryptographic processors previously reported in the literature.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133529768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-11-01DOI: 10.1109/SIPS.2005.1579879
N. Tack, G. Lafruit, F. Catthoor, R. Lauwereins
Today, mobile terminals such as personal digital assistants and mobile phones have reached a sufficiently high level of performance as to support simple 3D graphics applications. The challenge is to generate the best possible images within the performance constraints of the used terminal. The algorithms that solve this optimization problem however ignores the energy consumption, which is a scarce resource on a mobile device. We therefore propose to extend current 3D graphics optimization algorithms which adjust image quality to meet timing constraints, with an energy cost. We propose to let the user choose the desired trade-off between visual quality and energy consumption. The task of the optimization algorithm is then to try to provide the user requested quality and to minimize the energy consumption for a given execution time deadline.
{"title":"A content quality driven energy management system for mobile 3D graphics","authors":"N. Tack, G. Lafruit, F. Catthoor, R. Lauwereins","doi":"10.1109/SIPS.2005.1579879","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579879","url":null,"abstract":"Today, mobile terminals such as personal digital assistants and mobile phones have reached a sufficiently high level of performance as to support simple 3D graphics applications. The challenge is to generate the best possible images within the performance constraints of the used terminal. The algorithms that solve this optimization problem however ignores the energy consumption, which is a scarce resource on a mobile device. We therefore propose to extend current 3D graphics optimization algorithms which adjust image quality to meet timing constraints, with an energy cost. We propose to let the user choose the desired trade-off between visual quality and energy consumption. The task of the optimization algorithm is then to try to provide the user requested quality and to minimize the energy consumption for a given execution time deadline.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127254949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-24DOI: 10.1109/ICASIC.2005.1611290
Leibo Liu, Zhihua Wang, Ning Chen, Li Zhang
This paper proposed a VLSI architecture of embedded block coding with optimized truncation (EBCOT) Tier-2 encoder for JPEG2000. Based on a rate-distortion (RD) slope method, the proposed architecture eliminate the iteration of the RD truncation, reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time, accurately control the compression bit-rate with 95% precision. The proposed Tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18 /spl mu/m 1P6M CMOS technology.
{"title":"VLSI architecture of EBCOT Tier-2 encoder for JPEG2000","authors":"Leibo Liu, Zhihua Wang, Ning Chen, Li Zhang","doi":"10.1109/ICASIC.2005.1611290","DOIUrl":"https://doi.org/10.1109/ICASIC.2005.1611290","url":null,"abstract":"This paper proposed a VLSI architecture of embedded block coding with optimized truncation (EBCOT) Tier-2 encoder for JPEG2000. Based on a rate-distortion (RD) slope method, the proposed architecture eliminate the iteration of the RD truncation, reduces the scale of the on-chip bit-stream buffering from full tile size down to three-code-block size and at the same time, accurately control the compression bit-rate with 95% precision. The proposed Tier-2 encoder has already been integrated into the JPEG2000 codec and fabricated with SMIC 0.18 /spl mu/m 1P6M CMOS technology.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123982798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-08DOI: 10.1109/MAPE.2005.1618130
H. Nguyen, T. Lestable
Link adaptation technology has been introduced in new generation transmission systems such as 3-G or 4-G, optimizing both their throughput and their power consumption. The adaptation of radio configuration requires information about the radio link quality. The information must be exchanged between the access point and the mobile terminal, leading to an associated signaling load, whose amount may decrease the system transmission efficiency. A mechanism for reducing the amount of signaling information has to be designed for increasing the overall system capacity (more users, more available bandwidth). This paper addresses multi-carrier systems whose link adaptation is carried out by means of bit loading algorithms. However, the associated signaling load increases quickly with the number of sub-carriers, modulation schemes and users. These bit loading vectors are considered a-priori known at the receiver, and almost no literature concerning transmission of such information is available. In realistic transmission systems, correlation exists in time due to Doppler effect, and in frequency due to multi-path delay spread. We intend to exploit this two-fold redundancy to decrease the signaling information load related to the power vector data for bit loading. A compression system for both bit allocation and power allocation of the bit loading is proposed. The performance of such compression system is then evaluated.
{"title":"Network signalling compression for bit loading","authors":"H. Nguyen, T. Lestable","doi":"10.1109/MAPE.2005.1618130","DOIUrl":"https://doi.org/10.1109/MAPE.2005.1618130","url":null,"abstract":"Link adaptation technology has been introduced in new generation transmission systems such as 3-G or 4-G, optimizing both their throughput and their power consumption. The adaptation of radio configuration requires information about the radio link quality. The information must be exchanged between the access point and the mobile terminal, leading to an associated signaling load, whose amount may decrease the system transmission efficiency. A mechanism for reducing the amount of signaling information has to be designed for increasing the overall system capacity (more users, more available bandwidth). This paper addresses multi-carrier systems whose link adaptation is carried out by means of bit loading algorithms. However, the associated signaling load increases quickly with the number of sub-carriers, modulation schemes and users. These bit loading vectors are considered a-priori known at the receiver, and almost no literature concerning transmission of such information is available. In realistic transmission systems, correlation exists in time due to Doppler effect, and in frequency due to multi-path delay spread. We intend to exploit this two-fold redundancy to decrease the signaling information load related to the power vector data for bit loading. A compression system for both bit allocation and power allocation of the bit loading is proposed. The performance of such compression system is then evaluated.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123970344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579958
Jung-Ju Kim, Jung-Ho Noh, K. Chang
In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M. 1225, detection probability, false alarm, missing probability, and mean acquisition time of the proposed timing synchronization scheme are compared with the existing method of T.M. Scmidl et al, (1997) to demonstrate the excellence of the proposed scheme. MSE (mean square error) and signal constellation to show the performance of carrier frequency offset estimation is also addressed in this paper.
本文提出了OFDMA (OFDM-FDMA)系统的鲁棒定时和频率同步技术。在ITU-R M. 1225的多径信道环境下，将提出的定时同步方案的检测概率、虚报警、缺失概率和平均采集时间与T.M. Scmidl等(1997)的现有方法进行比较，证明了所提方案的优越性。本文还讨论了用均方误差(MSE)和信号星座来显示载波频偏估计的性能。
{"title":"Robust timing & frequency synchronization techniques for OFDM-FDMA systems","authors":"Jung-Ju Kim, Jung-Ho Noh, K. Chang","doi":"10.1109/SIPS.2005.1579958","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579958","url":null,"abstract":"In this paper, robust timing & frequency synchronization techniques for OFDMA (OFDM-FDMA) systems is presented. Under the multi-path channel environment of ITU-R M. 1225, detection probability, false alarm, missing probability, and mean acquisition time of the proposed timing synchronization scheme are compared with the existing method of T.M. Scmidl et al, (1997) to demonstrate the excellence of the proposed scheme. MSE (mean square error) and signal constellation to show the performance of carrier frequency offset estimation is also addressed in this paper.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114652234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579884
T. Sihvo, J. Niittylahti
This paper discusses the optimization of the H.264/AVC sub-pixel interpolation operation in the context of a software implementation on a subword parallel processor. Several known algorithmic and architectural optimization approaches are combined to achieve a low-cost interpolation implementation. The proposed interpolation scheme, which produces identical results with the reference software, requires no multiplications and 16-bit integer arithmetic is sufficient for the computation. The instruction set extensions result in cycle savings without much increasing the hardware cost. They also enable in-place processing in the half-pixel interpolation. When the optimizations are applied, it is possible to implement the H.264/AVC decoder without a multiplier.
{"title":"H.264/AVC interpolation optimization","authors":"T. Sihvo, J. Niittylahti","doi":"10.1109/SIPS.2005.1579884","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579884","url":null,"abstract":"This paper discusses the optimization of the H.264/AVC sub-pixel interpolation operation in the context of a software implementation on a subword parallel processor. Several known algorithmic and architectural optimization approaches are combined to achieve a low-cost interpolation implementation. The proposed interpolation scheme, which produces identical results with the reference software, requires no multiplications and 16-bit integer arithmetic is sufficient for the computation. The instruction set extensions result in cycle savings without much increasing the hardware cost. They also enable in-place processing in the half-pixel interpolation. When the optimizations are applied, it is possible to implement the H.264/AVC decoder without a multiplier.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121325936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579853
Yi-Ran Sun, S. Signell
Sampling noise folding causes a large SNR degradation at the output of bandpass sampling (BPS) system. A sampling architecture based on generalized quadrature bandpass sampling (GQBPS) was proposed in Y.-R. Sun and S. Signell (2005). Theoretical analysis showed that such architecture is promising to reduce the SNR degradation due to noise aliasing. In this paper, uniform quadrature bandpass sampling (UQBPS) as a special case of GQBPS is analyzed for both ideal sampling and a sample-and-hold. One available implementation method to UQBPS is shown and discussed at the circuit level.
{"title":"Analysis and implementation of uniform quadrature bandpass sampling","authors":"Yi-Ran Sun, S. Signell","doi":"10.1109/SIPS.2005.1579853","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579853","url":null,"abstract":"Sampling noise folding causes a large SNR degradation at the output of bandpass sampling (BPS) system. A sampling architecture based on generalized quadrature bandpass sampling (GQBPS) was proposed in Y.-R. Sun and S. Signell (2005). Theoretical analysis showed that such architecture is promising to reduce the SNR degradation due to noise aliasing. In this paper, uniform quadrature bandpass sampling (UQBPS) as a special case of GQBPS is analyzed for both ideal sampling and a sample-and-hold. One available implementation method to UQBPS is shown and discussed at the circuit level.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"105 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122633806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：