Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579841
C. Brunelli, P. Salmela, J. Takala, J. Nurmi
In the last years multimedia processing applications have gained more and more importance in the field of mobile and hand-held devices, requiring dedicated hardware platforms characterized by high performance computation capabilities with reduced area occupation and low power consumption. 2D graphics and signal processing applications in general benefit from the usage of integer single-instruction-multiple-data (SIMD) functional units, while 3D graphics applications can be significantly accelerated employing single precision floating-point functional units. This paper presents a model and implementation of a versatile multiplier able to perform either double precision, (paired) single precision floating-point multiplications or 16-bit or 8-bit SIMD integer (vector) multiplications; it was implemented on an FPGA device and compared to other floating-point multipliers and similar devices, each capable of performing only a limited subset of the proposed design. The results show that all the functionalities provided by the set of the other considered devices can be performed by the proposed design with a minor area overhead penalty and still competitive performance; thus the proposed multiplier represents in particular a good candidate for usage in area-limited designs.
{"title":"A flexible multiplier for media processing","authors":"C. Brunelli, P. Salmela, J. Takala, J. Nurmi","doi":"10.1109/SIPS.2005.1579841","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579841","url":null,"abstract":"In the last years multimedia processing applications have gained more and more importance in the field of mobile and hand-held devices, requiring dedicated hardware platforms characterized by high performance computation capabilities with reduced area occupation and low power consumption. 2D graphics and signal processing applications in general benefit from the usage of integer single-instruction-multiple-data (SIMD) functional units, while 3D graphics applications can be significantly accelerated employing single precision floating-point functional units. This paper presents a model and implementation of a versatile multiplier able to perform either double precision, (paired) single precision floating-point multiplications or 16-bit or 8-bit SIMD integer (vector) multiplications; it was implemented on an FPGA device and compared to other floating-point multipliers and similar devices, each capable of performing only a limited subset of the proposed design. The results show that all the functionalities provided by the set of the other considered devices can be performed by the proposed design with a minor area overhead penalty and still competitive performance; thus the proposed multiplier represents in particular a good candidate for usage in area-limited designs.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122693765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579898
B. Montrucchio, F. Lamberti, A. Gamba, G. Serini
This paper presents a comprehensive framework for quantitative analysis of vascular processes from in-vitro videomicroscopy data. By following an active contours based approach, we designed a quasi-automatic technique enabling highly interacting motile endothelial cells (ECs) tracking in large field of view phase contrast microscopy video sequences. Our work was motivated by the necessity of validating through statistical analysis an analytical model mimicking ECs behavior. However, the proposed framework could also constitute an invaluable tool supporting general experimental studies on vascularization. Our tracking technique has been extensively validated on realistic data-sets by comparison with a manually defined ground-truth.
{"title":"Tracking endothelial cells during blood vessel networks assembly using active contours","authors":"B. Montrucchio, F. Lamberti, A. Gamba, G. Serini","doi":"10.1109/SIPS.2005.1579898","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579898","url":null,"abstract":"This paper presents a comprehensive framework for quantitative analysis of vascular processes from in-vitro videomicroscopy data. By following an active contours based approach, we designed a quasi-automatic technique enabling highly interacting motile endothelial cells (ECs) tracking in large field of view phase contrast microscopy video sequences. Our work was motivated by the necessity of validating through statistical analysis an analytical model mimicking ECs behavior. However, the proposed framework could also constitute an invaluable tool supporting general experimental studies on vascularization. Our tracking technique has been extensively validated on realistic data-sets by comparison with a manually defined ground-truth.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128268842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579855
Wonjae Lee, Jaeseok Kim
A cost-effective demosaicked image enhancement method for a single chip CMOS (complementary metal oxide semiconductor) image sensor which has on-chip ISP (image signal processor) is introduced. CMOS image sensors are becoming popular, because various circuits can be integrated with it into a single chip. In a single chip CMOS image sensor for handheld devices which requires low power consumption, ISP has to be implemented to small size while maintaining the high performance. Demosaicking and image enhancing are the largest blocks in the ISP, because they need some line memories. In this paper, we propose a new method to minimize the number of line memory. In the proposed method, contrast enhancement is done using the buffered data for demosaicking. The green channel is used instead of luminance. Experimental results indicate that the proposed approach enhances the image quality without additional line memories. The proposed method is implemented on FPGA chip in real time mode, and performed successfully.
{"title":"A cost-effective demosaicked image enhancement for a single chip CMOS image sensor","authors":"Wonjae Lee, Jaeseok Kim","doi":"10.1109/SIPS.2005.1579855","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579855","url":null,"abstract":"A cost-effective demosaicked image enhancement method for a single chip CMOS (complementary metal oxide semiconductor) image sensor which has on-chip ISP (image signal processor) is introduced. CMOS image sensors are becoming popular, because various circuits can be integrated with it into a single chip. In a single chip CMOS image sensor for handheld devices which requires low power consumption, ISP has to be implemented to small size while maintaining the high performance. Demosaicking and image enhancing are the largest blocks in the ISP, because they need some line memories. In this paper, we propose a new method to minimize the number of line memory. In the proposed method, contrast enhancement is done using the buffered data for demosaicking. The green channel is used instead of luminance. Experimental results indicate that the proposed approach enhances the image quality without additional line memories. The proposed method is implemented on FPGA chip in real time mode, and performed successfully.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128730786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In a typical multi-chip handheld system for multi-media applications, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 50%, 61%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With Artisan 0.18 /spl mu/m cell library, the proposed EC codec engine can encode or decode at VGA@30fps with area and power consumption of 293,605 /spl mu/m/sup 2/ and 3.36 mW.
{"title":"Multi-mode embedded compression codec engine for power-aware video coding system","authors":"Chih-Chi Cheng, Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen","doi":"10.1109/SIPS.2005.1579925","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579925","url":null,"abstract":"In a typical multi-chip handheld system for multi-media applications, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 50%, 61%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With Artisan 0.18 /spl mu/m cell library, the proposed EC codec engine can encode or decode at VGA@30fps with area and power consumption of 293,605 /spl mu/m/sup 2/ and 3.36 mW.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127268997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579916
J. Heikkinen, J. Takala, Henk Corporaal
Program code size has become a critical design constraint of embedded systems. Large program codes result in large memories, which increase the size and cost of the chip. Poor code density is a problem especially in VLIW architectures, where a long instruction word is used to control the concurrently operating hardware resources. In addition, wide instructions increase the memory bandwidth, which may result in increased power consumption. Dictionary compression is one of the most often used compression methods to improve the code density due to its simplicity. In this paper, dictionary-based program compression is applied on transport triggered architecture, a customizable processor architecture that is particularly suitable for tailoring the hardware resources according to the requirements of the application. The effects on area and power consumption were measured. We observed that at best, the area of the instruction memory and the fetch and decode logic could be reduced by 87%, and power consumption by 80%, correspondingly.
{"title":"Dictionary-based program compression on TTAs: effects on area and power consumption","authors":"J. Heikkinen, J. Takala, Henk Corporaal","doi":"10.1109/SIPS.2005.1579916","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579916","url":null,"abstract":"Program code size has become a critical design constraint of embedded systems. Large program codes result in large memories, which increase the size and cost of the chip. Poor code density is a problem especially in VLIW architectures, where a long instruction word is used to control the concurrently operating hardware resources. In addition, wide instructions increase the memory bandwidth, which may result in increased power consumption. Dictionary compression is one of the most often used compression methods to improve the code density due to its simplicity. In this paper, dictionary-based program compression is applied on transport triggered architecture, a customizable processor architecture that is particularly suitable for tailoring the hardware resources according to the requirements of the application. The effects on area and power consumption were measured. We observed that at best, the area of the instruction memory and the fetch and decode logic could be reduced by 87%, and power consumption by 80%, correspondingly.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129032605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579892
I. Stathopoulou, G. Tsihrintzis
Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines automatically whether or not there are any faces in given images and, if so, returns the location and extent of each face. Next, FADECS uses neural network-based classifiers which allow the classification of several facial expressions from features that we develop and describe.
{"title":"Detection and expression classification systems for face images (FADECS)","authors":"I. Stathopoulou, G. Tsihrintzis","doi":"10.1109/SIPS.2005.1579892","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579892","url":null,"abstract":"Towards building new, friendlier human-computer interaction systems and multimedia interactive services systems, we developed a neural network-based image processing system (called FADECS), which first determines automatically whether or not there are any faces in given images and, if so, returns the location and extent of each face. Next, FADECS uses neural network-based classifiers which allow the classification of several facial expressions from features that we develop and describe.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129105317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579946
M. Lanuzza, S. Perri, P. Corsonello, G. Cocorullo
This paper presents the design of a new wavelet-based encoder suitable for fast and low-power image and video compression. The proposed circuit is based on a modified version of the No List SPIHT algorithm. When realized using a XILINX Virtex XC2V1000 device, the new encoder requires only 3.4 ms to perform lossless image compression on a 128/spl times/128 16-bit discrete wavelet transformed image. It uses 392 slices, /spl sim/15 KB of RAM memory and dissipates just 8.2 mW/MHz.
{"title":"An efficient wavelet image encoder for FPGA-based designs","authors":"M. Lanuzza, S. Perri, P. Corsonello, G. Cocorullo","doi":"10.1109/SIPS.2005.1579946","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579946","url":null,"abstract":"This paper presents the design of a new wavelet-based encoder suitable for fast and low-power image and video compression. The proposed circuit is based on a modified version of the No List SPIHT algorithm. When realized using a XILINX Virtex XC2V1000 device, the new encoder requires only 3.4 ms to perform lossless image compression on a 128/spl times/128 16-bit discrete wavelet transformed image. It uses 392 slices, /spl sim/15 KB of RAM memory and dissipates just 8.2 mW/MHz.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129736395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579886
N. Doulamis, A. Doulamis, D. Kosmopoulos
In this paper we present a novel method for gesture video decomposition based on the depicted content. From the initial content the key-frames are extracted and the neighboring frames are assigned to key-frames of similar content. The resulting frame groups are decomposed to binary trees, based on the energy of the depicted gestures. In case of reduced bandwidth we keep the original timeline but we send only a dynamically adapted video summary. The respective frames are obtained by moving appropriately across the hierarchy layers of the constructed tree. The hierarchically structured video can be used for purposes such as efficient video browsing and transmission of dynamically generated summaries over low bandwidth networks, for communication or human-computer interface applications.
{"title":"Content-based decomposition of gesture videos","authors":"N. Doulamis, A. Doulamis, D. Kosmopoulos","doi":"10.1109/SIPS.2005.1579886","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579886","url":null,"abstract":"In this paper we present a novel method for gesture video decomposition based on the depicted content. From the initial content the key-frames are extracted and the neighboring frames are assigned to key-frames of similar content. The resulting frame groups are decomposed to binary trees, based on the energy of the depicted gestures. In case of reduced bandwidth we keep the original timeline but we send only a dynamically adapted video summary. The respective frames are obtained by moving appropriately across the hierarchy layers of the constructed tree. The hierarchically structured video can be used for purposes such as efficient video browsing and transmission of dynamically generated summaries over low bandwidth networks, for communication or human-computer interface applications.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"67 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132372575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579834
R. Matei, F. Lelia, H. Sorin
A new approach in designing the filtering stage in a digital IF-sampling software defined radio (SDR) receiver is presented. The proposed technique provides a practical solution towards the implementation of a programmable wireless transceiver compatible with the requirements of various voice and data wireless standards: TETRA, PDC, IS-95, GSM, IS-54, TACS and Extended GSM. A sixth-order 1 dB ripple Chebyshev band-pass filter is designed on standard 0.25 /spl mu/ CMOS processes to implement the IF filter. It is based on an operational transconductance amplifier (OTA) with large dc gain and wide bandwidth. The filter features high linearity and bandwidth programmability between 10 MHz and 35 MHz, at a center frequency of 100 MHz.
提出了一种设计数字中频采样软件无线电接收机滤波级的新方法。提出的技术为实现可编程无线收发器提供了一种实用的解决方案，该无线收发器兼容各种语音和数据无线标准:TETRA、PDC、IS-95、GSM、IS-54、TACS和扩展GSM。在标准的0.25 /spl μ m / CMOS工艺上设计了一个6阶1db纹波切比雪夫带通滤波器来实现中频滤波器。它是基于一个操作跨导放大器(OTA)，具有大直流增益和宽带宽。该滤波器具有高线性度和带宽可编程性，在10 MHz和35 MHz之间，中心频率为100 MHz。
{"title":"A programmable band-select filter for digital IF software defined radio receivers","authors":"R. Matei, F. Lelia, H. Sorin","doi":"10.1109/SIPS.2005.1579834","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579834","url":null,"abstract":"A new approach in designing the filtering stage in a digital IF-sampling software defined radio (SDR) receiver is presented. The proposed technique provides a practical solution towards the implementation of a programmable wireless transceiver compatible with the requirements of various voice and data wireless standards: TETRA, PDC, IS-95, GSM, IS-54, TACS and Extended GSM. A sixth-order 1 dB ripple Chebyshev band-pass filter is designed on standard 0.25 /spl mu/ CMOS processes to implement the IF filter. It is based on an operational transconductance amplifier (OTA) with large dc gain and wide bandwidth. The filter features high linearity and bandwidth programmability between 10 MHz and 35 MHz, at a center frequency of 100 MHz.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122235458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579847
P. Tzouveli, K. Ntalianis, S. Kollias
A novel video object based watermarking scheme is proposed in this paper, providing copyright protection of the semantic content. To achieve this goal, an adaptive two-dimensional Gaussian model of skin color distribution is initially used in order to detect face and body regions within the initial image. An invariant watermark is then designed and tested against attacks using invariant Hu moments. The proposed algorithms have the advantages of being robust, computationally efficient, and overheads transmitted to the decoder side are very low. Performance of the proposed object based watermarking system is tested under various signal distortions such as JPEG lossy compression, blurring, filtering and cropping, Experimental results on real life images indicate the efficiency and robustness of the proposed scheme.
{"title":"Human video object watermarking based on Hu moments","authors":"P. Tzouveli, K. Ntalianis, S. Kollias","doi":"10.1109/SIPS.2005.1579847","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579847","url":null,"abstract":"A novel video object based watermarking scheme is proposed in this paper, providing copyright protection of the semantic content. To achieve this goal, an adaptive two-dimensional Gaussian model of skin color distribution is initially used in order to detect face and body regions within the initial image. An invariant watermark is then designed and tested against attacks using invariant Hu moments. The proposed algorithms have the advantages of being robust, computationally efficient, and overheads transmitted to the decoder side are very low. Performance of the proposed object based watermarking system is tested under various signal distortions such as JPEG lossy compression, blurring, filtering and cropping, Experimental results on real life images indicate the efficiency and robustness of the proposed scheme.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125096713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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