Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579954
G. Pastuszak
The architecture for EBCOT in JPEG 2000 is presented. The architecture embeds all functions necessary to produce the final codestream consistent with the JPEG 2000 specification. A number of hardware optimisation methods are used to achieve the high throughput at relatively low cost of hardware resources. The architecture is verified in simulations and synthesized for ASIC and FPGA technologies. Implementation results for FPGA Stratix II devices show that it can work at 120 MHz and process about 40 million samples per second in the regular lossless mode.
{"title":"A high-performance architecture for EBCOT in the JPEG 2000 encoder","authors":"G. Pastuszak","doi":"10.1109/SIPS.2005.1579954","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579954","url":null,"abstract":"The architecture for EBCOT in JPEG 2000 is presented. The architecture embeds all functions necessary to produce the final codestream consistent with the JPEG 2000 specification. A number of hardware optimisation methods are used to achieve the high throughput at relatively low cost of hardware resources. The architecture is verified in simulations and synthesized for ASIC and FPGA technologies. Implementation results for FPGA Stratix II devices show that it can work at 120 MHz and process about 40 million samples per second in the regular lossless mode.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127992861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579868
P. Bougas, A. Tsirikos, P. Kalivas, K. Pekmestzi
In this paper, a novel architecture for the implementation of serial parallel multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. This multiplier achieves higher throughput because it requires small number of zeros to start a new multiplication cycle at a moderate hardware expense and achieves significant hardware reduction compared to the double precision SPM. The proposed technique permits the optimization of the area time product.
{"title":"Segmenetation based design of serial parallel multipliers","authors":"P. Bougas, A. Tsirikos, P. Kalivas, K. Pekmestzi","doi":"10.1109/SIPS.2005.1579868","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579868","url":null,"abstract":"In this paper, a novel architecture for the implementation of serial parallel multipliers (SPM) is proposed. The proposed multiplier is based on a segmentation technique of a simple SPM to blocks of equal bit length. This multiplier achieves higher throughput because it requires small number of zeros to start a new multiplication cycle at a moderate hardware expense and achieves significant hardware reduction compared to the double precision SPM. The proposed technique permits the optimization of the area time product.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579912
Mahmoud Saeidi, S. Motamedi, A. Behrad, B. Saeidi, R. Saeidi, Reza Saeidi
In this paper, we will propose a novel spatiotemporal filter that utilizes consecutive frames in order to remove noise. The consecutive frames include: current, previous and next noisy frames. The filter proposed in this paper is based upon the weighted averaging pixels intensity in image sequences. The weights are determined by a well-defined mathematical criterion, which is adaptive to the feature of spatiotemporal pixels of the consecutive frames. It is experimentally shown that the proposed filter can preserve image structures and edges under motion while suppressing noise, and thus can be effectively used in image sequences filtering. Most importantly, our proposed filter is independent of noise variance and only utilizes the intensity of pixels to suppress noise.
{"title":"Noise reduction of consecutive images using a new adaptive weighted averaging filter","authors":"Mahmoud Saeidi, S. Motamedi, A. Behrad, B. Saeidi, R. Saeidi, Reza Saeidi","doi":"10.1109/SIPS.2005.1579912","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579912","url":null,"abstract":"In this paper, we will propose a novel spatiotemporal filter that utilizes consecutive frames in order to remove noise. The consecutive frames include: current, previous and next noisy frames. The filter proposed in this paper is based upon the weighted averaging pixels intensity in image sequences. The weights are determined by a well-defined mathematical criterion, which is adaptive to the feature of spatiotemporal pixels of the consecutive frames. It is experimentally shown that the proposed filter can preserve image structures and edges under motion while suppressing noise, and thus can be effectively used in image sequences filtering. Most importantly, our proposed filter is independent of noise variance and only utilizes the intensity of pixels to suppress noise.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133061456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579870
Junqing Liu, Jun Sun, Tianhao Li
Based on one-way hash function, Sun proposed an efficient remote login authentication protocol with smart card in 2000. However, in 2002, Chien at al. pointed out a deficiency of Sun's scheme which only realized unilateral authentication and put forward an efficient and practical solution for remote mutual authentication scheme. But recently, Hsu discussed that this scheme was not secure enough since it was vulnerable to the parallel session attack again. In this paper, we give an enhanced remote login authentication with smart card, which inherits all the merits of the previous schemes as well as realizes secure mutual authentication without significantly increasing the computational cost.
{"title":"An enhanced remote login authentication with smart card","authors":"Junqing Liu, Jun Sun, Tianhao Li","doi":"10.1109/SIPS.2005.1579870","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579870","url":null,"abstract":"Based on one-way hash function, Sun proposed an efficient remote login authentication protocol with smart card in 2000. However, in 2002, Chien at al. pointed out a deficiency of Sun's scheme which only realized unilateral authentication and put forward an efficient and practical solution for remote mutual authentication scheme. But recently, Hsu discussed that this scheme was not secure enough since it was vulnerable to the parallel session attack again. In this paper, we give an enhanced remote login authentication with smart card, which inherits all the merits of the previous schemes as well as realizes secure mutual authentication without significantly increasing the computational cost.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128657340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579924
Y. Hwang, Shin-Chi Lai
This paper presents a novel MDCT/IMDCT algorithm and its hardware design. In algorithm derivation, the MDCT/IMDCT computation is first converted into a form of matrix multiplication consisting of a half size DCT-IV kernel and a projection matrix. The DCT-IV kernel is then realized by a fast DCT-II computing scheme. Since MDCT and IMDCT algorithms use the same DCT kernel, a unified architecture using the same set of twiddle factors can be employed for both computations. Based on the proposed algorithm, a novel design mapping is developed with emphasis on the reduction of hardware and memory access complexities. By careful scheduling in computation and memory access schemes, only single port memory modules are needed in lieu of expensive dual port memories. Performance analyses reveal that, given the comparable hardware resource allocation, the proposed design can outperform other MDCT/IMDCT designs in terms of memory storage size, computing latency and fixed point implementation error.
{"title":"A novel MDCT/IMDCT computing kernel design","authors":"Y. Hwang, Shin-Chi Lai","doi":"10.1109/SIPS.2005.1579924","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579924","url":null,"abstract":"This paper presents a novel MDCT/IMDCT algorithm and its hardware design. In algorithm derivation, the MDCT/IMDCT computation is first converted into a form of matrix multiplication consisting of a half size DCT-IV kernel and a projection matrix. The DCT-IV kernel is then realized by a fast DCT-II computing scheme. Since MDCT and IMDCT algorithms use the same DCT kernel, a unified architecture using the same set of twiddle factors can be employed for both computations. Based on the proposed algorithm, a novel design mapping is developed with emphasis on the reduction of hardware and memory access complexities. By careful scheduling in computation and memory access schemes, only single port memory modules are needed in lieu of expensive dual port memories. Performance analyses reveal that, given the comparable hardware resource allocation, the proposed design can outperform other MDCT/IMDCT designs in terms of memory storage size, computing latency and fixed point implementation error.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115497989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579950
G. Motta, J. Storer, B. Carpentieri
When encoding low bit-rate video at constant bit-rate, state of the art video encoders may be forced to skip frames. Frames are mostly skipped after "scene changes", i.e. immediately after the beginning of a new scene. We address the problem of determining the minimal number and the exact positions of the frames that must be skipped in a video sequence in order to match closely a prefixed rate and distortion. The reduction of the number of skipped frames decreases the jerkiness associated to the skips and improves the overall quality of the encoded video. The off-line frame-layer rate control method we propose can be used in several existing video coders and it is fully compatible with rate-distortion optimized macroblock-layer rate controls. We also present a simplified heuristic that performs almost optimally while requiring only minimal encoding complexity with respect to the standard encoders.
{"title":"Frame skipping minimization in low bit-rate video coding","authors":"G. Motta, J. Storer, B. Carpentieri","doi":"10.1109/SIPS.2005.1579950","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579950","url":null,"abstract":"When encoding low bit-rate video at constant bit-rate, state of the art video encoders may be forced to skip frames. Frames are mostly skipped after \"scene changes\", i.e. immediately after the beginning of a new scene. We address the problem of determining the minimal number and the exact positions of the frames that must be skipped in a video sequence in order to match closely a prefixed rate and distortion. The reduction of the number of skipped frames decreases the jerkiness associated to the skips and improves the overall quality of the encoded video. The off-line frame-layer rate control method we propose can be used in several existing video coders and it is fully compatible with rate-distortion optimized macroblock-layer rate controls. We also present a simplified heuristic that performs almost optimally while requiring only minimal encoding complexity with respect to the standard encoders.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115525890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579957
F. Angarita, A. Pérez-Pascual, T. Sansaloni, Javier Valls
In this paper an optimized hardware implementation on FPGA of a Viterbi decoder is presented for WLAN. A fixed-point analysis is made and its performance is compared with a soft decision decoding floating point model with CSI weight. Only 6 bits are needed to perform the soft quantification and 7 bits to the CSI, in order to maintain the performance of the floating point model. A normalization method is proposed to increase the throughput of the decoder, being possible to decode 172 Mbps when it is implemented in a Virtex 2 device. Power consumption results of the decoder implementation are presented for Hiperlan/2 maximum rate. Moreover, it has been shown that it is possible to reduce the power consumption disabling the unnecessary hardware depending on the WLAN modes.
{"title":"Efficient mapping on FPGA of a Viterbi decoder for wireless LANs","authors":"F. Angarita, A. Pérez-Pascual, T. Sansaloni, Javier Valls","doi":"10.1109/SIPS.2005.1579957","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579957","url":null,"abstract":"In this paper an optimized hardware implementation on FPGA of a Viterbi decoder is presented for WLAN. A fixed-point analysis is made and its performance is compared with a soft decision decoding floating point model with CSI weight. Only 6 bits are needed to perform the soft quantification and 7 bits to the CSI, in order to maintain the performance of the floating point model. A normalization method is proposed to increase the throughput of the decoder, being possible to decode 172 Mbps when it is implemented in a Virtex 2 device. Power consumption results of the decoder implementation are presented for Hiperlan/2 maximum rate. Moreover, it has been shown that it is possible to reduce the power consumption disabling the unnecessary hardware depending on the WLAN modes.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"456 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125799709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579896
S. Junnila, A. Akhbardeh, A. Varri, T. Koivistoinen
New sensor technologies open possibilities for measuring traditional biosignals in new innovative ways. This, together with the development of signal processing systems and their computing power, can sometimes give new life to old measurement techniques. Ballistocardiogram is one such technique, originally promising but quickly replaced by the now very popular electrocardiogram. A ballistocardiograph chair, designed to look like a normal office chair, was built and fitted with pressure sensitive EMFi-films. The films are connected via a charge amplifier to a medical bioamplifier. The system was accepted for medical use in Tampere University Hospital and patient measurements have been performed. The system is presented and it's performance evaluated. A wireless version of the system is needed to hide the cabling from the user. This makes the chair indistinguishable from a normal office chair. Overview of first wireless prototype is given. To analyze recorded BCG, individual BCG cycles must be extracted from the signal containing respiration and movement artifacts. A method for this and results of it's application are presented. The developed system can be used for BCG measurements and it is able to automatically extract individual BCG cycles, but it has some limitations which are presented in the paper.
{"title":"An EMFi-film sensor based ballistocardiographic chair: performance and cycle extraction method","authors":"S. Junnila, A. Akhbardeh, A. Varri, T. Koivistoinen","doi":"10.1109/SIPS.2005.1579896","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579896","url":null,"abstract":"New sensor technologies open possibilities for measuring traditional biosignals in new innovative ways. This, together with the development of signal processing systems and their computing power, can sometimes give new life to old measurement techniques. Ballistocardiogram is one such technique, originally promising but quickly replaced by the now very popular electrocardiogram. A ballistocardiograph chair, designed to look like a normal office chair, was built and fitted with pressure sensitive EMFi-films. The films are connected via a charge amplifier to a medical bioamplifier. The system was accepted for medical use in Tampere University Hospital and patient measurements have been performed. The system is presented and it's performance evaluated. A wireless version of the system is needed to hide the cabling from the user. This makes the chair indistinguishable from a normal office chair. Overview of first wireless prototype is given. To analyze recorded BCG, individual BCG cycles must be extracted from the signal containing respiration and movement artifacts. A method for this and results of it's application are presented. The developed system can be used for BCG measurements and it is able to automatically extract individual BCG cycles, but it has some limitations which are presented in the paper.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125959043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579846
Konstantinos Aisopos, A. Kakarountas, H. Michail, C. Goutis
A design approach to create small-sized high-speed implementation of the new version of secure hash algorithm is proposed. The resulted design can be easily embedded to operate in HMAC IP cores, providing a high degree of security. The proposed implementation does not introduce significant area penalty, compared to other competitive designs. However the achieved throughput presents an increase compared to commercially available IP cores that range from 43%-1830%.
{"title":"High throughput implementation of the new secure hash algorithm through partial unrolling","authors":"Konstantinos Aisopos, A. Kakarountas, H. Michail, C. Goutis","doi":"10.1109/SIPS.2005.1579846","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579846","url":null,"abstract":"A design approach to create small-sized high-speed implementation of the new version of secure hash algorithm is proposed. The resulted design can be easily embedded to operate in HMAC IP cores, providing a high degree of security. The proposed implementation does not introduce significant area penalty, compared to other competitive designs. However the achieved throughput presents an increase compared to commercially available IP cores that range from 43%-1830%.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126582753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIPS.2005.1579921
S. H. Yoon, M. Sunwoo, J. Moon
This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 /spl mu/m standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz.
{"title":"Design of a high-quality audio-specific DSP core","authors":"S. H. Yoon, M. Sunwoo, J. Moon","doi":"10.1109/SIPS.2005.1579921","DOIUrl":"https://doi.org/10.1109/SIPS.2005.1579921","url":null,"abstract":"This paper proposes a specialized DSP architecture and their instructions, which efficiently support MPEG-2/4 AAC high-quality audio algorithms. The proposed architecture is specially designed and optimized for the IMDCT (inverse modified discrete cosine transform), Huffman decoding, etc. Performance comparisons show significant improvement compared with TMS320C62x and ASDSP21060 for the IMDCT computation. Furthermore, the dedicated Huffman accelerator performs the decoding process in only 2 cycles. The proposed DSP has been synthesized using the Samsung SEC 0.18 /spl mu/m standard cell library. The proposed DSP core consists of 120,283 gates and runs at 200 MHz.","PeriodicalId":436123,"journal":{"name":"IEEE Workshop on Signal Processing Systems Design and Implementation, 2005.","volume":"388 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124810611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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