Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904894
C. Ndiaye, V. Huard, R. Bertholon, M. Rafik, X. Federspiel, A. Bravaix
In this paper, we analyze the impact of Layout Dependent Effect (LDE) observed on MOSFETs. It is shown that changing the Layout have an impact on MOSFET device parameters and reliability. Here, we studied the Well Proximity Effect (WPE), Length of diffusion (LOD) and Oxide Spacing Effect (OSE) impacts on device MOSFET parameters and reliability. We also analyzed SiGe impacts on LDE, since it is commonly used to boost device performance.
{"title":"Layout Dependent Effect: Impact on device performance and reliability in recent CMOS nodes","authors":"C. Ndiaye, V. Huard, R. Bertholon, M. Rafik, X. Federspiel, A. Bravaix","doi":"10.1109/IIRW.2016.7904894","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904894","url":null,"abstract":"In this paper, we analyze the impact of Layout Dependent Effect (LDE) observed on MOSFETs. It is shown that changing the Layout have an impact on MOSFET device parameters and reliability. Here, we studied the Well Proximity Effect (WPE), Length of diffusion (LOD) and Oxide Spacing Effect (OSE) impacts on device MOSFET parameters and reliability. We also analyzed SiGe impacts on LDE, since it is commonly used to boost device performance.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129962325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904893
T. Ho, K. Joshi, K. Lee, P. Liao, J. Shih, Y. Lee
A systematic study of time dependent source/drain junction degradation (TDJD) for extremely scaled FinFETs is conducted. It is verified that junction degradation can be attributed to the increase in band to band tunneling due to generation of new traps upon application of stress. Impact of varying stress conditions, drain engineering and junction area on TDJD is also studied. It is shown for the first time that TDJD follows 1/E model based on the long-term stress data.
{"title":"Time dependent junction degradation in FinFET","authors":"T. Ho, K. Joshi, K. Lee, P. Liao, J. Shih, Y. Lee","doi":"10.1109/IIRW.2016.7904893","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904893","url":null,"abstract":"A systematic study of time dependent source/drain junction degradation (TDJD) for extremely scaled FinFETs is conducted. It is verified that junction degradation can be attributed to the increase in band to band tunneling due to generation of new traps upon application of stress. Impact of varying stress conditions, drain engineering and junction area on TDJD is also studied. It is shown for the first time that TDJD follows 1/E model based on the long-term stress data.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904909
B. Bittel, S. Vadlamani, S. Ramey, S. Padiyar
Tremendous amounts of wafer level reliability testing is required to support transistor technology development efforts. Conventional testing takes considerable time which severely limits reliability organizations. We present two approaches that help increase data velocity for wafer level reliability measurements and discuss their current limitations.
{"title":"Increasing velocity of wafer level reliability characterization: Novel approaches and limitations","authors":"B. Bittel, S. Vadlamani, S. Ramey, S. Padiyar","doi":"10.1109/IIRW.2016.7904909","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904909","url":null,"abstract":"Tremendous amounts of wafer level reliability testing is required to support transistor technology development efforts. Conventional testing takes considerable time which severely limits reliability organizations. We present two approaches that help increase data velocity for wafer level reliability measurements and discuss their current limitations.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126902374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904910
Kangil Kim, I. Chung, Duan Sun, Sangjae Rhe, Ilgweon Kim, Hongsun Hwang, Kangyong Cho, Gyoyoung Jin
We investigated threshold voltage degradation and recovery of short channel NMOS transistors in the sub wordline driver (SWD), where the source of NMOS transistors was biased with negative voltage during off-state. We found that the threshold voltage degradation occurred by the off-state hot carrier stress. The gate of NMOS transistor in sub wordline driver (SWD) in the off-state is under the subthreshold region (0
{"title":"Study on off-state hot carrier degradation and recovery of NMOSFET in SWD circuits of DRAM","authors":"Kangil Kim, I. Chung, Duan Sun, Sangjae Rhe, Ilgweon Kim, Hongsun Hwang, Kangyong Cho, Gyoyoung Jin","doi":"10.1109/IIRW.2016.7904910","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904910","url":null,"abstract":"We investigated threshold voltage degradation and recovery of short channel NMOS transistors in the sub wordline driver (SWD), where the source of NMOS transistors was biased with negative voltage during off-state. We found that the threshold voltage degradation occurred by the off-state hot carrier stress. The gate of NMOS transistor in sub wordline driver (SWD) in the off-state is under the subthreshold region (0<VGS<VT) due to the negative bias voltage applied to the source terminal. At this situation if a high voltage is applied to the drain, the subthreshold drain current increases due to the DIBL effect. Furthermore, hot carriers with higher energies generate interface traps near the dielectric/Si interface of the MOSFET. These hot carrier degradation caused the positive shift in the threshold voltage. Aforementioned degradation could be recovered by baking with bias. Furthermore, the time of such a recovery was shortened when the gate terminal was floating.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121048630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904902
Theodor Hillebrand, Maike Taddiken, Konstantin Tscherkaschin, S. Paul, D. Peters-Drolshagen
In this paper a comprehensive analysis of 12 different extraction methods for the threshold voltage Vth is presented. Accounting for the emerging needs of advanced technology nodes the methods are evaluated with TCAD simulations of FDSOI, Bulk and Fin MOSFET devices. The presented analysis provides Figures of Merit in order to choose the most suited extraction method for modeling purposes or determining the impact of degradation. Additionally, a maximum measurement noise can be ascertained ensuring reliable extracted values of Vth for any measurement setup. The recognition capability is analyzed for each method, leading to a measurable minimal ΔVth of a single transistor.
{"title":"Vth is dead - long live the threshold voltage","authors":"Theodor Hillebrand, Maike Taddiken, Konstantin Tscherkaschin, S. Paul, D. Peters-Drolshagen","doi":"10.1109/IIRW.2016.7904902","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904902","url":null,"abstract":"In this paper a comprehensive analysis of 12 different extraction methods for the threshold voltage Vth is presented. Accounting for the emerging needs of advanced technology nodes the methods are evaluated with TCAD simulations of FDSOI, Bulk and Fin MOSFET devices. The presented analysis provides Figures of Merit in order to choose the most suited extraction method for modeling purposes or determining the impact of degradation. Additionally, a maximum measurement noise can be ascertained ensuring reliable extracted values of Vth for any measurement setup. The recognition capability is analyzed for each method, leading to a measurable minimal ΔVth of a single transistor.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122390472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904905
Thomas E. Kopley, K. O'Brien, W.C. Chang
We present a framework for circuit-level and application-level gate oxide wearout analysis using a quasi-static AC Time-Dependent Dielectric Breakdown (TDDB) model. The method can assess the gate oxide wearout rate for analog circuit blocks operating in normal or extreme conditions in the field. It can also be used to assess gate-oxide wearout rates for discrete MOSFETs, IGBTs, or any other device with a gate oxide, operated in specific applications. The model has been implemented in Matlab and R as well as Cadence design tools, the latter to allow circuit designers to do quick reliability assessments on their designs. As part of this framework, we introduce gate oxide failure rate versus operating time plots, which offer a concise picture of the amount of failures expected in the field due to gate oxide wearout. This allows designers and product engineers to assess the reliability of a product in terms of ppm failure rates with time in operation.
{"title":"AC TDDB analysis for circuit-level gate oxide wearout reliability assessment","authors":"Thomas E. Kopley, K. O'Brien, W.C. Chang","doi":"10.1109/IIRW.2016.7904905","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904905","url":null,"abstract":"We present a framework for circuit-level and application-level gate oxide wearout analysis using a quasi-static AC Time-Dependent Dielectric Breakdown (TDDB) model. The method can assess the gate oxide wearout rate for analog circuit blocks operating in normal or extreme conditions in the field. It can also be used to assess gate-oxide wearout rates for discrete MOSFETs, IGBTs, or any other device with a gate oxide, operated in specific applications. The model has been implemented in Matlab and R as well as Cadence design tools, the latter to allow circuit designers to do quick reliability assessments on their designs. As part of this framework, we introduce gate oxide failure rate versus operating time plots, which offer a concise picture of the amount of failures expected in the field due to gate oxide wearout. This allows designers and product engineers to assess the reliability of a product in terms of ppm failure rates with time in operation.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116251876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904900
C. LaRow, Y. Liu, Z. Chbili, A. Gondal
This work presents a new experimental setup to perform highly accelerated Time Dependent Dielectric Breakdown (TDDB) in constant voltage stress (CVS) mode with capability of collecting failure distributions in sub millisecond regime. The new apparatus is capable of collecting failure times down to tens of microseconds and we demonstrate that power law dependence with respect to gate voltage down to hundreds of microseconds is valid irrespective of technology. We argue that the implementation of fast TDDB setup for early reliability evaluation would complement the use of voltage ramped stress (VRS), shorten the time for learning cycles, and provide early guidance for reliability assessments.
{"title":"Fast TDDB for early reliability monitoring","authors":"C. LaRow, Y. Liu, Z. Chbili, A. Gondal","doi":"10.1109/IIRW.2016.7904900","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904900","url":null,"abstract":"This work presents a new experimental setup to perform highly accelerated Time Dependent Dielectric Breakdown (TDDB) in constant voltage stress (CVS) mode with capability of collecting failure distributions in sub millisecond regime. The new apparatus is capable of collecting failure times down to tens of microseconds and we demonstrate that power law dependence with respect to gate voltage down to hundreds of microseconds is valid irrespective of technology. We argue that the implementation of fast TDDB setup for early reliability evaluation would complement the use of voltage ramped stress (VRS), shorten the time for learning cycles, and provide early guidance for reliability assessments.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116692907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904888
K. Giering, André Lange, B. Kaczer, R. Jancke
We present a BTI compact model that is able to account for the complex BTI stress patterns encountered in complex electronic circuits. Such stress patterns are composed of various blocks corresponding to different circuit operation states, protocol modes or input conditions, and the blocks repeat within a composite, hierarchical structure. The present work extends a previously introduced physics-based accurate NBTI modeling while preserving its numerical efficiency. We provide insight into some principal characteristics of BTI degradation under hierarchical stress patterns, such as a non-trivial dependence on multiple duty cycles. In particular, the NBTI degradation can sensitively depend on the temporal sequence of NBTI stress blocks, and building a model on just the average stress or on stress histograms can be misleading. An SRAM cell example demonstrates this method and compares the cell's BTI failure statistics for two different hierarchic-periods stress patterns.
{"title":"BTI variability of SRAM cells under periodically changing stress profiles","authors":"K. Giering, André Lange, B. Kaczer, R. Jancke","doi":"10.1109/IIRW.2016.7904888","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904888","url":null,"abstract":"We present a BTI compact model that is able to account for the complex BTI stress patterns encountered in complex electronic circuits. Such stress patterns are composed of various blocks corresponding to different circuit operation states, protocol modes or input conditions, and the blocks repeat within a composite, hierarchical structure. The present work extends a previously introduced physics-based accurate NBTI modeling while preserving its numerical efficiency. We provide insight into some principal characteristics of BTI degradation under hierarchical stress patterns, such as a non-trivial dependence on multiple duty cycles. In particular, the NBTI degradation can sensitively depend on the temporal sequence of NBTI stress blocks, and building a model on just the average stress or on stress histograms can be misleading. An SRAM cell example demonstrates this method and compares the cell's BTI failure statistics for two different hierarchic-periods stress patterns.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114362265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904907
E. Ceccarelli, C. Heffernan, J. Browne, P. Fitzgerald
This work presents a device level reliability (DLR) characterization for the Analog Devices proprietary metal contact microelectromechanical systems (MEMS) switch technology. Stand-alone device characterizations in both hold-down and toggle operation modes are described. An alternative operation mode to analyze is the so called “hot switching”. The switch pull-in voltage and the contact resistance are the main physical parameters that have been analyzed. This DLR characterization methodology can be considered a first step towards a standard that will be performed in parallel to typical product qualifications in order to assess the device long term reliability.
{"title":"Intrinsic reliability characterization for stand-alone MEMS switch technology","authors":"E. Ceccarelli, C. Heffernan, J. Browne, P. Fitzgerald","doi":"10.1109/IIRW.2016.7904907","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904907","url":null,"abstract":"This work presents a device level reliability (DLR) characterization for the Analog Devices proprietary metal contact microelectromechanical systems (MEMS) switch technology. Stand-alone device characterizations in both hold-down and toggle operation modes are described. An alternative operation mode to analyze is the so called “hot switching”. The switch pull-in voltage and the contact resistance are the main physical parameters that have been analyzed. This DLR characterization methodology can be considered a first step towards a standard that will be performed in parallel to typical product qualifications in order to assess the device long term reliability.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128199633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IIRW.2016.7904904
S. Jose, J. Bisschop, V. Girault, L. V. Marwijk, J. Zhang, S. Nath
This paper presents the long-term stability of integrated CMOS resistors in a 40nm technology node. Unsilicided polysilicon and diffusion resistors with two different geometries were investigated. The thermal stability of the resistors was studied at different stress temperatures. Some resistors were subjected to the critical bake temperature in the WLCSP (Wafer Level Chip Scale Packaging) assembly process. The resistance shifts were measured at different stress temperatures after the bake. It was found that WLCSP thermal budget has a significant influence on the resistor shift characteristics in the case of p-poly resistors.
{"title":"Reliability of integrated resistors and the influence of WLCSP bake","authors":"S. Jose, J. Bisschop, V. Girault, L. V. Marwijk, J. Zhang, S. Nath","doi":"10.1109/IIRW.2016.7904904","DOIUrl":"https://doi.org/10.1109/IIRW.2016.7904904","url":null,"abstract":"This paper presents the long-term stability of integrated CMOS resistors in a 40nm technology node. Unsilicided polysilicon and diffusion resistors with two different geometries were investigated. The thermal stability of the resistors was studied at different stress temperatures. Some resistors were subjected to the critical bake temperature in the WLCSP (Wafer Level Chip Scale Packaging) assembly process. The resistance shifts were measured at different stress temperatures after the bake. It was found that WLCSP thermal budget has a significant influence on the resistor shift characteristics in the case of p-poly resistors.","PeriodicalId":436183,"journal":{"name":"2016 IEEE International Integrated Reliability Workshop (IIRW)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131821088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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