Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792516
Feyzan Durn, Martina Weingärtner, M. Khosrawi, Renate Brielmann, M. Gulcur
Elastomers are used in many key applications in semiconductor manufacturing. They have the critical task to maintain vacuum integrity as seals, while elastomer end-effector pads, suction caps and other damping elements made of elastomers play important roles to maintain high efficiency of the semiconductor manufacturing tools. Stiction is a common problem in elastomer parts particularly in sealing applications. We developed Seal-Glide®, a plasma-based surface treatment method that has been successfully employed to overcome the stiction of the seal on the mating surface. Test methods for measuring static and dynamic stiction forces were developed in-house. Three types of test jigs were manufactured to demonstrate the stiction effect on stainless steel, aluminum, and quartz surfaces. To mimic the operating conditions, a single O-Ring was compressed between two plates to a pre-determined deflection using spacers, and the jig was conditioned in an oven at the target temperature. The jig was later uniaxially loaded in tension by a tensile machine at room temperature and the maximum force to separate the two plates was recorded as the stiction force. Cyclic compression tests were also performed on stainless steel and aluminum surfaces to demonstrate the seals’ performance in dynamic applications. Comparison of the tests performed with various sealing materials under the same testing conditions with and without plasma treatment demonstrated that plasma treatment could lower stiction between the seal and the countersurface by 85%. Such a reduction can represent major benefits in the performance of semiconductor manufacturing tools.
{"title":"Surface modification of elastomeric seals to reduce stiction force on various surfaces","authors":"Feyzan Durn, Martina Weingärtner, M. Khosrawi, Renate Brielmann, M. Gulcur","doi":"10.1109/asmc54647.2022.9792516","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792516","url":null,"abstract":"Elastomers are used in many key applications in semiconductor manufacturing. They have the critical task to maintain vacuum integrity as seals, while elastomer end-effector pads, suction caps and other damping elements made of elastomers play important roles to maintain high efficiency of the semiconductor manufacturing tools. Stiction is a common problem in elastomer parts particularly in sealing applications. We developed Seal-Glide®, a plasma-based surface treatment method that has been successfully employed to overcome the stiction of the seal on the mating surface. Test methods for measuring static and dynamic stiction forces were developed in-house. Three types of test jigs were manufactured to demonstrate the stiction effect on stainless steel, aluminum, and quartz surfaces. To mimic the operating conditions, a single O-Ring was compressed between two plates to a pre-determined deflection using spacers, and the jig was conditioned in an oven at the target temperature. The jig was later uniaxially loaded in tension by a tensile machine at room temperature and the maximum force to separate the two plates was recorded as the stiction force. Cyclic compression tests were also performed on stainless steel and aluminum surfaces to demonstrate the seals’ performance in dynamic applications. Comparison of the tests performed with various sealing materials under the same testing conditions with and without plasma treatment demonstrated that plasma treatment could lower stiction between the seal and the countersurface by 85%. Such a reduction can represent major benefits in the performance of semiconductor manufacturing tools.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126653082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792495
Shiladitya Chakravorty, N. Nagarur
Queue time restricted zones present some unique challenges for dispatching and scheduling systems in a semiconductor manufacturing facility. In this study we present a real time algorithm for wafer dispatching in queue time zones based on cycle time predictions. Proposed prediction methodologies are based on backpropagation trained artificial neural network and radial basis function based neural network. Results obtained from the artificial neural network models are compared to each other and with a multivariate linear regression model for cycle time prediction.
{"title":"Analysis of Artificial Neural Network Based Algorithms For Real Time Dispatching","authors":"Shiladitya Chakravorty, N. Nagarur","doi":"10.1109/asmc54647.2022.9792495","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792495","url":null,"abstract":"Queue time restricted zones present some unique challenges for dispatching and scheduling systems in a semiconductor manufacturing facility. In this study we present a real time algorithm for wafer dispatching in queue time zones based on cycle time predictions. Proposed prediction methodologies are based on backpropagation trained artificial neural network and radial basis function based neural network. Results obtained from the artificial neural network models are compared to each other and with a multivariate linear regression model for cycle time prediction.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126050995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792507
Yu-Fan Chang, Hong-Ji Lee, Fu-Hsing Chou, Shih-Chin Lee, Yao-An Chung, N. Lian, T. Han, Tahone Yang, K. Chen, Chih-Yuan Lu
Control of slit bottom critical dimension (BCD) and the depth of etched recess upon underlying first polysilicon (PL) layer are important to avoid the slit patterns collapsing during the CMOS under array (CuA) type 3D NAND manufacturing. In this paper, we presents a case study to describe how machine learning assists on high aspect ratio deep trench etching under considering overall uniformity across the wafer. The machine learning model created through Neural Network (NN) modeling based on an etch starting baseline enables to predict desired slit BCD and the depth of PL recess locally on the center/middle/edge of the wafer from known process database including numerous process variants and etching profiles. The accuracy is at least >92% between the actual results and the predicted profile from the NN model we trained and validated. At the earlier stage, even if the modeling database size is limited, we still can apply it to reduce the turnaround time of etch development and work out a clear tuning trend through a series of virtual profile prediction and validation during NN modeling.
{"title":"Machine learning Assists on High Aspect Ratio Slit Trench Etching in 3D NAND","authors":"Yu-Fan Chang, Hong-Ji Lee, Fu-Hsing Chou, Shih-Chin Lee, Yao-An Chung, N. Lian, T. Han, Tahone Yang, K. Chen, Chih-Yuan Lu","doi":"10.1109/asmc54647.2022.9792507","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792507","url":null,"abstract":"Control of slit bottom critical dimension (BCD) and the depth of etched recess upon underlying first polysilicon (PL) layer are important to avoid the slit patterns collapsing during the CMOS under array (CuA) type 3D NAND manufacturing. In this paper, we presents a case study to describe how machine learning assists on high aspect ratio deep trench etching under considering overall uniformity across the wafer. The machine learning model created through Neural Network (NN) modeling based on an etch starting baseline enables to predict desired slit BCD and the depth of PL recess locally on the center/middle/edge of the wafer from known process database including numerous process variants and etching profiles. The accuracy is at least >92% between the actual results and the predicted profile from the NN model we trained and validated. At the earlier stage, even if the modeling database size is limited, we still can apply it to reduce the turnaround time of etch development and work out a clear tuning trend through a series of virtual profile prediction and validation during NN modeling.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128128781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With data storage capacity increasing, more memory cell stacks for three-dimensional NAND (3D NAND) devices are developed. When stacking more thin-film layers, the capability to form uniform high aspect ratio (HAR) structures becomes a key 3D NAND process step. Therefore, in 3D NAND manufacturing, etch process control is especially important. Etch processes generate HAR structures and defects are usually buried in the deep trenches or holes, which become inspection challenges. Defect control is important for semiconductor manufacturing to ensure device quality. In this study, a high landing energy (HiLE) e-beam defect inspection system with a wide landing energy operation range is utilized to compare scanning electron microscopy (SEM) images of different landing energy to get the best signal for defects of interest (DOI) that are buried in the deep vertical channel (VC) holes. A landing energy of 30KeV was determined to provide best DOI imaging. In addition, to reduce the burden of manual defect classification (MDC) and improve traditional algorithm limitations, a deep learning (DL)-based algorithm methodology is implemented that successfully demonstrates detection of DOI at ~6 μm depth within the VC holes of a 96-layer 3D NAND device, while also achieving auto defect classification (ADC) with >90% purity by each VC row.
{"title":"3D NAND vertical channel defect inspection and classification solution on a DL-based e-beam system : DI : Defect Inspection and Reduction","authors":"Cheng Hung Wu, Yen-Chun Chuan Sun, Rishabh Kushwaha, Piyush Bajpai, Shao Chang Cheng","doi":"10.1109/asmc54647.2022.9792511","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792511","url":null,"abstract":"With data storage capacity increasing, more memory cell stacks for three-dimensional NAND (3D NAND) devices are developed. When stacking more thin-film layers, the capability to form uniform high aspect ratio (HAR) structures becomes a key 3D NAND process step. Therefore, in 3D NAND manufacturing, etch process control is especially important. Etch processes generate HAR structures and defects are usually buried in the deep trenches or holes, which become inspection challenges. Defect control is important for semiconductor manufacturing to ensure device quality. In this study, a high landing energy (HiLE) e-beam defect inspection system with a wide landing energy operation range is utilized to compare scanning electron microscopy (SEM) images of different landing energy to get the best signal for defects of interest (DOI) that are buried in the deep vertical channel (VC) holes. A landing energy of 30KeV was determined to provide best DOI imaging. In addition, to reduce the burden of manual defect classification (MDC) and improve traditional algorithm limitations, a deep learning (DL)-based algorithm methodology is implemented that successfully demonstrates detection of DOI at ~6 μm depth within the VC holes of a 96-layer 3D NAND device, while also achieving auto defect classification (ADC) with >90% purity by each VC row.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128179896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792509
Yuanfu Yang, Min Sun
In advanced semiconductor process technology, lithography hotspot detection has become an essential task in design for manufacturability. The ability to detect and repair lithography hotspots that can affect printability is critical to improving yield and productivity. Machine learning technology has become a powerful tool in a variety of applications, from finance to manufacturing and computer vision. The use of quantum systems to process classical data using machine learning algorithms has created an emerging field of research, namely quantum machine learning (QML). We explore the possibility of converting a novel machine learning model to a hybrid quantum-classical machine learning that benefits from using variational quantum layers. We show that this hybrid model can perform similar to the classical approach. In addition, we explore parametrized quantum circuits (PQC) with different expressibility and entangling capacities. Then we compare their training performance to quantify the expected benefits. These results can be used to build a future roadmap to develop circuit-based hybrid quantum-classical machine learning for lithography hotspot detection.
{"title":"Hybrid Quantum-Classical Machine Learning for Lithography Hotspot Detection","authors":"Yuanfu Yang, Min Sun","doi":"10.1109/asmc54647.2022.9792509","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792509","url":null,"abstract":"In advanced semiconductor process technology, lithography hotspot detection has become an essential task in design for manufacturability. The ability to detect and repair lithography hotspots that can affect printability is critical to improving yield and productivity. Machine learning technology has become a powerful tool in a variety of applications, from finance to manufacturing and computer vision. The use of quantum systems to process classical data using machine learning algorithms has created an emerging field of research, namely quantum machine learning (QML). We explore the possibility of converting a novel machine learning model to a hybrid quantum-classical machine learning that benefits from using variational quantum layers. We show that this hybrid model can perform similar to the classical approach. In addition, we explore parametrized quantum circuits (PQC) with different expressibility and entangling capacities. Then we compare their training performance to quantify the expected benefits. These results can be used to build a future roadmap to develop circuit-based hybrid quantum-classical machine learning for lithography hotspot detection.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126017765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792489
S. Panchangam, Keerthi Gowdaru
Semiconductor processing chambers operate in controlled but aggressive operating conditions (chemistry, plasma, high temperature etc.) Owing to this, the design of these equipment requires developing robust and reliable hardware and software solutions. Equipment downtime due to reliability issues can have cost implications both for customer in terms of tool down time (reduced throughput) and for equipment manufacturer in terms of high warranty costs and customer trust deficit. The objective of the paper is to model the failure rate of “critical” spare parts to give customers guidelines with respect to optimum replacement schedule. A stochastics-based reliability model has been proposed in the current work. The model utilizes historical field failure data coming from various tools, normalizing this data to current operating conditions, segregating competent failure modes, and categorizing reliability and supplier issues using Weibull analysis. The result of the analysis helps in identifying failure mitigation measures and recommending optimal maintenance schedules intervals using cost function approach incorporating Weibull parameters.
{"title":"Stochastics Based Reliability Model for Optimal Scheduled Maintenance of Semiconductor Tools","authors":"S. Panchangam, Keerthi Gowdaru","doi":"10.1109/asmc54647.2022.9792489","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792489","url":null,"abstract":"Semiconductor processing chambers operate in controlled but aggressive operating conditions (chemistry, plasma, high temperature etc.) Owing to this, the design of these equipment requires developing robust and reliable hardware and software solutions. Equipment downtime due to reliability issues can have cost implications both for customer in terms of tool down time (reduced throughput) and for equipment manufacturer in terms of high warranty costs and customer trust deficit. The objective of the paper is to model the failure rate of “critical” spare parts to give customers guidelines with respect to optimum replacement schedule. A stochastics-based reliability model has been proposed in the current work. The model utilizes historical field failure data coming from various tools, normalizing this data to current operating conditions, segregating competent failure modes, and categorizing reliability and supplier issues using Weibull analysis. The result of the analysis helps in identifying failure mitigation measures and recommending optimal maintenance schedules intervals using cost function approach incorporating Weibull parameters.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132038063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792491
Yujie Xiao, S. Sun, Ghit Guan Goh, Guanyu Zhou, Kim Foong Kong
BF2 may be implanted in a silicon wafer to create doped regions. When a sufficiently energetic BF2 molecule collides with a Si crystal, the B-F bond will be broken and both atoms will enter the Si crystal. Since F is an interstitial element in the Si lattice, the higher the dose/energy used for BF2 implantation, the higher the number of F atoms implanted. During photoresist strip, plasma generates Hradicals that penetrate the surface SiO2 and substrate, react with F-implants to form gaseous HF. During annealing, HF gas evolves, causing delamination in the surface oxide film. Subsequent SiN film deposition will enhance the delamination, which will be detected as a bubble defect (Fig. 1). This article evaluates a new photoresist strip recipe with shorter time and pins-up, as well as a different gas, to reduce fluorine outgassing, to eliminate subsequent process bubble defect issues.
{"title":"Optimizing Photoresist Strip to reduce fluorine outgassing causing bubble defect","authors":"Yujie Xiao, S. Sun, Ghit Guan Goh, Guanyu Zhou, Kim Foong Kong","doi":"10.1109/asmc54647.2022.9792491","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792491","url":null,"abstract":"BF2 may be implanted in a silicon wafer to create doped regions. When a sufficiently energetic BF2 molecule collides with a Si crystal, the B-F bond will be broken and both atoms will enter the Si crystal. Since F is an interstitial element in the Si lattice, the higher the dose/energy used for BF2 implantation, the higher the number of F atoms implanted. During photoresist strip, plasma generates Hradicals that penetrate the surface SiO2 and substrate, react with F-implants to form gaseous HF. During annealing, HF gas evolves, causing delamination in the surface oxide film. Subsequent SiN film deposition will enhance the delamination, which will be detected as a bubble defect (Fig. 1). This article evaluates a new photoresist strip recipe with shorter time and pins-up, as well as a different gas, to reduce fluorine outgassing, to eliminate subsequent process bubble defect issues.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130092619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792482
Erik Collart, A. Longley, Dirk Gordon, John Nordquist, Paul Matthews
Many critical steps in semi manufacturing need high vacuum or controlled ambient conditions. This need is met through a very extensive network of vacuum and abatement systems. In a typical fab this network consists of many thousands of pumps, abatement, and ancillary equipment. This provides and maintains vacuum levels and quality, two key process parameters. Applying Smart Manufacturing and Predictive Maintenance is key to Operational Excellence and reducing risk and uncertainty associated with unplanned vacuum and abatement downs. In this paper we focus on cryogenic pumps and discuss using both rule-based and statistical models (ML models) to provide maintenance guidance and maintenance prioritization. Rule-based case studies include Helium circuit contamination detection and Cryo regeneration fault detection. Our ML models, were developed, trained, and verified on extensive HVM pump data. They were applied to 3 different pump types and scored high on key binary classifier rate metrics, as high as 93% accuracy and 87% recall depending on pump type. As we collect more data our models will continue to learn and improve and further reduce risk and uncertainty.
{"title":"Predictive Maintenance Practices for Cryogenic Pumps in Semiconductor Manufacturing","authors":"Erik Collart, A. Longley, Dirk Gordon, John Nordquist, Paul Matthews","doi":"10.1109/asmc54647.2022.9792482","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792482","url":null,"abstract":"Many critical steps in semi manufacturing need high vacuum or controlled ambient conditions. This need is met through a very extensive network of vacuum and abatement systems. In a typical fab this network consists of many thousands of pumps, abatement, and ancillary equipment. This provides and maintains vacuum levels and quality, two key process parameters. Applying Smart Manufacturing and Predictive Maintenance is key to Operational Excellence and reducing risk and uncertainty associated with unplanned vacuum and abatement downs. In this paper we focus on cryogenic pumps and discuss using both rule-based and statistical models (ML models) to provide maintenance guidance and maintenance prioritization. Rule-based case studies include Helium circuit contamination detection and Cryo regeneration fault detection. Our ML models, were developed, trained, and verified on extensive HVM pump data. They were applied to 3 different pump types and scored high on key binary classifier rate metrics, as high as 93% accuracy and 87% recall depending on pump type. As we collect more data our models will continue to learn and improve and further reduce risk and uncertainty.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126938231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792517
Jianhua Yin, Ian Chen, Rakesh Chokanathan, Suraj Gyawali, Yupei Du, Yuansong Wang, Xue Mei Liu, CT Lim, Wen Zhi Gao
Fast product yield learning rate is very critical to shorten the design to market cycle time, especially for mobile products with only 2~3-year product lifetime. Based on the typical yield learning curve as a function of a product’ life cycle, systematic defects resulting from the interaction between design and process may dominate product yield loss. Root cause identification and technical solutions of these systematics are very critical to achieve a significant improvement in the stage of production ramp-up stage. In this paper, a yield improvement methodology is presented to address design systematics and has been successfully deployed in multiple cases during volume ramp-up production in 14nm and beyond technology.
{"title":"Yield Improvement Methodology with addressing Design Systematics during Production Ramp-up","authors":"Jianhua Yin, Ian Chen, Rakesh Chokanathan, Suraj Gyawali, Yupei Du, Yuansong Wang, Xue Mei Liu, CT Lim, Wen Zhi Gao","doi":"10.1109/asmc54647.2022.9792517","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792517","url":null,"abstract":"Fast product yield learning rate is very critical to shorten the design to market cycle time, especially for mobile products with only 2~3-year product lifetime. Based on the typical yield learning curve as a function of a product’ life cycle, systematic defects resulting from the interaction between design and process may dominate product yield loss. Root cause identification and technical solutions of these systematics are very critical to achieve a significant improvement in the stage of production ramp-up stage. In this paper, a yield improvement methodology is presented to address design systematics and has been successfully deployed in multiple cases during volume ramp-up production in 14nm and beyond technology.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124914254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792523
Doug Suerich, Trevor McIlroy
Semiconductor cluster tools add an integral component to the modern semiconductor manufacturing process. These complex tools provide a flexible deployment option to group multiple processing steps into a single piece of equipment, allowing for more efficient processing. They also contribute to a reduction in the number of times a wafer must go through the atmospheric-vacuum-atmospheric cycle. These highly automated tools present a complex scheduling challenge where process-specific requirements are balanced against a need to achieve maximum wafer throughput in a fault tolerant manner. Due to the global chip shortage, many semiconductor fabs have started to demand increased throughput from the equipment on their manufacturing floors. While process timing is often constrained by physics, opportunities do exist to reduce wait time waste by leveraging machine learning to optimize the manner in which substrates are scheduled within complex semiconductor cluster tools.Previous work demonstrated that a reinforcement learning algorithm is suitable for automated generation of efficient planners for both simple and complex tools [2]. This investigation looked at techniques that could be used to move scheduler optimization away from offline cloud analysis and into real time, on-tool production planning.
{"title":"Artificial Intelligence for Real Time Cluster Tool Scheduling : EO: Equipment Optimization","authors":"Doug Suerich, Trevor McIlroy","doi":"10.1109/asmc54647.2022.9792523","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792523","url":null,"abstract":"Semiconductor cluster tools add an integral component to the modern semiconductor manufacturing process. These complex tools provide a flexible deployment option to group multiple processing steps into a single piece of equipment, allowing for more efficient processing. They also contribute to a reduction in the number of times a wafer must go through the atmospheric-vacuum-atmospheric cycle. These highly automated tools present a complex scheduling challenge where process-specific requirements are balanced against a need to achieve maximum wafer throughput in a fault tolerant manner. Due to the global chip shortage, many semiconductor fabs have started to demand increased throughput from the equipment on their manufacturing floors. While process timing is often constrained by physics, opportunities do exist to reduce wait time waste by leveraging machine learning to optimize the manner in which substrates are scheduled within complex semiconductor cluster tools.Previous work demonstrated that a reinforcement learning algorithm is suitable for automated generation of efficient planners for both simple and complex tools [2]. This investigation looked at techniques that could be used to move scheduler optimization away from offline cloud analysis and into real time, on-tool production planning.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125877356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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