The with-in-wafer uniformity and geometry of the CMP process varies across the life of consumables. The pre layer geometry and thickness significantly affect the post CMP process uniformity and geometry of the wafer. Inconsistency in post CMP wafer uniformity and geometry affects downstream process margin which leads to various yield issues like open or short circuit between contact to gate. Wafer geometry is measured, and out-of-control wafers are reworked to be within specified control limits. OOC and rework in CMP due to consumable caused variations in CMP and upstream process contribution to variation. To reduce rework, CMP is normally employed with process controls like APC (Advanced Process Control) and Endpoints. APC can be effective if integrated closely with CMP system with reduced delays in feedback, while Endpoints are challenging, since the oxide CMP layer is required for an endpoint within the layer (i.e., stop in layer), which makes it inaccurate and small changes in underlying layer properties affect endpoints to be less accurate. iAPC (integrated Advanced Process Control) is tightly integrated with the CMP polishing systems, which reduces feedback delays with a faster interface with the tool to achieve better process control. Modeling strategy of iAPC for CMP is discussed here in detail to achieve desired process control across consumable life and across tool pool. The modeling approach is segmented by modeling across wafer radial regions to include significance of polishing head’s zone to zone interaction and to get the wafer’s geometry characteristics on each region with consumable influenced by each polishing head zone. Thickness Out-of-Control (OOC) is significantly reduced with iAPC segmented modeling, and the model of identical process schemes is grouped together for continuous feedback across consumable life, which will be discussed in later sections of this paper.
{"title":"CMP Process Control With iAPC Segmented Modeling to Achieve Desired With-in-Wafer Uniformity and Geometry Across Consumable Life","authors":"Logamanya Rukmangathan Duraisamy, Karthik Sankar, Gerry Dizon, Sreejith Ajithkumar, Yew Siew Chong Mentor","doi":"10.1109/asmc54647.2022.9792498","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792498","url":null,"abstract":"The with-in-wafer uniformity and geometry of the CMP process varies across the life of consumables. The pre layer geometry and thickness significantly affect the post CMP process uniformity and geometry of the wafer. Inconsistency in post CMP wafer uniformity and geometry affects downstream process margin which leads to various yield issues like open or short circuit between contact to gate. Wafer geometry is measured, and out-of-control wafers are reworked to be within specified control limits. OOC and rework in CMP due to consumable caused variations in CMP and upstream process contribution to variation. To reduce rework, CMP is normally employed with process controls like APC (Advanced Process Control) and Endpoints. APC can be effective if integrated closely with CMP system with reduced delays in feedback, while Endpoints are challenging, since the oxide CMP layer is required for an endpoint within the layer (i.e., stop in layer), which makes it inaccurate and small changes in underlying layer properties affect endpoints to be less accurate. iAPC (integrated Advanced Process Control) is tightly integrated with the CMP polishing systems, which reduces feedback delays with a faster interface with the tool to achieve better process control. Modeling strategy of iAPC for CMP is discussed here in detail to achieve desired process control across consumable life and across tool pool. The modeling approach is segmented by modeling across wafer radial regions to include significance of polishing head’s zone to zone interaction and to get the wafer’s geometry characteristics on each region with consumable influenced by each polishing head zone. Thickness Out-of-Control (OOC) is significantly reduced with iAPC segmented modeling, and the model of identical process schemes is grouped together for continuous feedback across consumable life, which will be discussed in later sections of this paper.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125476612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792531
Leon van Dijk, K. M. Adal, Sepideh Golmakaniyoon, B. Le-Gratiet, Niyam Haque, Reza Sahraeian, A. Lam, Richard J. F. van Haren
Computational overlay is developed based on a hybrid approach that combines physical modeling with machine learning. The performance of computational overlay is evaluated on the critical overlay between contact and gate layers. A prediction performance of ~0.7 is achieved in terms of the R2 statistic. The computational overlay model is able to follow variations in overlay, and can be used to establish a link between sources of overlay errors and the actual overlay performance. Furthermore, we will assess how computational overlay-based exposure corrections can be used to reduce the intra-field magnification error variation that is observed.
{"title":"Computational overlay as enabler for enhanced on-product overlay control","authors":"Leon van Dijk, K. M. Adal, Sepideh Golmakaniyoon, B. Le-Gratiet, Niyam Haque, Reza Sahraeian, A. Lam, Richard J. F. van Haren","doi":"10.1109/asmc54647.2022.9792531","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792531","url":null,"abstract":"Computational overlay is developed based on a hybrid approach that combines physical modeling with machine learning. The performance of computational overlay is evaluated on the critical overlay between contact and gate layers. A prediction performance of ~0.7 is achieved in terms of the R2 statistic. The computational overlay model is able to follow variations in overlay, and can be used to establish a link between sources of overlay errors and the actual overlay performance. Furthermore, we will assess how computational overlay-based exposure corrections can be used to reduce the intra-field magnification error variation that is observed.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792474
W. Tu, Yan Wang, Jing Qiu, Haiyang Zhang
The metal gate (MG) height composed of complicated work function metal (WFM) films is crucial to the device and yield performance at the FinFET Technology. The parasitic capacitance between MGs and conductors gets increased with the increasing MG height while an disproportional relation is found between the channel resistance and MG height. In this paper, temperature sensitivities of various MG films were investigated and a new MG structure was proposed for the Hydra implementation. The MG height variation across the 300mm wafer was controlled with a Hydra based MG etching on the proposed sidewall WFM chamfered structure. The final MG height uniformity was improved 24%. Current work could be extended to the control of the wafer-to-wafer MG height variation.
{"title":"A Metal Gate Height Variation Control Method by the Metal Gate Etch at the FinFET Technology","authors":"W. Tu, Yan Wang, Jing Qiu, Haiyang Zhang","doi":"10.1109/asmc54647.2022.9792474","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792474","url":null,"abstract":"The metal gate (MG) height composed of complicated work function metal (WFM) films is crucial to the device and yield performance at the FinFET Technology. The parasitic capacitance between MGs and conductors gets increased with the increasing MG height while an disproportional relation is found between the channel resistance and MG height. In this paper, temperature sensitivities of various MG films were investigated and a new MG structure was proposed for the Hydra implementation. The MG height variation across the 300mm wafer was controlled with a Hydra based MG etching on the proposed sidewall WFM chamfered structure. The final MG height uniformity was improved 24%. Current work could be extended to the control of the wafer-to-wafer MG height variation.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125685173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792512
A. Nourbakhsh, Lan Yu, Tyler Sherwood, Xing Chen, Siddarth A. Krishnan, Py Hung, A. Cepler, Marjorie Cheng, Yonatan Oren
In-line, nondestructive strain measurements are obtained on high aspect ratio 3D device structures using Raman scatterometry on full 300-mm wafers. In-line Raman spectroscopy allows for the monitoring of high-volume manufacturing, thereby offering benefits that include cost savings and faster and improved process control.
{"title":"In-Line Raman Spectroscopy: High-Throughput Strain Metrology for 3D Devices","authors":"A. Nourbakhsh, Lan Yu, Tyler Sherwood, Xing Chen, Siddarth A. Krishnan, Py Hung, A. Cepler, Marjorie Cheng, Yonatan Oren","doi":"10.1109/asmc54647.2022.9792512","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792512","url":null,"abstract":"In-line, nondestructive strain measurements are obtained on high aspect ratio 3D device structures using Raman scatterometry on full 300-mm wafers. In-line Raman spectroscopy allows for the monitoring of high-volume manufacturing, thereby offering benefits that include cost savings and faster and improved process control.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116545359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792503
Gary Xing, P. Werbaneth, Randy Treur, Phil Barros
Modular gas delivery systems replaced conventional gas panels in the semiconductor capital equipment industry for “dry” manufacturing processes such as plasma etch, chemical vapor deposition, physical vapor deposition, epitaxy, and dry strip. Modular gas delivery systems were adopted as a result of numerous benefits the modular architecture offers over conventional system designs. These benefits include smaller size/smaller footprint, easily customizable configurability, ease of maintenance, and increased equipment productivity. From our position as a gas panel supplier to major dry processing equipment manufacturers we have observed and responded to the customer-driven conversion to modular gas delivery systems. We think the same advantages of modularity apply in liquid chemical delivery applications, for example wet cleaning and surface removal, and we are in the process of converting conventional chemical delivery systems into modular-based ones. We present here details about the industry’s conversion from conventional to modular gas delivery systems, extracting the lessons learned, and applying those best practices to modular architecture chemical delivery systems used in the major wet tool applications, including wet cleaning, Electrochemical Deposition (ECD), and Chemical Mechanical Planarization (CMP). We will also discuss three areas of focuses of development on the modular system architecture: serviceability, sealing mechanisms, and contamination control.
{"title":"Evolution of Gas Delivery and Liquid Delivery Systems in Semiconductor Processing Equipment: Modular Architectures Drive Configurability Options and Improve Tool Productivity : EO: Equipment Optimization","authors":"Gary Xing, P. Werbaneth, Randy Treur, Phil Barros","doi":"10.1109/asmc54647.2022.9792503","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792503","url":null,"abstract":"Modular gas delivery systems replaced conventional gas panels in the semiconductor capital equipment industry for “dry” manufacturing processes such as plasma etch, chemical vapor deposition, physical vapor deposition, epitaxy, and dry strip. Modular gas delivery systems were adopted as a result of numerous benefits the modular architecture offers over conventional system designs. These benefits include smaller size/smaller footprint, easily customizable configurability, ease of maintenance, and increased equipment productivity. From our position as a gas panel supplier to major dry processing equipment manufacturers we have observed and responded to the customer-driven conversion to modular gas delivery systems. We think the same advantages of modularity apply in liquid chemical delivery applications, for example wet cleaning and surface removal, and we are in the process of converting conventional chemical delivery systems into modular-based ones. We present here details about the industry’s conversion from conventional to modular gas delivery systems, extracting the lessons learned, and applying those best practices to modular architecture chemical delivery systems used in the major wet tool applications, including wet cleaning, Electrochemical Deposition (ECD), and Chemical Mechanical Planarization (CMP). We will also discuss three areas of focuses of development on the modular system architecture: serviceability, sealing mechanisms, and contamination control.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132614152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792520
Benjamin Kovács, Pierre Tassel, Ramsha Ali, Mohammed M. S. El-Kholany, M. Gebser, Georg Seidel
Optimal scheduling of semiconductor fabs is a huge challenge due to the problem scale and complexity. New dispatching strategies are usually developed and tested using simulators of different fidelity levels. This work presents a scalable, open-source tool for simulating factories up to real-world size, aiming to support the research into new scheduling algorithms from prototyping to large-scale experiments. The simulator comes with a declarative environment definition framework and is out of the box usable with existing reinforcement learning methods, priority-based rules, or evolutionary algorithms. We verify our tool on large-scale public instances and provide proof-of-concept demonstrations of the reinforcement learning interface’s usage.
{"title":"A Customizable Simulator for Artificial Intelligence Research to Schedule Semiconductor Fabs","authors":"Benjamin Kovács, Pierre Tassel, Ramsha Ali, Mohammed M. S. El-Kholany, M. Gebser, Georg Seidel","doi":"10.1109/asmc54647.2022.9792520","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792520","url":null,"abstract":"Optimal scheduling of semiconductor fabs is a huge challenge due to the problem scale and complexity. New dispatching strategies are usually developed and tested using simulators of different fidelity levels. This work presents a scalable, open-source tool for simulating factories up to real-world size, aiming to support the research into new scheduling algorithms from prototyping to large-scale experiments. The simulator comes with a declarative environment definition framework and is out of the box usable with existing reinforcement learning methods, priority-based rules, or evolutionary algorithms. We verify our tool on large-scale public instances and provide proof-of-concept demonstrations of the reinforcement learning interface’s usage.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133979977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792496
Russell McCabe, Suraj KaulKevin Ward, Ronilo Acosta, Bhaskar Pant
Dual STI CMP step recombination was implemented to reduce the variation of the floating gate polysilicon thickness), resulting in less failure from poly foot. Initial qualification of the single oxide CMP showed elevated scratch count, which required DOE modeling with slurry flow rate and tool upgrades to reduce the scratch counts. Once qualified, the recombination showed numerous positive results at probe and post-assembly yield Additional benefits along with the variation reduction was the cycle time improvement along with the cost savings due to merging the dual CMP step into a single step. This change also enabled capacity improvement by qualifying it to run with other technologies and reduced Server SBL(Statistical Bin Limits) breaches driven by poly foot fails.
{"title":"NOR yield enhancement and downstream process variation reduction by STI CMP optimization","authors":"Russell McCabe, Suraj KaulKevin Ward, Ronilo Acosta, Bhaskar Pant","doi":"10.1109/asmc54647.2022.9792496","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792496","url":null,"abstract":"Dual STI CMP step recombination was implemented to reduce the variation of the floating gate polysilicon thickness), resulting in less failure from poly foot. Initial qualification of the single oxide CMP showed elevated scratch count, which required DOE modeling with slurry flow rate and tool upgrades to reduce the scratch counts. Once qualified, the recombination showed numerous positive results at probe and post-assembly yield Additional benefits along with the variation reduction was the cycle time improvement along with the cost savings due to merging the dual CMP step into a single step. This change also enabled capacity improvement by qualifying it to run with other technologies and reduced Server SBL(Statistical Bin Limits) breaches driven by poly foot fails.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133677715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792524
R. Duru, I. Mica, J. Frascaroli, P. Bellanger
Room temperature photoluminescence imaging is assessed in industrial environment to detect slip line formation on 300 mm resistive silicon wafers used for Insulated Gate Bipolar Transistor (IGBT) technology and to characterize associated dislocations. The technique, with a combined use of macro and micro scale acquisitions, enables inline detection, characterization, and quantification of defects, allowing efficient process optimization and production monitoring.
{"title":"Photoluminescence imaging for slip line detection and characterization in silicon substrates","authors":"R. Duru, I. Mica, J. Frascaroli, P. Bellanger","doi":"10.1109/asmc54647.2022.9792524","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792524","url":null,"abstract":"Room temperature photoluminescence imaging is assessed in industrial environment to detect slip line formation on 300 mm resistive silicon wafers used for Insulated Gate Bipolar Transistor (IGBT) technology and to characterize associated dislocations. The technique, with a combined use of macro and micro scale acquisitions, enables inline detection, characterization, and quantification of defects, allowing efficient process optimization and production monitoring.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"362 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133301617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792504
M. Haberjahn, S. Srichandan, Yulia Polak, Georg Ehrentraut, Franz Heider
Three different in-line metrology techniques are combined to calculate the bottom width of trenches, 3μm and 42μm deep. CD-SEM gives the top critical dimension (CD) of trenches and scatterometry provides the trench depth. An average value for the trench bottom width or bottom CD is obtained from a mass loss determination with a pre- and post-etch measurement, in combination with the available top CD and depth values. This hybrid metrology approach has been demonstrated in case of the 3μm deep trench, where the conventional physical scatterometry modelling with rigorous coupled wave analysis (RCWA) is used to determine the trench depth and shape. The physical RCWA modelling is not applicable to the 42μm deep trenches with a pitch of >5μm. Hence, the proposed combined metrology method is verified with SEM cross-sections from wafers with different trench side-wall angles.
{"title":"Combination of Mass Metrology with Scatterometry to obtain bottom Width of deep Trenches : AM: Advanced Metrology","authors":"M. Haberjahn, S. Srichandan, Yulia Polak, Georg Ehrentraut, Franz Heider","doi":"10.1109/asmc54647.2022.9792504","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792504","url":null,"abstract":"Three different in-line metrology techniques are combined to calculate the bottom width of trenches, 3μm and 42μm deep. CD-SEM gives the top critical dimension (CD) of trenches and scatterometry provides the trench depth. An average value for the trench bottom width or bottom CD is obtained from a mass loss determination with a pre- and post-etch measurement, in combination with the available top CD and depth values. This hybrid metrology approach has been demonstrated in case of the 3μm deep trench, where the conventional physical scatterometry modelling with rigorous coupled wave analysis (RCWA) is used to determine the trench depth and shape. The physical RCWA modelling is not applicable to the 42μm deep trenches with a pitch of >5μm. Hence, the proposed combined metrology method is verified with SEM cross-sections from wafers with different trench side-wall angles.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116434493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792484
Russell McCabe, R. Chaudhuri, S. Spangler, Russ Heller, A. Tahraoui, Emmett Synder, W. Simpson, Michael Frachel, Glen Martin
A systematic approach for root cause identification and mitigation of poly CMP underpolish increase in high volume manufacturing is presented. Different aspects of product quality and yield enhancement has been highlighted utilizing appropriate inline metrology and wafer probe data.
{"title":"Root Cause Identification and Mitigation of Polysilicon CMP Underpolish Increase in DRAM Manufacturing","authors":"Russell McCabe, R. Chaudhuri, S. Spangler, Russ Heller, A. Tahraoui, Emmett Synder, W. Simpson, Michael Frachel, Glen Martin","doi":"10.1109/asmc54647.2022.9792484","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792484","url":null,"abstract":"A systematic approach for root cause identification and mitigation of poly CMP underpolish increase in high volume manufacturing is presented. Different aspects of product quality and yield enhancement has been highlighted utilizing appropriate inline metrology and wafer probe data.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"8 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131037979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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