Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792525
C. Boye, DukKyun Moon, Steven McDermott, Norbert Arnold, N. Saulnier, F. Levitov, Sam-Kyu Choi, A. Goldenshtein, Uri Smolyan, N. Amit, I. Ok, I. Saraf
Critical Dimension (CD) measurement control strategies typically include measurements taken post plasma etch in a structure located in the kerf or street area specifically designed for this measurement. This type of measurement strategy is standard for control of CD variability across wafer. It is of interest to evaluate within macro CD variation of new designs at via levels by direct measurement of vias within the macro to characterize in-line sources of opens and resistance issues at electrical test. The steps taken and challenges encountered to develop a multi-via CD measurement in a testable macro and subsequent correlation to electrical test results will be described.
{"title":"Electrically Testable Product Macro Multi-via Measurement for Within Die CD Variation","authors":"C. Boye, DukKyun Moon, Steven McDermott, Norbert Arnold, N. Saulnier, F. Levitov, Sam-Kyu Choi, A. Goldenshtein, Uri Smolyan, N. Amit, I. Ok, I. Saraf","doi":"10.1109/asmc54647.2022.9792525","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792525","url":null,"abstract":"Critical Dimension (CD) measurement control strategies typically include measurements taken post plasma etch in a structure located in the kerf or street area specifically designed for this measurement. This type of measurement strategy is standard for control of CD variability across wafer. It is of interest to evaluate within macro CD variation of new designs at via levels by direct measurement of vias within the macro to characterize in-line sources of opens and resistance issues at electrical test. The steps taken and challenges encountered to develop a multi-via CD measurement in a testable macro and subsequent correlation to electrical test results will be described.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121331198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792500
Zhixing Li, Zhangyang Wang, Weiping Shi
The most widely adopted approach for defect analysis in the semiconductor manufacturing plant (fab) is the automatic defect classification (ADC) that uses images taken by optical microscopy or scanning electron microscopy (SEM) to classify defects. The state-of-art ADC methods are based on Convolutional Neural Network (CNN) but are expensive in revising or expanding defect categories, and low in classification accuracy. In this paper, we propose a novel method for ADC based on Deep Neural Network (DNN) with two innovations. 1) We use a decision tree of DNNs to classify each image into successively refined categories. In contrast to a single CNN/DNN, the benefit of a decision tree of DNNs is that the latter is significantly smaller in total size and faster in training time. 2) We create a mechanism of self-learning by reporting images whose classification confidences are below a threshold as “Unknown”. Once the unknown images are manually labeled, the cases are sent back for a quick re-training. This is possible since the decision tree of DNNs permits the re-training of one or a few DNNs instead of the entire system. Experiment results show that the proposed approach achieves 100% classification accuracy, in which 2% are classified as “Unknown” and require manual classification which will be used to re-train the DNNs. The re-training time of our ADC based on decision tree DNNs is about 60 times faster than ADCs based on a single CNN/DNN.
{"title":"Automatic Wafer Defect Classification Based on Decision Tree of Deep Neural Network","authors":"Zhixing Li, Zhangyang Wang, Weiping Shi","doi":"10.1109/asmc54647.2022.9792500","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792500","url":null,"abstract":"The most widely adopted approach for defect analysis in the semiconductor manufacturing plant (fab) is the automatic defect classification (ADC) that uses images taken by optical microscopy or scanning electron microscopy (SEM) to classify defects. The state-of-art ADC methods are based on Convolutional Neural Network (CNN) but are expensive in revising or expanding defect categories, and low in classification accuracy. In this paper, we propose a novel method for ADC based on Deep Neural Network (DNN) with two innovations. 1) We use a decision tree of DNNs to classify each image into successively refined categories. In contrast to a single CNN/DNN, the benefit of a decision tree of DNNs is that the latter is significantly smaller in total size and faster in training time. 2) We create a mechanism of self-learning by reporting images whose classification confidences are below a threshold as “Unknown”. Once the unknown images are manually labeled, the cases are sent back for a quick re-training. This is possible since the decision tree of DNNs permits the re-training of one or a few DNNs instead of the entire system. Experiment results show that the proposed approach achieves 100% classification accuracy, in which 2% are classified as “Unknown” and require manual classification which will be used to re-train the DNNs. The re-training time of our ADC based on decision tree DNNs is about 60 times faster than ADCs based on a single CNN/DNN.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116450822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792493
R. Varma, Jennifer Dossee Nunes
This paper will discuss the challenges associated with the constant evolution of IC device dimensions, and the need for carriers that can adapt quickly to the change in form factor but still maintain JEDEC standards for compatibility with existing equipment sets and pick & place tools. The paper will present a new technology inspired by gecko fibril microstructures with reversible adhesion that offers a unique approach to device handling.
{"title":"Novel Micro-Textured Film Offers Promise in Universal Handling of 3D Devices","authors":"R. Varma, Jennifer Dossee Nunes","doi":"10.1109/asmc54647.2022.9792493","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792493","url":null,"abstract":"This paper will discuss the challenges associated with the constant evolution of IC device dimensions, and the need for carriers that can adapt quickly to the change in form factor but still maintain JEDEC standards for compatibility with existing equipment sets and pick & place tools. The paper will present a new technology inspired by gecko fibril microstructures with reversible adhesion that offers a unique approach to device handling.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123397123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792481
C-P. Chen, S. Goswami, R. Gossman
Integrated Circuits (ICs) fabricated in Silicon Carbide (SiC) has been the most suitable candidate for high-temperature (> 500 °C) applications. Such high temperature resiliency is strongly dependent on the selection and combination of interconnect metal with the dielectric films for passivation. The protection of interconnect metal from oxidation using suitable passivation films, and the adhesion between the bond pad and the dielectric layers is functionally critical in high temperature environment. This paper reports promising results towards selecting improved passivation dielectric films, as well as metallization for bond pad interfaces. Early results are presented with ring oscillator (ROs) test circuits at prolonged 500 °C operation.
{"title":"High temperature resilience of deposited films in harsh environment semiconductor devices : Topics/categories: Non-silicon","authors":"C-P. Chen, S. Goswami, R. Gossman","doi":"10.1109/asmc54647.2022.9792481","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792481","url":null,"abstract":"Integrated Circuits (ICs) fabricated in Silicon Carbide (SiC) has been the most suitable candidate for high-temperature (> 500 °C) applications. Such high temperature resiliency is strongly dependent on the selection and combination of interconnect metal with the dielectric films for passivation. The protection of interconnect metal from oxidation using suitable passivation films, and the adhesion between the bond pad and the dielectric layers is functionally critical in high temperature environment. This paper reports promising results towards selecting improved passivation dielectric films, as well as metallization for bond pad interfaces. Early results are presented with ring oscillator (ROs) test circuits at prolonged 500 °C operation.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127060821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792519
Russell McCabe, R. Chaudhuri, S. Spangler, Lauren Kerstetter, Femi Aborisade, Raita Hoech
Reducing reworks in manufacturing process is important for product quality, as well cycle time and cost impact. Contact oxide stop on film process has historically had one of the higher rework percentages due to underpolish. Variation in the process from various sources leading to thickness variation and challenges in process control, lead to these reworks. A multiple phase process conversion was started with intent of reducing cost, as well as reducing process variation, that results in the reworks.
{"title":"Multiphased Process Optimization for CMP Variation Reduction in High Volume Manufacturing","authors":"Russell McCabe, R. Chaudhuri, S. Spangler, Lauren Kerstetter, Femi Aborisade, Raita Hoech","doi":"10.1109/asmc54647.2022.9792519","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792519","url":null,"abstract":"Reducing reworks in manufacturing process is important for product quality, as well cycle time and cost impact. Contact oxide stop on film process has historically had one of the higher rework percentages due to underpolish. Variation in the process from various sources leading to thickness variation and challenges in process control, lead to these reworks. A multiple phase process conversion was started with intent of reducing cost, as well as reducing process variation, that results in the reworks.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133992677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792534
E. J. Khor, Jian Xun Sun, Zin Tun Thant, R. Chockalingam, W. Hsu, P. Somasuntharam, K. S. Yew, H. Yap, Juan Boon Tan
One of the key challenges to qualify Metal Insulator Metal (MIM) capacitor passive devices for automotive grade integrated semiconductor manufacturing is to address the early breakdown failure mode observed with voltage ramp (Vramp) testing. Understanding the early failure mechanism is important in order to improve the process condition before subjecting the device to Time-Dependent-Dielectric Breakdown (TDDB) stress as the ultimate test. In this paper, we investigated the defect density performance across a design of experiment on the related process condition and collected Vramp test on a vast sample size of 34,000 sites per split to obtain a statistically significant electrical response. We addressed two early failure mechanisms and showed improvements in those with improved processing conditions for MIM capacitor with 1fF/um2 capacitance density. This MIM capacitor was embedded within the fabrication of the dual damascene copper interconnect process.
{"title":"A perspective of MIM defect density performance improvement for automotive chip fabrication","authors":"E. J. Khor, Jian Xun Sun, Zin Tun Thant, R. Chockalingam, W. Hsu, P. Somasuntharam, K. S. Yew, H. Yap, Juan Boon Tan","doi":"10.1109/asmc54647.2022.9792534","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792534","url":null,"abstract":"One of the key challenges to qualify Metal Insulator Metal (MIM) capacitor passive devices for automotive grade integrated semiconductor manufacturing is to address the early breakdown failure mode observed with voltage ramp (Vramp) testing. Understanding the early failure mechanism is important in order to improve the process condition before subjecting the device to Time-Dependent-Dielectric Breakdown (TDDB) stress as the ultimate test. In this paper, we investigated the defect density performance across a design of experiment on the related process condition and collected Vramp test on a vast sample size of 34,000 sites per split to obtain a statistically significant electrical response. We addressed two early failure mechanisms and showed improvements in those with improved processing conditions for MIM capacitor with 1fF/um2 capacitance density. This MIM capacitor was embedded within the fabrication of the dual damascene copper interconnect process.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122334001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792506
Seunguk Cha, Matteo Rossi, B. Koo, Kwanghyun Jin, V. Jain
We used a wireless temperature measurement wafer to determine actual wafer temperatures under real production process conditions. We compared the temperature profile during baking and cooling stages between two photoresist track tools and discovered significant differences in the cooling phase affecting the structural properties of the deposited film. These film variations were found to impact the downstream etch process giving rise to a larger number of defects related to Critical Dimension (CD) variation in one of the tools.
{"title":"Using a Wireless Temperature Measurement Wafer to Analyze the Cause of Critical Dimension Differences between Tools","authors":"Seunguk Cha, Matteo Rossi, B. Koo, Kwanghyun Jin, V. Jain","doi":"10.1109/asmc54647.2022.9792506","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792506","url":null,"abstract":"We used a wireless temperature measurement wafer to determine actual wafer temperatures under real production process conditions. We compared the temperature profile during baking and cooling stages between two photoresist track tools and discovered significant differences in the cooling phase affecting the structural properties of the deposited film. These film variations were found to impact the downstream etch process giving rise to a larger number of defects related to Critical Dimension (CD) variation in one of the tools.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116228565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792483
Jeff J. Ye, John Lee, Michael W. Davis
Frequent center injector shading issue at the DRAM bitline integrated dry etch step has affected chamber availability, yield and quality of the products in various applications for customers. In this paper, we presented an innovative method of applying a combination of a continuous plasma process (CPP) and an optimized waferless chamber clean (WCC) to eliminate center injector shading of wafers caused by etch by-product build-up in the inner wall of the gas injector.
{"title":"Continuous plasma etch process with waferless chamber clean optimization for defect reduction by eliminating center injector shading","authors":"Jeff J. Ye, John Lee, Michael W. Davis","doi":"10.1109/asmc54647.2022.9792483","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792483","url":null,"abstract":"Frequent center injector shading issue at the DRAM bitline integrated dry etch step has affected chamber availability, yield and quality of the products in various applications for customers. In this paper, we presented an innovative method of applying a combination of a continuous plasma process (CPP) and an optimized waferless chamber clean (WCC) to eliminate center injector shading of wafers caused by etch by-product build-up in the inner wall of the gas injector.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122208723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792499
T. N. Tran Thi Caliste, L. Kirste, A. Drouin, J. Baruchel
An advanced X-ray Bragg diffraction imaging technique known as Rocking Curve Imaging (RCI) was implemented and developed at the European Synchrotron Radiation Facility (ESRF) for the characterization of defects in bulk crystals and crystalline layers. We describe the technical aspects of RCI and show, as examples, results of its application to the observation of the long-range distortion field between parallel dislocations with opposite Burgers vectors that are often present in SiC, and the growth defects in ammonothermally grown GaN crystals. RCI allows obtaining unique results because of its sub-μm spatial resolution and its μradian range angular resolution.
{"title":"An advanced Bragg diffraction imaging technique to characterize defects in SiC and GaN : Topic/category, e.g. AM: Advanced Metrology","authors":"T. N. Tran Thi Caliste, L. Kirste, A. Drouin, J. Baruchel","doi":"10.1109/asmc54647.2022.9792499","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792499","url":null,"abstract":"An advanced X-ray Bragg diffraction imaging technique known as Rocking Curve Imaging (RCI) was implemented and developed at the European Synchrotron Radiation Facility (ESRF) for the characterization of defects in bulk crystals and crystalline layers. We describe the technical aspects of RCI and show, as examples, results of its application to the observation of the long-range distortion field between parallel dislocations with opposite Burgers vectors that are often present in SiC, and the growth defects in ammonothermally grown GaN crystals. RCI allows obtaining unique results because of its sub-μm spatial resolution and its μradian range angular resolution.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134107467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-02DOI: 10.1109/asmc54647.2022.9792518
Balazs Bordas, Kutup Kurt, A. Bamberg, S. Engell
The application performance of polymers is heavily influenced by their molecular weight distribution. As the dynamic modeling of the MWD in polymerization reactions is difficult based on first principles, a semi-physical or grey-box modeling approach is proposed for step-growth polymerization processes, utilizing molecular weight distribution measurement data. The method is tested on data from an industrial polymerization reactor.
{"title":"Developing a digital twin of a polymerization reaction for process optimization","authors":"Balazs Bordas, Kutup Kurt, A. Bamberg, S. Engell","doi":"10.1109/asmc54647.2022.9792518","DOIUrl":"https://doi.org/10.1109/asmc54647.2022.9792518","url":null,"abstract":"The application performance of polymers is heavily influenced by their molecular weight distribution. As the dynamic modeling of the MWD in polymerization reactions is difficult based on first principles, a semi-physical or grey-box modeling approach is proposed for step-growth polymerization processes, utilizing molecular weight distribution measurement data. The method is tested on data from an industrial polymerization reactor.","PeriodicalId":436890,"journal":{"name":"2022 33rd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123822959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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