Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951394
K. Lasanen, E. Raisanen-Ruotsalainen, J. Kostamovaara
In this paper, a low-power CMOS operational amplifier for biomedical instrumentation operating with a 1-V supply is described. Large input common-mode range (CMR) is achieved utilizing bulk-driven PMOS-transistors as an input differential pair of the opamp. The opamp was fabricated in a 0.35 /spl mu/m n-well double-poly CMOS process with threshold voltages of 0.5 V and 0.65 V. The open-loop gain (A/sub 0/) of the amplifier is 70 dB, the gain-bandwidth product (GBW) is 190 kHz and the phase margin (PM) is 60/spl deg/ with a 7 pF load. The power consumption of the opamp is 5 /spl mu/W.
{"title":"A 1-V 5 /spl mu/W CMOS-opamp with bulk-driven input transistors","authors":"K. Lasanen, E. Raisanen-Ruotsalainen, J. Kostamovaara","doi":"10.1109/MWSCAS.2000.951394","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951394","url":null,"abstract":"In this paper, a low-power CMOS operational amplifier for biomedical instrumentation operating with a 1-V supply is described. Large input common-mode range (CMR) is achieved utilizing bulk-driven PMOS-transistors as an input differential pair of the opamp. The opamp was fabricated in a 0.35 /spl mu/m n-well double-poly CMOS process with threshold voltages of 0.5 V and 0.65 V. The open-loop gain (A/sub 0/) of the amplifier is 70 dB, the gain-bandwidth product (GBW) is 190 kHz and the phase margin (PM) is 60/spl deg/ with a 7 pF load. The power consumption of the opamp is 5 /spl mu/W.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"640 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116085875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951574
S. Chowdhury, M. Zoltowski, J. S. Goldstein
The chip-level MMSE estimate of the (multi-user) synchronous sum signal transmitted by the base-station, followed by a correlate and sum, has been shown to perform very well in the CDMA forward link using orthogonal channel codes. In this paper, adaptive reduced-rank, chip-level MMSE estimation based on the Multi-Stage Nested Wiener Filter (MSNWF) is presented. Our simulations show that, adaptive MSNWF operating in a very low rank subspace and using the pilot channel for training can achieve near full-rank performance at a fast convergence speed.
{"title":"Reduced-rank adaptive MMSE equalization for the forward link in high-speed CDMA","authors":"S. Chowdhury, M. Zoltowski, J. S. Goldstein","doi":"10.1109/MWSCAS.2000.951574","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951574","url":null,"abstract":"The chip-level MMSE estimate of the (multi-user) synchronous sum signal transmitted by the base-station, followed by a correlate and sum, has been shown to perform very well in the CDMA forward link using orthogonal channel codes. In this paper, adaptive reduced-rank, chip-level MMSE estimation based on the Multi-Stage Nested Wiener Filter (MSNWF) is presented. Our simulations show that, adaptive MSNWF operating in a very low rank subspace and using the pilot channel for training can achieve near full-rank performance at a fast convergence speed.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116653700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952838
Lingling Fan, A. Feliachi
This paper presents a methodology for decentralized stabilization of a multimachine nonlinear electric power system through the excitation systems. To handle the nonlinearities, feedback linearization techniques are used. To achieve decoupling of subsystem models, the interface variables are estimated from available local measurements. Robust control design techniques are then applied to account for measurement noise. A nine-bus, three-machine, power system is used to illustrate the proposed method.
{"title":"Decentralized stabilization of nonlinear electric power systems using local measurements and feedback linearization","authors":"Lingling Fan, A. Feliachi","doi":"10.1109/MWSCAS.2000.952838","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952838","url":null,"abstract":"This paper presents a methodology for decentralized stabilization of a multimachine nonlinear electric power system through the excitation systems. To handle the nonlinearities, feedback linearization techniques are used. To achieve decoupling of subsystem models, the interface variables are estimated from available local measurements. Robust control design techniques are then applied to account for measurement noise. A nine-bus, three-machine, power system is used to illustrate the proposed method.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114293060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951591
K. Baek, Ki-Wook Kim, S. Kang
In this paper, we propose a novel bus encoding scheme called LESS (Low Energy Set Scheme) to minimize the coupling effects which cause significant delay and power consumption in the on-chip interconnect. Our experimental results indicate that the proposed encoding technique saves the interconnect power-delay product up to 15% and energy-delay product up to 31% for independent 8-bit data stream. Because LESS uses a slim encoding structure, area, delay, and power penalties due to additional coding circuitry are negligible compared to benefits.
{"title":"A low energy encoding technique for reduction of coupling effects in SoC interconnects","authors":"K. Baek, Ki-Wook Kim, S. Kang","doi":"10.1109/MWSCAS.2000.951591","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951591","url":null,"abstract":"In this paper, we propose a novel bus encoding scheme called LESS (Low Energy Set Scheme) to minimize the coupling effects which cause significant delay and power consumption in the on-chip interconnect. Our experimental results indicate that the proposed encoding technique saves the interconnect power-delay product up to 15% and energy-delay product up to 31% for independent 8-bit data stream. Because LESS uses a slim encoding structure, area, delay, and power penalties due to additional coding circuitry are negligible compared to benefits.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122438922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951580
J.P. Mima, B. Huang, J. Johnson, G. Branner
This paper presents the steps leading to development of a highly accurate PHEMT circuit model primarily for accurate prediction of DC, small and large signal microwave performance. This model characterizes the fundamental and higher order harmonic performance over a broad range of input power with a high degree of accuracy.
{"title":"High precision large signal modeling of microwave PHEMT transistors","authors":"J.P. Mima, B. Huang, J. Johnson, G. Branner","doi":"10.1109/MWSCAS.2000.951580","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951580","url":null,"abstract":"This paper presents the steps leading to development of a highly accurate PHEMT circuit model primarily for accurate prediction of DC, small and large signal microwave performance. This model characterizes the fundamental and higher order harmonic performance over a broad range of input power with a high degree of accuracy.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123000742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951416
P. B. Wu, R. Mack, R. Massara
A quantitative benchmarking metric is presented for the objective evaluation of the quality of analog layout. It facilitates comparisons between alternative design automation tools, and, for a given tool, provides the assessment of each layout instance. The quality metric reflects two principal concerns in layout design: area efficiency and net-routing optimality. The results demonstrate the effectiveness of the metric in that the calculated scores provide a characterization that corresponds to expert designers' judgements.
{"title":"A quantitative method for evaluating the quality of analog layout","authors":"P. B. Wu, R. Mack, R. Massara","doi":"10.1109/MWSCAS.2000.951416","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951416","url":null,"abstract":"A quantitative benchmarking metric is presented for the objective evaluation of the quality of analog layout. It facilitates comparisons between alternative design automation tools, and, for a given tool, provides the assessment of each layout instance. The quality metric reflects two principal concerns in layout design: area efficiency and net-routing optimality. The results demonstrate the effectiveness of the metric in that the calculated scores provide a characterization that corresponds to expert designers' judgements.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131255873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951619
S.R. Das, M. Sudarma, J. Liang, E. Petriu, M. Assaf, W. Jone
It was recently suggested by Jone and Das that given a multiple-output combinational circuit, a parity bit signature for exhaustive testing of VLSI circuits can be generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. Based on the aforesaid concepts of Jone and Das, this paper proposes a multiple-output parity bit signature for built-in self-testing of VLSI circuits using nonexhaustive or compact test sets. The feasibility of the developed approach is demonstrated by extensive simulation experiments on ISCAS 85 combinational benchmark circuits using simulation programs FSIM, ATALANTA, and COMPACTEST, showing a high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead.
{"title":"Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with compact test sets","authors":"S.R. Das, M. Sudarma, J. Liang, E. Petriu, M. Assaf, W. Jone","doi":"10.1109/MWSCAS.2000.951619","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951619","url":null,"abstract":"It was recently suggested by Jone and Das that given a multiple-output combinational circuit, a parity bit signature for exhaustive testing of VLSI circuits can be generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. Based on the aforesaid concepts of Jone and Das, this paper proposes a multiple-output parity bit signature for built-in self-testing of VLSI circuits using nonexhaustive or compact test sets. The feasibility of the developed approach is demonstrated by extensive simulation experiments on ISCAS 85 combinational benchmark circuits using simulation programs FSIM, ATALANTA, and COMPACTEST, showing a high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127680962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951472
I. Filanovsky
Describes synthesis of a network to have the step response close to a rectangular shape pulse. The derivative of this step response is described by positive and delayed negative semi-periods of sine-squared function. The real and imaginary parts of the Laplace transform of this derivative are expanded in infinite products. Then, using a finite amount of terms in these products one can obtain the transfer function realizable as a reactance network loaded by a resistor.
{"title":"Synthesis of a reactance network having the step response close to a rectangular shape pulse","authors":"I. Filanovsky","doi":"10.1109/MWSCAS.2000.951472","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951472","url":null,"abstract":"Describes synthesis of a network to have the step response close to a rectangular shape pulse. The derivative of this step response is described by positive and delayed negative semi-periods of sine-squared function. The real and imaginary parts of the Laplace transform of this derivative are expanded in infinite products. Then, using a finite amount of terms in these products one can obtain the transfer function realizable as a reactance network loaded by a resistor.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128083684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951421
P. Lowenborg, H. Johansson, L. Wanhammar
This paper introduces hybrid analog/digital filter banks with alias-free subbands. The aliasing at the output is small due to stopband attenuation of the individual filters and not due to cancellation, which is the case in maximally decimated filter banks. Thus, the accuracy requirements of the analog filter components are relaxed.
{"title":"Two-channel hybrid analog/digital filter banks with alias-free subbands","authors":"P. Lowenborg, H. Johansson, L. Wanhammar","doi":"10.1109/MWSCAS.2000.951421","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951421","url":null,"abstract":"This paper introduces hybrid analog/digital filter banks with alias-free subbands. The aliasing at the output is small due to stopband attenuation of the individual filters and not due to cancellation, which is the case in maximally decimated filter banks. Thus, the accuracy requirements of the analog filter components are relaxed.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132555590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951605
S. Papadopoulos, R. Mack, R. Massara
An approach is presented for the automated sizing of analog circuits based upon a combination of a genetic algorithm (GA) with a least squares (Gauss-Newton) gradient search. The method combines the global-search properties of the GA with the fast local convergence properties of the least squares method to produce a circuit design from random initial component values in a reduced time compared to the application of a direct GA method, or a restart least squares algorithm. Results are presented to demonstrate the application of the method in the design of both passive and active circuits.
{"title":"A hybrid genetic algorithm method for optimizing analog circuits","authors":"S. Papadopoulos, R. Mack, R. Massara","doi":"10.1109/MWSCAS.2000.951605","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951605","url":null,"abstract":"An approach is presented for the automated sizing of analog circuits based upon a combination of a genetic algorithm (GA) with a least squares (Gauss-Newton) gradient search. The method combines the global-search properties of the GA with the fast local convergence properties of the least squares method to produce a circuit design from random initial component values in a reduced time compared to the application of a direct GA method, or a restart least squares algorithm. Results are presented to demonstrate the application of the method in the design of both passive and active circuits.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132577301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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