Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951397
B. Minch
The author presents a folded floating-gate MOS (FGMOS) differential pair circuit that is capable of simultaneously providing a rail-to-rail common-mode input voltage range and a rail-to-rail output voltage swing with a low power-supply voltage. In this configuration, the voltage drop across the bias current source is folded up into the same range over which the output voltages swing, facilitating low-voltage operation. The floating-gate charge can be used to trim out the offset voltage of the differential pair and to reduce the required power-supply voltage for a given bias current level. The author provides both a qualitative description of how the circuit works and a quantitative incremental high-frequency analysis of the differential-mode and common-mode transconductance gains and common-mode rejection ratio of the circuit. He also shows experimental measurements from a prototype circuit that was fabricated in a 1.2 /spl mu/m double-poly CMOS process.
{"title":"Evolution of a folded floating-gate differential pair","authors":"B. Minch","doi":"10.1109/MWSCAS.2000.951397","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951397","url":null,"abstract":"The author presents a folded floating-gate MOS (FGMOS) differential pair circuit that is capable of simultaneously providing a rail-to-rail common-mode input voltage range and a rail-to-rail output voltage swing with a low power-supply voltage. In this configuration, the voltage drop across the bias current source is folded up into the same range over which the output voltages swing, facilitating low-voltage operation. The floating-gate charge can be used to trim out the offset voltage of the differential pair and to reduce the required power-supply voltage for a given bias current level. The author provides both a qualitative description of how the circuit works and a quantitative incremental high-frequency analysis of the differential-mode and common-mode transconductance gains and common-mode rejection ratio of the circuit. He also shows experimental measurements from a prototype circuit that was fabricated in a 1.2 /spl mu/m double-poly CMOS process.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127708910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951430
M. Sarcinelli-Filho, F. Mota
The problem of suppressing zero-input limit cycles in coupled-form state-space digital filters when the quantization is performed after the multiplication is addressed. To the extent of the authors' knowledge, no proof has been presented that the parasitic oscillations are suppressed for poles anywhere in the unit circle, under that condition. Some authors have addressed this subject, but their results constrain the poles to a bounded region inside the unit circle. With the objective of exploring this topic further, the authors present a proof that for poles whose angle is either 0, /spl plusmn/45, /spl plusmn/90, /spl plusmn/135 or 180 degrees and whose radius is lower than one, the second-order state-space coupled-form digital filter is free of zero-input limit cycles when quantizers placed just after the multipliers implement magnitude truncation.
{"title":"On the stability of coupled-form state-space digital filters with quantization before summation","authors":"M. Sarcinelli-Filho, F. Mota","doi":"10.1109/MWSCAS.2000.951430","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951430","url":null,"abstract":"The problem of suppressing zero-input limit cycles in coupled-form state-space digital filters when the quantization is performed after the multiplication is addressed. To the extent of the authors' knowledge, no proof has been presented that the parasitic oscillations are suppressed for poles anywhere in the unit circle, under that condition. Some authors have addressed this subject, but their results constrain the poles to a bounded region inside the unit circle. With the objective of exploring this topic further, the authors present a proof that for poles whose angle is either 0, /spl plusmn/45, /spl plusmn/90, /spl plusmn/135 or 180 degrees and whose radius is lower than one, the second-order state-space coupled-form digital filter is free of zero-input limit cycles when quantizers placed just after the multipliers implement magnitude truncation.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"141 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129191202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951694
Roman Genov, Gert Cauwenberghs
An internally analog, externally digital architecture for matrix-vector multiplication is presented. Fully parallel processing allows for high data throughput and minimal latency. The analog architecture incorporates an array of charge-mode analog computational cells with dynamic storage and row-parallel flash analog-to-digital converters (ADC). Each of the cells includes a dynamic storage element and a charge injection device computing binary inner product of two arguments. The matrix elements are stored in the array of computational cells in bit-parallel fashion, and the input vector is presented bit-serially. Digital post-processing is then performed on the ADC outputs to construct the resulting product with precision higher than that of each conversion. The analog architecture is tailored for high-density and low power VLSI implementation, and matrix dimensions of 128/spl times/512 and ADC resolution of 6 bits for an overall resolution in excess of 8 bits are feasible on a 3 mm/spl times/3 mm chip in standard CMOS 0.5 /spl mu/m technology.
{"title":"Charge-mode parallel architecture for matrix-vector multiplication","authors":"Roman Genov, Gert Cauwenberghs","doi":"10.1109/MWSCAS.2000.951694","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951694","url":null,"abstract":"An internally analog, externally digital architecture for matrix-vector multiplication is presented. Fully parallel processing allows for high data throughput and minimal latency. The analog architecture incorporates an array of charge-mode analog computational cells with dynamic storage and row-parallel flash analog-to-digital converters (ADC). Each of the cells includes a dynamic storage element and a charge injection device computing binary inner product of two arguments. The matrix elements are stored in the array of computational cells in bit-parallel fashion, and the input vector is presented bit-serially. Digital post-processing is then performed on the ADC outputs to construct the resulting product with precision higher than that of each conversion. The analog architecture is tailored for high-density and low power VLSI implementation, and matrix dimensions of 128/spl times/512 and ADC resolution of 6 bits for an overall resolution in excess of 8 bits are feasible on a 3 mm/spl times/3 mm chip in standard CMOS 0.5 /spl mu/m technology.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116359777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951626
A. Salian, H. Kulah, N. Yazdi, G. He, K. Najafi
This paper presents a hybrid microaccelerometer subsystem consisting of an all-silicon /spl mu/g capacitive microaccelerometer and a low noise CMOS capacitive interface circuit. This accelerometer has a measured sensitivity of 1.4pF/g for a device with 2mm /spl times/ 1mm proof mass and 1.4/spl mu/m air gap. The calculated mechanical noise floor for the device is 0.39/spl mu/g/vHz in atmosphere. The circuit has a 95dB dynamic range; a low offset of 370/spl mu/V and can resolve better than 75aF. The overall sensitivity of the complete module is measured as 160mV/g with a noise floor of 3.6/spl mu/V/vHz (-110dBV/vHz), indicating that the current system is capable of resolving about 20/spl mu/g/vHz.
{"title":"Hybrid silicon microaccelerometer system with CMOS interface circuit","authors":"A. Salian, H. Kulah, N. Yazdi, G. He, K. Najafi","doi":"10.1109/MWSCAS.2000.951626","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951626","url":null,"abstract":"This paper presents a hybrid microaccelerometer subsystem consisting of an all-silicon /spl mu/g capacitive microaccelerometer and a low noise CMOS capacitive interface circuit. This accelerometer has a measured sensitivity of 1.4pF/g for a device with 2mm /spl times/ 1mm proof mass and 1.4/spl mu/m air gap. The calculated mechanical noise floor for the device is 0.39/spl mu/g/vHz in atmosphere. The circuit has a 95dB dynamic range; a low offset of 370/spl mu/V and can resolve better than 75aF. The overall sensitivity of the complete module is measured as 160mV/g with a noise floor of 3.6/spl mu/V/vHz (-110dBV/vHz), indicating that the current system is capable of resolving about 20/spl mu/g/vHz.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117083931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952926
Jyh-Neng Yang, Chen-Yi Lee, Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang
A 2.4 GHz low noise amplifier has been designed in a standard CMOS 0.35 um process. The transistor model is Bsim3 for 0.35 um process. The amplifier provides a forward gain of 33 dB with a noise figure only 0.92 dB while drawing 17 mw from a 1.5 V supply. Design simulation results are presented in this paper.
{"title":"A 1.5-V, 2.4GHz CMOS low-noise amplifier","authors":"Jyh-Neng Yang, Chen-Yi Lee, Terng-Yin Hsu, Terng-Ren Hsu, Chung-Cheng Wang","doi":"10.1109/MWSCAS.2000.952926","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952926","url":null,"abstract":"A 2.4 GHz low noise amplifier has been designed in a standard CMOS 0.35 um process. The transistor model is Bsim3 for 0.35 um process. The amplifier provides a forward gain of 33 dB with a noise figure only 0.92 dB while drawing 17 mw from a 1.5 V supply. Design simulation results are presented in this paper.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116706821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951667
A. Amira, A. Bouridane, P. Milligan, P. Sage
This paper presents a novel architecture for a matrix-matrix multiplication algorithm. The paper describes the mathematical model for the algorithm (based on Baugh-Wooley algorithm), the associated design and implementation of the algorithm on a Xilinx FPGA board, and discusses the efficiency of the implementation requiring (N/sup 2/) and O(2nN) as area and time complexities respectively, where N is the matrix size and n is the word length.
{"title":"A high throughput FPGA implementation of a bit-level matrix-matrix product","authors":"A. Amira, A. Bouridane, P. Milligan, P. Sage","doi":"10.1109/MWSCAS.2000.951667","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951667","url":null,"abstract":"This paper presents a novel architecture for a matrix-matrix multiplication algorithm. The paper describes the mathematical model for the algorithm (based on Baugh-Wooley algorithm), the associated design and implementation of the algorithm on a Xilinx FPGA board, and discusses the efficiency of the implementation requiring (N/sup 2/) and O(2nN) as area and time complexities respectively, where N is the matrix size and n is the word length.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116753117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951647
R. A. Rafla, M. El-Gamal
Three 2-3 V-supply LNA's were designed in 0.35 /spl mu/m and 0.25 /spl mu/m digital CMOS processes, for center frequencies of 2.4, 3, and 5.8 GHz. The circuits' components are fully-integrated making them suitable for integration into a complete transceiver. The measured forward transmissions S21 for the 2.4 and 3 GHz LNA's are 6.5 and 8 dB respectively, at relatively low power consumption of 20 mW, when excluding the output stages. The noise figures achieved are 2.5 and 3 dB respectively. Simulation of the 5.8 GHz LNA yielded 10 dB of forward gain and 3 dB of noise figure, at 20 mW of power consumption.
{"title":"2.4-5.8 GHz CMOS LNA's using integrated inductors","authors":"R. A. Rafla, M. El-Gamal","doi":"10.1109/MWSCAS.2000.951647","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951647","url":null,"abstract":"Three 2-3 V-supply LNA's were designed in 0.35 /spl mu/m and 0.25 /spl mu/m digital CMOS processes, for center frequencies of 2.4, 3, and 5.8 GHz. The circuits' components are fully-integrated making them suitable for integration into a complete transceiver. The measured forward transmissions S21 for the 2.4 and 3 GHz LNA's are 6.5 and 8 dB respectively, at relatively low power consumption of 20 mW, when excluding the output stages. The noise figures achieved are 2.5 and 3 dB respectively. Simulation of the 5.8 GHz LNA yielded 10 dB of forward gain and 3 dB of noise figure, at 20 mW of power consumption.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115640730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952881
Samuel M. Palermo, JosC Pineda de Gyve2
A phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. Implemented in 1.4 /spl mu/m CMOS, the PLL has a 111-290 MHz range, phase noise of -92.3 dBc/Hz at a 50 kHz offset, and dissipates 9 mW from a 2.7 V supply.
{"title":"A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO","authors":"Samuel M. Palermo, JosC Pineda de Gyve2","doi":"10.1109/MWSCAS.2000.952881","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952881","url":null,"abstract":"A phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. Implemented in 1.4 /spl mu/m CMOS, the PLL has a 111-290 MHz range, phase noise of -92.3 dBc/Hz at a 50 kHz offset, and dissipates 9 mW from a 2.7 V supply.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114208618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952835
D. Rerkpreedapong, A. Feliachi
This paper applies feedback linearization to control a multimachine nonlinear electric power system thru the excitation and governor subsystems. The rotor angles are estimated in real-time from local measurement to achieve decoupling. The nonlinear decentralized controller effectively regulates the terminal voltage and also stabilizes the power system when a fault is applied. Two test systems are used to illustrate the proposed method: one-machine-infinite-bus and nine-bus three-machine power systems.
{"title":"Decentralized control of nonlinear electric power systems thru excitation and governor systems using local measurements and feedback linearization","authors":"D. Rerkpreedapong, A. Feliachi","doi":"10.1109/MWSCAS.2000.952835","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952835","url":null,"abstract":"This paper applies feedback linearization to control a multimachine nonlinear electric power system thru the excitation and governor subsystems. The rotor angles are estimated in real-time from local measurement to achieve decoupling. The nonlinear decentralized controller effectively regulates the terminal voltage and also stabilizes the power system when a fault is applied. Two test systems are used to illustrate the proposed method: one-machine-infinite-bus and nine-bus three-machine power systems.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114436217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951407
Yiwei Wang, J. Doherty, R.E. Van Dyck
During recent years, digital watermarking has drawn a lot of attention as a means to protect the copyright of image data. Numerous algorithms have been proposed in different domains. Particularly, a set of these algorithms embed the watermark information in the amplitudes of the discrete Fourier transform (DFT) coefficients. However, studies have shown that the image can be reconstructed by using only the DFT phase information. It is a common belief that watermarking algorithms can be improved by evaluating possible attacking methods and modifying the algorithms accordingly. We propose an algorithm to attack the watermarks embedded in DFT amplitudes. The proposed attacking algorithm uses projection onto convex sets (POCS). The results show that it may be necessary to embed the watermark information in both amplitudes and phases of the DFT coefficients.
{"title":"A POCS-based algorithm to attack image watermarks embedded in DFT amplitudes","authors":"Yiwei Wang, J. Doherty, R.E. Van Dyck","doi":"10.1109/MWSCAS.2000.951407","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951407","url":null,"abstract":"During recent years, digital watermarking has drawn a lot of attention as a means to protect the copyright of image data. Numerous algorithms have been proposed in different domains. Particularly, a set of these algorithms embed the watermark information in the amplitudes of the discrete Fourier transform (DFT) coefficients. However, studies have shown that the image can be reconstructed by using only the DFT phase information. It is a common belief that watermarking algorithms can be improved by evaluating possible attacking methods and modifying the algorithms accordingly. We propose an algorithm to attack the watermarks embedded in DFT amplitudes. The proposed attacking algorithm uses projection onto convex sets (POCS). The results show that it may be necessary to embed the watermark information in both amplitudes and phases of the DFT coefficients.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114868450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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