Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952910
Y. Fouzar, M. Sawan, Y. Savaria
Presents a fully integrated CMOS fast phase locked loop (PLL), based on a new wide swing differential voltage controlled oscillator (WSDVCO). The proposed PLL incorporates new simple architecture of well known PLL building blocks (a dynamic phase-frequency detector, a charge pump, an on-chip low-pass filter, a WSDVCO and a frequency divider). The present version of the WSDVCO allows one to obtain wide tuning range of 40 to 730 MHz simulated with Spectre simulator using 0.25 /spl mu/m CMOS technology. The simplicity of the proposed PLL building blocks permits one to design high performance PLL.
{"title":"CMOS wide-swing differential VCO for fully integrated fast PLL","authors":"Y. Fouzar, M. Sawan, Y. Savaria","doi":"10.1109/MWSCAS.2000.952910","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952910","url":null,"abstract":"Presents a fully integrated CMOS fast phase locked loop (PLL), based on a new wide swing differential voltage controlled oscillator (WSDVCO). The proposed PLL incorporates new simple architecture of well known PLL building blocks (a dynamic phase-frequency detector, a charge pump, an on-chip low-pass filter, a WSDVCO and a frequency divider). The present version of the WSDVCO allows one to obtain wide tuning range of 40 to 730 MHz simulated with Spectre simulator using 0.25 /spl mu/m CMOS technology. The simplicity of the proposed PLL building blocks permits one to design high performance PLL.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952913
H. M. Hamed, M. Zaghloul
Frequency shift keying (FSK) finds application in low frequency transmission over band limited audio frequency channels, such as calling number identification, a service currently provided by telephone service providers. The conventional approaches to FSK demodulation work well when the transmitted frequencies are significantly higher than the baud rate. However, when the baud rate is comparable to the transmission frequencies, they become costly to implement. This paper describes a mixed signal approach to FSK demodulation suitable in particular to the decoding of this type of signal, based on a finite state machine (FSM). The proposed circuit consists of an analog interface followed by a threshold device, which is itself followed by the FSM.
{"title":"Mixed signal decoder for audio frequency FSK applications with transmission rate comparable to the carrier frequencies","authors":"H. M. Hamed, M. Zaghloul","doi":"10.1109/MWSCAS.2000.952913","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952913","url":null,"abstract":"Frequency shift keying (FSK) finds application in low frequency transmission over band limited audio frequency channels, such as calling number identification, a service currently provided by telephone service providers. The conventional approaches to FSK demodulation work well when the transmitted frequencies are significantly higher than the baud rate. However, when the baud rate is comparable to the transmission frequencies, they become costly to implement. This paper describes a mixed signal approach to FSK demodulation suitable in particular to the decoding of this type of signal, based on a finite state machine (FSM). The proposed circuit consists of an analog interface followed by a threshold device, which is itself followed by the FSM.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124085056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951457
R. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, E. Friedman
The placement of substrate contacts in epi and non-epi technologies in order to control and reduce the substrate noise amplitude and spreading is analyzed. The choice of small or large substrate contacts or rings for each of the two major technologies are highlighted. Design guidelines for placing substrate contacts particularly appropriate to improving the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.
{"title":"Placement of substrate contacts to alleviate substrate noise in epi and non-epi technologies","authors":"R. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, E. Friedman","doi":"10.1109/MWSCAS.2000.951457","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951457","url":null,"abstract":"The placement of substrate contacts in epi and non-epi technologies in order to control and reduce the substrate noise amplitude and spreading is analyzed. The choice of small or large substrate contacts or rings for each of the two major technologies are highlighted. Design guidelines for placing substrate contacts particularly appropriate to improving the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128411518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951412
S. Hagopian, G. Erten
A programmable convolution array (PCA) architecture is described. The architecture uses CMOS light sensors, each connected to an amplifier. The aggregate of amplifiers yields a sum of products and computes convolution of the image with kernels of arbitrary size. A chip based on this architecture and test results are presented.
{"title":"Programmable convolution array (PCA) chip for arbitrary image transforms on the sensory plane","authors":"S. Hagopian, G. Erten","doi":"10.1109/MWSCAS.2000.951412","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951412","url":null,"abstract":"A programmable convolution array (PCA) architecture is described. The architecture uses CMOS light sensors, each connected to an amplifier. The aggregate of amplifiers yields a sum of products and computes convolution of the image with kernels of arbitrary size. A chip based on this architecture and test results are presented.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128560235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952895
Fan Xu, A. Willson
We propose a pipelined DPASTd algorithm for signal subspace tracking. Our algorithm allows the computations of multiple eigenvectors to be fully pipelined. Two novel systolic implementations of the algorithm are studied and a method for reciprocal computation is discussed. We also present simulation results to validate the algorithm.
{"title":"Novel systolic architectures for signal subspace tracking","authors":"Fan Xu, A. Willson","doi":"10.1109/MWSCAS.2000.952895","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952895","url":null,"abstract":"We propose a pipelined DPASTd algorithm for signal subspace tracking. Our algorithm allows the computations of multiple eigenvectors to be fully pipelined. Two novel systolic implementations of the algorithm are studied and a method for reciprocal computation is discussed. We also present simulation results to validate the algorithm.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129061924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951668
Hui Liu, X. Du, M. Hassoun
The design and implementation of the components of a non-radix 2 12-bit pipeline analog-to-digital converter (ADC) is presented in this paper. The ADC is composed of 13 pipeline stages each with a gain of 1.9 rather than the traditional 2. Each stage of the pipeline is composed of a fully differential sample and hold amplifier (SHA), a 1-bit sub-ADC and a 1-bit sub-DAC. The sub-DAC functionality is rolled in as part of the SHA switched-capacitor circuit, which is referred to as the multiplying DAC (MDAC). The ADC has been implemented in a 0.35 /spl mu/m single-poly CMOS digital process.
{"title":"Components of a 12-bit 50 Ms/s non-radix 2 pipeline analog-to-digital converter","authors":"Hui Liu, X. Du, M. Hassoun","doi":"10.1109/MWSCAS.2000.951668","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951668","url":null,"abstract":"The design and implementation of the components of a non-radix 2 12-bit pipeline analog-to-digital converter (ADC) is presented in this paper. The ADC is composed of 13 pipeline stages each with a gain of 1.9 rather than the traditional 2. Each stage of the pipeline is composed of a fully differential sample and hold amplifier (SHA), a 1-bit sub-ADC and a 1-bit sub-DAC. The sub-DAC functionality is rolled in as part of the SHA switched-capacitor circuit, which is referred to as the multiplying DAC (MDAC). The ADC has been implemented in a 0.35 /spl mu/m single-poly CMOS digital process.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128869172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951393
Y. Yu, S. Choi, Dong-Yong Kim, KyuTae Park, H. Ahn
Proposes two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistors 1 and 2 employ a p-type folded composite transistor and an electronic Zener diode in order to decrease the threshold voltage, respectively. The simulation has been carried out using 0.25/spl mu/m n-well process with 2.5V supply voltage.
{"title":"Design of CMOS composite transistors with improved operating region","authors":"Y. Yu, S. Choi, Dong-Yong Kim, KyuTae Park, H. Ahn","doi":"10.1109/MWSCAS.2000.951393","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951393","url":null,"abstract":"Proposes two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistors 1 and 2 employ a p-type folded composite transistor and an electronic Zener diode in order to decrease the threshold voltage, respectively. The simulation has been carried out using 0.25/spl mu/m n-well process with 2.5V supply voltage.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128895078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952818
W.W. Wu
Highlights the challenges of information transmission by the combination of ATM (asynchronous transfer mode), Internet, and satellites. Specifically, the network and protocol incompatibility problems and the limitations of existing solutions are highlighted. For ATM, it is the ATM cell switching structure established by the ATM Forum and ITU; for Internet, it is the transmission protocols standardized by the IETF (Internet Engineering Task Force); for satellites, it is the ITU-RR endorsed Intelsat SSOG and the IMT-2000. Potential solutions are briefly discussed. Quality of multimedia services (QoMS) issues are addressed. These issues are in terms of efficiency enhancement, transmission delay reduction, avoidance of message traffic congestion, and reliability improvement. Proposed solutions are in compliance with standardized protocol arrangements. One of the solutions is shown to have the domino effect of maximum QoMS impact with minimum effort.
{"title":"Move information with ATM, Internet, and satellites","authors":"W.W. Wu","doi":"10.1109/MWSCAS.2000.952818","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952818","url":null,"abstract":"Highlights the challenges of information transmission by the combination of ATM (asynchronous transfer mode), Internet, and satellites. Specifically, the network and protocol incompatibility problems and the limitations of existing solutions are highlighted. For ATM, it is the ATM cell switching structure established by the ATM Forum and ITU; for Internet, it is the transmission protocols standardized by the IETF (Internet Engineering Task Force); for satellites, it is the ITU-RR endorsed Intelsat SSOG and the IMT-2000. Potential solutions are briefly discussed. Quality of multimedia services (QoMS) issues are addressed. These issues are in terms of efficiency enhancement, transmission delay reduction, avoidance of message traffic congestion, and reliability improvement. Proposed solutions are in compliance with standardized protocol arrangements. One of the solutions is shown to have the domino effect of maximum QoMS impact with minimum effort.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130946753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951475
D.Y.-C. Huang, C. Hutchens, B. Offord, H. Marlin, R. Bates
A 128/spl times/128 real-time infrared (RTIR) CMOS scene generation IC is presented. The RTIR IC offers real-time dynamic thermal scene generation. This system is a mixed mode design, 9 bit accurate with 16 element analog scene information written and stored in the thermal pixel array. The presented design utilizes micro electromechanical systems (MEMS) in conjunction with the 1.2 /spl mu/m Supertex CMOS process to develop a low cost RTIR IC scene generator.
{"title":"A real time infrared array IC","authors":"D.Y.-C. Huang, C. Hutchens, B. Offord, H. Marlin, R. Bates","doi":"10.1109/MWSCAS.2000.951475","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951475","url":null,"abstract":"A 128/spl times/128 real-time infrared (RTIR) CMOS scene generation IC is presented. The RTIR IC offers real-time dynamic thermal scene generation. This system is a mixed mode design, 9 bit accurate with 16 element analog scene information written and stored in the thermal pixel array. The presented design utilizes micro electromechanical systems (MEMS) in conjunction with the 1.2 /spl mu/m Supertex CMOS process to develop a low cost RTIR IC scene generator.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122962539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951673
R. Uusikartano, J. Niittylahti
In this paper, a compact architecture of a digital frequency synthesizer for a 2.4 GHz fast frequency hopping radio modem is presented. The synthesizer is designed for generating 12-bit quadrature carrier signals from 50 to 90 MHz in 500 kHz steps. The phase-to-amplitude conversion is performed with a look-up table which is compressed by using the fact that only a limited set of discrete frequencies is needed. Simulation and synthesis results for a VHDL-implementation of the architecture are given. In addition, the proposed architecture is compared to a traditional look-up based direct digital frequency synthesizer with similar performance.
{"title":"A digital frequency synthesizer for a 2.4 GHz fast frequency hopping transceiver","authors":"R. Uusikartano, J. Niittylahti","doi":"10.1109/MWSCAS.2000.951673","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951673","url":null,"abstract":"In this paper, a compact architecture of a digital frequency synthesizer for a 2.4 GHz fast frequency hopping radio modem is presented. The synthesizer is designed for generating 12-bit quadrature carrier signals from 50 to 90 MHz in 500 kHz steps. The phase-to-amplitude conversion is performed with a look-up table which is compressed by using the fact that only a limited set of discrete frequencies is needed. Simulation and synthesis results for a VHDL-implementation of the architecture are given. In addition, the proposed architecture is compared to a traditional look-up based direct digital frequency synthesizer with similar performance.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122252798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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