Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951594
J. Biernacki, D. Czarkowski
An RF (radio frequency) dc-dc converter has been developed to demonstrate the possibility of using a flyback configuration at 63 MHz. The converter consists of two sections: a variable pulse width generator (PWG) and a FET switch with a transformer and a detector. The bulk of the design was concentrated on improving the efficiency of the switch, the transformer and the detector. Low capacitances of the heterostructure AlGaAs/GaAs FET (HFET), a low leakage inductance of the RF transformer, a fast Schottky diode, multilayer ceramic chip capacitors and surface mount chip resistors made it possible to achieve high efficiencies from 20 MHz to 63 MHz. The "hard switching" 1-Watt converter achieves 60 to 70 percent efficiency, while operating with a wide range of input and output voltages.
一个RF(射频)dc-dc转换器已经开发，以证明在63兆赫使用反激配置的可能性。该变换器由两个部分组成:可变脉宽发生器(PWG)和带变压器和检测器的场效应管开关。设计的主要内容是提高开关、变压器和检测器的效率。异质结构AlGaAs/GaAs FET (HFET)的低电容，RF变压器的低漏感，快速肖特基二极管，多层陶瓷芯片电容器和表面贴装芯片电阻器使其能够实现从20 MHz到63 MHz的高效率。“硬开关”1瓦变换器达到60%至70%的效率，同时在宽范围的输入和输出电压下工作。
{"title":"Radio frequency dc-dc flyback converter","authors":"J. Biernacki, D. Czarkowski","doi":"10.1109/MWSCAS.2000.951594","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951594","url":null,"abstract":"An RF (radio frequency) dc-dc converter has been developed to demonstrate the possibility of using a flyback configuration at 63 MHz. The converter consists of two sections: a variable pulse width generator (PWG) and a FET switch with a transformer and a detector. The bulk of the design was concentrated on improving the efficiency of the switch, the transformer and the detector. Low capacitances of the heterostructure AlGaAs/GaAs FET (HFET), a low leakage inductance of the RF transformer, a fast Schottky diode, multilayer ceramic chip capacitors and surface mount chip resistors made it possible to achieve high efficiencies from 20 MHz to 63 MHz. The \"hard switching\" 1-Watt converter achieves 60 to 70 percent efficiency, while operating with a wide range of input and output voltages.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126088574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951454
R. Hashemian
An algorithm with logarithmic carry propagation delay is developed for high-density adders. The design procedure is introduced for the construction of a 64-bit adder with maximum path delay equivalent to 8 gate delays. The algorithm is based on the carry select technique with operands partitioned into very fine slices for both quick response and low gate counts. Another property observed in this algorithm is resource (hardware) sharing which is due to regularity of the carry channel structure. The design is coded in Verilog, simulated and implemented using XC4010E Xilinx FPGA technology.
{"title":"A new design for high speed and high-density carry select adders","authors":"R. Hashemian","doi":"10.1109/MWSCAS.2000.951454","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951454","url":null,"abstract":"An algorithm with logarithmic carry propagation delay is developed for high-density adders. The design procedure is introduced for the construction of a 64-bit adder with maximum path delay equivalent to 8 gate delays. The algorithm is based on the carry select technique with operands partitioned into very fine slices for both quick response and low gate counts. Another property observed in this algorithm is resource (hardware) sharing which is due to regularity of the carry channel structure. The design is coded in Verilog, simulated and implemented using XC4010E Xilinx FPGA technology.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122384185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952846
J. Bruce, P. Stubberud
Many dynamic element matching (DEM) algorithms for digital to analog use interconnection networks. In this paper, performance metrics that can compare interconnection networks used in DEM algorithms are introduced. Using these performance metrics, several interconnection networks are compared. Finally, two new hardware efficient networks for DEM are introduced.
{"title":"A comparison of hardware efficient dynamic element matching networks for digital to analog converters","authors":"J. Bruce, P. Stubberud","doi":"10.1109/MWSCAS.2000.952846","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952846","url":null,"abstract":"Many dynamic element matching (DEM) algorithms for digital to analog use interconnection networks. In this paper, performance metrics that can compare interconnection networks used in DEM algorithms are introduced. Using these performance metrics, several interconnection networks are compared. Finally, two new hardware efficient networks for DEM are introduced.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121851718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951628
Wen J. Li, Tammy Ho, Gordon M. H. Chan, P. Leong, H. Wong
Presents the development of a vibration-induced power generator with total volume of /spl sim/1cm/sup 3/ that uses laser-micromachined springs to convert mechanical energy into useful electrical power. The goal of this project is to create a minimally sized electric power generator capable of producing enough voltage to drive low-power ICs and/or micro sensors for applications where mechanical vibrations are present. Thus far, we have developed a generator capable of producing 2V DC with 64Hz to 120Hz input frequency at /spl sim/250/spl mu/m vibration amplitude. We have also demonstrated that this generator has enough power to drive an IR transmitter to send 140ms pulse trains with /spl sim/60sec power generation time.
{"title":"Infrared signal transmission by a laser-micromachined, vibration-induced power generator","authors":"Wen J. Li, Tammy Ho, Gordon M. H. Chan, P. Leong, H. Wong","doi":"10.1109/MWSCAS.2000.951628","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951628","url":null,"abstract":"Presents the development of a vibration-induced power generator with total volume of /spl sim/1cm/sup 3/ that uses laser-micromachined springs to convert mechanical energy into useful electrical power. The goal of this project is to create a minimally sized electric power generator capable of producing enough voltage to drive low-power ICs and/or micro sensors for applications where mechanical vibrations are present. Thus far, we have developed a generator capable of producing 2V DC with 64Hz to 120Hz input frequency at /spl sim/250/spl mu/m vibration amplitude. We have also demonstrated that this generator has enough power to drive an IR transmitter to send 140ms pulse trains with /spl sim/60sec power generation time.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"10 3-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129713141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951695
J. Ramírez-Angulo, R. Carvajal, A. Torralba
This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output to achieve low input resistance and very high output resistance. This scheme has a simulated bandwidth of 40 MHz and has been experimentally verified, obtaining 0.15 V input-output voltage requirements, 250 /spl Omega/ input resistance, greater than 200 M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1 V supply in a standard CMOS technology.
{"title":"Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements","authors":"J. Ramírez-Angulo, R. Carvajal, A. Torralba","doi":"10.1109/MWSCAS.2000.951695","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951695","url":null,"abstract":"This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output to achieve low input resistance and very high output resistance. This scheme has a simulated bandwidth of 40 MHz and has been experimentally verified, obtaining 0.15 V input-output voltage requirements, 250 /spl Omega/ input resistance, greater than 200 M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1 V supply in a standard CMOS technology.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129832358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951458
Yonghua Cong, R. Geiger
Gradient error can be compensated by optimizing switching sequences of DAC arrays. This paper establishes an absolute lower bound of integral nonlinearity (INL) which may be achieved by optimizing switching sequences. Optimal switching sequences that meet this lower bound are presented for one-dimensional linear gradient error compensation in unary (thermometer decoded) DAC arrays. The sequences can be used in row-column decoded current or capacitor unary arrays as well as R-string DACs, where the switching sequence is optimized in one dimension.
{"title":"Optimal switching sequences for one-dimensional linear gradient error compensation in unary DAC arrays","authors":"Yonghua Cong, R. Geiger","doi":"10.1109/MWSCAS.2000.951458","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951458","url":null,"abstract":"Gradient error can be compensated by optimizing switching sequences of DAC arrays. This paper establishes an absolute lower bound of integral nonlinearity (INL) which may be achieved by optimizing switching sequences. Optimal switching sequences that meet this lower bound are presented for one-dimensional linear gradient error compensation in unary (thermometer decoded) DAC arrays. The sequences can be used in row-column decoded current or capacitor unary arrays as well as R-string DACs, where the switching sequence is optimized in one dimension.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"90 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129846319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951590
J. J. Tapia, G. Atkin, J. LoCicero
A new domain, termed the frequency-delay domain, is used to design stable, all-pass digital filters resembling a given delay response in the least-squares sense. This spectral technique identifies the delay response of a stable, second-order, all-pass digital filter as a double sideband suppressed carrier amplitude modulated signal in the frequency-delay domain. Optimization techniques are used to render the filter coefficients. The algorithm is a significant improvement over related methods because it results in a physically realizable stable all-pass filter that closely approximates a desired delay response.
{"title":"Frequency-delay domain design of stable all-pass digital filters","authors":"J. J. Tapia, G. Atkin, J. LoCicero","doi":"10.1109/MWSCAS.2000.951590","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951590","url":null,"abstract":"A new domain, termed the frequency-delay domain, is used to design stable, all-pass digital filters resembling a given delay response in the least-squares sense. This spectral technique identifies the delay response of a stable, second-order, all-pass digital filter as a double sideband suppressed carrier amplitude modulated signal in the frequency-delay domain. Optimization techniques are used to render the filter coefficients. The algorithm is a significant improvement over related methods because it results in a physically realizable stable all-pass filter that closely approximates a desired delay response.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128210964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952896
A. David, T. Aboulnasr
In this paper, we propose a novel compression method applicable to digital images. We employ Maximum Entropy (ME) as the optimization criterion and Kalman Filter (KF) as means of implementing the compressor. We will show for compression ratios comparable to those of traditional methods, such as JPEG, the high frequency components of the signal, i.e. texture and edges, are preserved. The motivation for using ME as the optimization criterion is to avoid over-smoothing of the signal associated with traditional methods based on Mean Square Error (MSE). The ME criterion is motivated by the fact that it does not make any assumptions, regarding the unobserved data.
{"title":"A maximum entropy Kalman filter for image compression","authors":"A. David, T. Aboulnasr","doi":"10.1109/MWSCAS.2000.952896","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952896","url":null,"abstract":"In this paper, we propose a novel compression method applicable to digital images. We employ Maximum Entropy (ME) as the optimization criterion and Kalman Filter (KF) as means of implementing the compressor. We will show for compression ratios comparable to those of traditional methods, such as JPEG, the high frequency components of the signal, i.e. texture and edges, are preserved. The motivation for using ME as the optimization criterion is to avoid over-smoothing of the signal associated with traditional methods based on Mean Square Error (MSE). The ME criterion is motivated by the fact that it does not make any assumptions, regarding the unobserved data.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123596238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951671
M. Ghoneima, K. Sharaf, H. Ragai, A. El-Halim Zekry
In this paper, the issues of designing a low power VLSI implementation of the Viterbi decoder are addressed. We propose a new improvement in the VLSI architecture of the Add-Compare-Select unit (ACSU) and the State-Decode Unit (SDU) in the Viterbi decoder. These new schemes have led to a 47.6% and 43.9% power consumption reduction compared to the conventional ACSU and SDU architectures, respectively. These new improvements have also reduced the critical path of both units. The use of these new architectures in the design of a systolic sliding block Viterbi decoder, has led to a reduction of 25.8% in power consumption and 12.2% in die area. A 7.3% gain in decoding rate has also been gained without any degradation in error performance.
{"title":"Low power units for the Viterbi decoder","authors":"M. Ghoneima, K. Sharaf, H. Ragai, A. El-Halim Zekry","doi":"10.1109/MWSCAS.2000.951671","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951671","url":null,"abstract":"In this paper, the issues of designing a low power VLSI implementation of the Viterbi decoder are addressed. We propose a new improvement in the VLSI architecture of the Add-Compare-Select unit (ACSU) and the State-Decode Unit (SDU) in the Viterbi decoder. These new schemes have led to a 47.6% and 43.9% power consumption reduction compared to the conventional ACSU and SDU architectures, respectively. These new improvements have also reduced the critical path of both units. The use of these new architectures in the design of a systolic sliding block Viterbi decoder, has led to a reduction of 25.8% in power consumption and 12.2% in die area. A 7.3% gain in decoding rate has also been gained without any degradation in error performance.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114322771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952872
A. Younis, M. Hassoun
A high-speed fully differential folded cascode operational amplifier is presented. The operational amplifier uses fully differential boosting amplifiers to increase the open loop gain of the opamp. The opamp has a CMFB circuit that is made of a switched capacitor circuit and a continuous time CMFB circuit. The boosting amplifiers have continuous time CMFBs. The opamp is designed in TSMC 0.25 u digital CMOS process with 2.5 V power supply and achieved a dc gain of 81 dB with a 680 MHz unity gain frequency and 30 mW power consumption.
{"title":"A high speed fully differential CMOS opamp","authors":"A. Younis, M. Hassoun","doi":"10.1109/MWSCAS.2000.952872","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952872","url":null,"abstract":"A high-speed fully differential folded cascode operational amplifier is presented. The operational amplifier uses fully differential boosting amplifiers to increase the open loop gain of the opamp. The opamp has a CMFB circuit that is made of a switched capacitor circuit and a continuous time CMFB circuit. The boosting amplifiers have continuous time CMFBs. The opamp is designed in TSMC 0.25 u digital CMOS process with 2.5 V power supply and achieved a dc gain of 81 dB with a 680 MHz unity gain frequency and 30 mW power consumption.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116248377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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