Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951444
J. Coleman
Multibit delta-sigma conversion requires an internal DAC so extraordinarily accurate that signal processing to move DAC hardware-mismatch error outside the signal band appears necessary. Here the error-shaping DACs reported previously are shown mathematically to be special cases of a general architecture convenient for analysis and simulation.
{"title":"Mathematical unification of dynamic-element-matching methods for spectral shaping of hardware-mismatch errors","authors":"J. Coleman","doi":"10.1109/MWSCAS.2000.951444","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951444","url":null,"abstract":"Multibit delta-sigma conversion requires an internal DAC so extraordinarily accurate that signal processing to move DAC hardware-mismatch error outside the signal band appears necessary. Here the error-shaping DACs reported previously are shown mathematically to be special cases of a general architecture convenient for analysis and simulation.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"21 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132285776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951696
Huiyan Li, B. Gwee, J.S. Chang, M. T. Tan
A PWM sampling process for low-power digital Class D amplifiers with low harmonic distortion is proposed. By means of a novel algorithm, the Natural Sampling Process is emulated through a Delta-Compensation Uniform Sampling Process. This algorithm features a simple circuit implementation (small IC area), low power operation (low sampling rate) and a highly desirable low harmonic distortion.
{"title":"A novel pulse width modulation sampling process for low power, low distortion digital Class D amplifiers","authors":"Huiyan Li, B. Gwee, J.S. Chang, M. T. Tan","doi":"10.1109/MWSCAS.2000.951696","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951696","url":null,"abstract":"A PWM sampling process for low-power digital Class D amplifiers with low harmonic distortion is proposed. By means of a novel algorithm, the Natural Sampling Process is emulated through a Delta-Compensation Uniform Sampling Process. This algorithm features a simple circuit implementation (small IC area), low power operation (low sampling rate) and a highly desirable low harmonic distortion.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133232928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951670
Ramakrishnan Rajamoni, R. Bhagavathula, Ravi Pendse
Cache memories are used to reduce the memory latency in systems. While instruction references of a CPU exhibit high temporal and spatial locality, disk references exhibit very minimal temporal and spatial locality. Owing to the fact that most of the block replacement algorithms exploit the available locality to improve cache performance, they are more effective with CPU instruction caches than with disk caches. This paper presents the results of an investigation of cache write policies and the impact of the Least Recently Used (LRU) and the Segmented LRU (SLRU) block replacement algorithms on the performance of disk caches. To obtain optimal performance at all workloads and cache sizes, an adaptive write caching policy is introduced. The adaptive write caching policy does a dynamic selection of the write policy at run time. Simulations reveal that when the cache size is less than 2 MB, caches employing adaptive write caching policy are 17% faster over caches employing write-back policy. For cache sizes of 16 MB and above the performance improvement is 9%. The performance improvement of caches employing adaptive write caching policy over caches employing write-through policy is 2.65% for cache sizes of 2 MB and is 27%, for cache sizes of 16 MB and above. The adaptive write caching policy yields optimum performance for many of the disk workloads and disk cache sizes.
{"title":"Timing analysis of block replacement algorithms on disk caches","authors":"Ramakrishnan Rajamoni, R. Bhagavathula, Ravi Pendse","doi":"10.1109/MWSCAS.2000.951670","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951670","url":null,"abstract":"Cache memories are used to reduce the memory latency in systems. While instruction references of a CPU exhibit high temporal and spatial locality, disk references exhibit very minimal temporal and spatial locality. Owing to the fact that most of the block replacement algorithms exploit the available locality to improve cache performance, they are more effective with CPU instruction caches than with disk caches. This paper presents the results of an investigation of cache write policies and the impact of the Least Recently Used (LRU) and the Segmented LRU (SLRU) block replacement algorithms on the performance of disk caches. To obtain optimal performance at all workloads and cache sizes, an adaptive write caching policy is introduced. The adaptive write caching policy does a dynamic selection of the write policy at run time. Simulations reveal that when the cache size is less than 2 MB, caches employing adaptive write caching policy are 17% faster over caches employing write-back policy. For cache sizes of 16 MB and above the performance improvement is 9%. The performance improvement of caches employing adaptive write caching policy over caches employing write-through policy is 2.65% for cache sizes of 2 MB and is 27%, for cache sizes of 16 MB and above. The adaptive write caching policy yields optimum performance for many of the disk workloads and disk cache sizes.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116929534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951433
G. Jovanovic-Dolecek, M. Aguilar-Ponce
Treats the harmonic interference removal where the frequency of the interference is a rational number and known in advance. In order to remove the interference from the corrupted signal without distortion we propose a structure, which uses a comb filter with a fractional delay. The polyphase structure with two output branches approximates a fractional delay. The proposed structure is convenient for the case when the delay is a ratio of high integers.
{"title":"Harmonic interference removal using a fractional delay filter","authors":"G. Jovanovic-Dolecek, M. Aguilar-Ponce","doi":"10.1109/MWSCAS.2000.951433","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951433","url":null,"abstract":"Treats the harmonic interference removal where the frequency of the interference is a rational number and known in advance. In order to remove the interference from the corrupted signal without distortion we propose a structure, which uses a comb filter with a fractional delay. The polyphase structure with two output branches approximates a fractional delay. The proposed structure is convenient for the case when the delay is a ratio of high integers.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114955059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951659
M. Rizkalla, K. Palaniswamy, A. Sinha, M. El-Sharkawy, P. Salama, S. Lyshevski, H. Gundrum
An 8-bit VHDL based 2-D median filter is designed using Mentor Graphic tools. The algorithm is based on sorting pixel samples and extracting their median values. The code was synthesized and optimized for an IC layout using CMOS 2 micron technology. The principal organization of the memory elements to store data that perform two dimensional transpose application is presented. A Matlab program for this algorithm was written, tested, and verified on 400/spl times/400 pixel images.
{"title":"ASIC memory design of 2-D median filters","authors":"M. Rizkalla, K. Palaniswamy, A. Sinha, M. El-Sharkawy, P. Salama, S. Lyshevski, H. Gundrum","doi":"10.1109/MWSCAS.2000.951659","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951659","url":null,"abstract":"An 8-bit VHDL based 2-D median filter is designed using Mentor Graphic tools. The algorithm is based on sorting pixel samples and extracting their median values. The code was synthesized and optimized for an IC layout using CMOS 2 micron technology. The principal organization of the memory elements to store data that perform two dimensional transpose application is presented. A Matlab program for this algorithm was written, tested, and verified on 400/spl times/400 pixel images.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116108097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951388
P. Aronhime, Tongfeng Qian
A comparison of two simple models for operational amplifiers is undertaken in this paper. One model is termed the one-pole rolloff model, and this model has been used with good results for several decades. The other model has been utilized from time-to-time in recent years. Three criteria are stated for a "good" model, and it is shown that one of the models fails to meet one of the criteria.
{"title":"Comparison of basic operational amplifier models","authors":"P. Aronhime, Tongfeng Qian","doi":"10.1109/MWSCAS.2000.951388","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951388","url":null,"abstract":"A comparison of two simple models for operational amplifiers is undertaken in this paper. One model is termed the one-pole rolloff model, and this model has been used with good results for several decades. The other model has been utilized from time-to-time in recent years. Three criteria are stated for a \"good\" model, and it is shown that one of the models fails to meet one of the criteria.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116162980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951399
A. Helmy, M. Rizkalla, M.M. Holdmann, P. Salama
Presents the theory supporting a new diagnostic method for a thermographic system. A finite element analysis of a hot thyroid nodule is developed and used for diagnosis utilizing thermal imaging. The new non-invasive diagnostic technique was applied to patients having Graves' diseases at the Indiana University (IU) Hospital, and compared with the existing scheme that utilizes I Scan. The results of the new diagnostic method were in very good agreement with the current existing method. The new technique is advantageous in that it can be safely applied to children and pregnant women, and is cost effective compared to the current techniques.
{"title":"Finite element analysis for simulating a hot thyroid nodule","authors":"A. Helmy, M. Rizkalla, M.M. Holdmann, P. Salama","doi":"10.1109/MWSCAS.2000.951399","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951399","url":null,"abstract":"Presents the theory supporting a new diagnostic method for a thermographic system. A finite element analysis of a hot thyroid nodule is developed and used for diagnosis utilizing thermal imaging. The new non-invasive diagnostic technique was applied to patients having Graves' diseases at the Indiana University (IU) Hospital, and compared with the existing scheme that utilizes I Scan. The results of the new diagnostic method were in very good agreement with the current existing method. The new technique is advantageous in that it can be safely applied to children and pregnant women, and is cost effective compared to the current techniques.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115013540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951683
Ko-Chi Kuo, A. Leuciuc
This paper presents a new configuration for linear MOS voltage-to-current converters (transconductors). The proposed circuit combines two previously reported linearization methods. The novel topology exhibits very good linearity for both balanced and unbalanced inputs. The linearity is preserved during the tuning process for a moderate range of transconductance values.
{"title":"A novel linear tunable MOS transconductor","authors":"Ko-Chi Kuo, A. Leuciuc","doi":"10.1109/MWSCAS.2000.951683","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951683","url":null,"abstract":"This paper presents a new configuration for linear MOS voltage-to-current converters (transconductors). The proposed circuit combines two previously reported linearization methods. The novel topology exhibits very good linearity for both balanced and unbalanced inputs. The linearity is preserved during the tuning process for a moderate range of transconductance values.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116650800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951413
U. Çilingiroğlu, Sicheng Chen
A novel CMOS imaging chip for real-time range finding is described. The system can extract range information without any mechanical movement and all the signal processing is done on chip. All the image sensors and mixed-signal processors are integrated in a chip. A prototype chip has been fabricated in 0.5 /spl mu/m CMOS technology that occupies 0.9 mm /spl times/ 0.9 mm silicon area. It can report the distance in the range 1.5 m - 10 m in 18 scales. Analog power dissipation is 50 mW for a 5 V power supply. The paper presents the proposed range extraction concept, describes the technique and circuit architecture, and verifies functionality by simulated results.
介绍了一种用于实时测距的新型CMOS成像芯片。该系统无需任何机械运动即可提取距离信息，所有信号处理均在芯片上完成。所有的图像传感器和混合信号处理器都集成在一个芯片上。原型芯片采用0.5 /spl μ m CMOS技术，占据0.9 mm /spl倍/ 0.9 mm的硅面积。它可以报告距离范围在1.5米至10米18尺度。模拟功耗为50mw的5v电源。本文介绍了所提出的测距提取概念，描述了技术和电路结构，并通过仿真结果验证了其功能。
{"title":"A CMOS imaging chip for real-time range finding","authors":"U. Çilingiroğlu, Sicheng Chen","doi":"10.1109/MWSCAS.2000.951413","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951413","url":null,"abstract":"A novel CMOS imaging chip for real-time range finding is described. The system can extract range information without any mechanical movement and all the signal processing is done on chip. All the image sensors and mixed-signal processors are integrated in a chip. A prototype chip has been fabricated in 0.5 /spl mu/m CMOS technology that occupies 0.9 mm /spl times/ 0.9 mm silicon area. It can report the distance in the range 1.5 m - 10 m in 18 scales. Analog power dissipation is 50 mW for a 5 V power supply. The paper presents the proposed range extraction concept, describes the technique and circuit architecture, and verifies functionality by simulated results.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951606
B. Robisson, J. Ganascia
By integrating in the representation of electrical circuits the properties of the physical laws which govern their functioning, we propose a way to construct a representation such that two circuits which "function in the same way" have the same representation. In this article, we show that the bond graph representation is a good candidate for such a functional representation because its formalism deletes a piece of information which is useless for analyzing the circuit's functioning. However, the existing algorithms which transform a circuit into a bond graph are not fully adapted to this formalism. A more suitable algorithm is proposed, based on the Tutte decomposition of graphs. This algorithm associates a unique bond graph with a given circuit and it formalizes the "inspection method" suggested by Karnopp [1975]. With this new algorithm, the gap between the bond graph representation and the functional representation is reduced.
{"title":"On the representation of electrical networks","authors":"B. Robisson, J. Ganascia","doi":"10.1109/MWSCAS.2000.951606","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951606","url":null,"abstract":"By integrating in the representation of electrical circuits the properties of the physical laws which govern their functioning, we propose a way to construct a representation such that two circuits which \"function in the same way\" have the same representation. In this article, we show that the bond graph representation is a good candidate for such a functional representation because its formalism deletes a piece of information which is useless for analyzing the circuit's functioning. However, the existing algorithms which transform a circuit into a bond graph are not fully adapted to this formalism. A more suitable algorithm is proposed, based on the Tutte decomposition of graphs. This algorithm associates a unique bond graph with a given circuit and it formalizes the \"inspection method\" suggested by Karnopp [1975]. With this new algorithm, the gap between the bond graph representation and the functional representation is reduced.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123391480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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