Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952904
M. Sarcinelli-Filho, H. Schneebeli, Eliete Caldeira, R. Carelli, O. Nasisi, C. Soria
This work addresses the use of optical flow to supervise the navigation of mobile robots. The amount of computation, the number of image frames to be stored and the reliability of the optical flow vectors generated should be acquainted for by programming a suitable algorithm for the onboard calculation of the optical flow. Two good candidates to be this algorithm are selected from the literature and are here considered. A slight modification of one of them is here proposed, and thus three algorithms are evaluated. This evaluation is based on two experiments whose results are reported. The conclusion is that the new algorithm here proposed is more suitable for the application.
{"title":"On the use of optical flow in mobile robot navigation: the search for a suitable algorithm","authors":"M. Sarcinelli-Filho, H. Schneebeli, Eliete Caldeira, R. Carelli, O. Nasisi, C. Soria","doi":"10.1109/MWSCAS.2000.952904","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952904","url":null,"abstract":"This work addresses the use of optical flow to supervise the navigation of mobile robots. The amount of computation, the number of image frames to be stored and the reliability of the optical flow vectors generated should be acquainted for by programming a suitable algorithm for the onboard calculation of the optical flow. Two good candidates to be this algorithm are selected from the literature and are here considered. A slight modification of one of them is here proposed, and thus three algorithms are evaluated. This evaluation is based on two experiments whose results are reported. The conclusion is that the new algorithm here proposed is more suitable for the application.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123792362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951630
H. Kulah, N. Yazdi, K. Najafi
Presents a CMOS interface electronics for monolithic micromachined capacitive accelerometer systems. The interface electronics is a fully differential switched-capacitor charge integrator with its internal clock generator and sensor feedback circuit for closed-loop operation. The circuit is designed for open-loop and closed-loop operations, and provides both digital and differential analog outputs. One of the main advantages of this chip is that it can be monolithically integrated with the sensor, resulting in a considerably increased sensor module performance by decreasing the overall system area, minimizing the interface parasitics, and simplifying the packaging. The interface electronics operates at 200kHz sampling clock and provides an adjustable sensitivity between 0.3 and 1.2V/pF with better than 100aF expected resolution resulting in a 93dB dynamic range for 1Hz bandwidth. The total chip dissipates less than 7.2mW power from a single 5V supply, and occupies an area of 3.4/spl times/3.6 mm/sup 2/ in 3/spl mu/m one-metal two-poly p-well. CMOS process of University of Michigan.
介绍了一种用于单片微机械电容式加速度计系统的CMOS接口电子学。接口电子器件是一个全差分开关电容电荷积分器，其内部时钟发生器和传感器反馈电路用于闭环操作。该电路设计用于开环和闭环操作，并提供数字和差分模拟输出。该芯片的主要优点之一是它可以与传感器单片集成，从而通过减小整个系统面积、最小化接口寄生和简化封装来显着提高传感器模块的性能。接口电子器件在200kHz采样时钟下工作，提供0.3至1.2V/pF之间的可调灵敏度，预期分辨率优于100aF，从而在1Hz带宽下实现93dB动态范围。单5V电源的总功耗小于7.2mW，占地面积为3.4/spl倍/3.6 mm/sup / in /3 /spl mu/m单金属双聚p阱。密歇根大学的CMOS工艺。
{"title":"A CMOS switched-capacitor interface circuit for an integrated accelerometer","authors":"H. Kulah, N. Yazdi, K. Najafi","doi":"10.1109/MWSCAS.2000.951630","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951630","url":null,"abstract":"Presents a CMOS interface electronics for monolithic micromachined capacitive accelerometer systems. The interface electronics is a fully differential switched-capacitor charge integrator with its internal clock generator and sensor feedback circuit for closed-loop operation. The circuit is designed for open-loop and closed-loop operations, and provides both digital and differential analog outputs. One of the main advantages of this chip is that it can be monolithically integrated with the sensor, resulting in a considerably increased sensor module performance by decreasing the overall system area, minimizing the interface parasitics, and simplifying the packaging. The interface electronics operates at 200kHz sampling clock and provides an adjustable sensitivity between 0.3 and 1.2V/pF with better than 100aF expected resolution resulting in a 93dB dynamic range for 1Hz bandwidth. The total chip dissipates less than 7.2mW power from a single 5V supply, and occupies an area of 3.4/spl times/3.6 mm/sup 2/ in 3/spl mu/m one-metal two-poly p-well. CMOS process of University of Michigan.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A multi-layered perceptron neural network with the backpropagation algorithm (MLP/BP) is realized as an equalizer for nonreturn-to-zero (NRZ) signal recovery in band-limited channels. It is applied as an adaptive filter to recover the NRZ signal. By computer simulations, the proposed design can recover 100 MHz NRZ data in a 10 MHz channel.
{"title":"A MLP/BP-based equalizer for NRZ signal recovery in band-limited channels","authors":"Terng-Ren Hsu, Terng-Yin Hsu, Hsuan-Yu Liu, Shuenn-Der Tzeng, Jyh-Neng Yang, Chen-Yi Lee","doi":"10.1109/MWSCAS.2000.951462","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951462","url":null,"abstract":"A multi-layered perceptron neural network with the backpropagation algorithm (MLP/BP) is realized as an equalizer for nonreturn-to-zero (NRZ) signal recovery in band-limited channels. It is applied as an adaptive filter to recover the NRZ signal. By computer simulations, the proposed design can recover 100 MHz NRZ data in a 10 MHz channel.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129624807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951442
M.E. Schlannann, R. Geiger
A simple transresistance amplifier is introduced that is both linear and compact. It consists of only two transistors and a current source. Despite its simplicity, its linearity properties are attractive when compared to existing transresistance structures. Simulation results comparing the performance of the new structure with several other single-ended and balanced structures are presented along with experimental results.
{"title":"A simple 2-transistor transresistor","authors":"M.E. Schlannann, R. Geiger","doi":"10.1109/MWSCAS.2000.951442","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951442","url":null,"abstract":"A simple transresistance amplifier is introduced that is both linear and compact. It consists of only two transistors and a current source. Despite its simplicity, its linearity properties are attractive when compared to existing transresistance structures. Simulation results comparing the performance of the new structure with several other single-ended and balanced structures are presented along with experimental results.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130728449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951402
N. Clark, P. Furth
Develops a new paradigm, based on massively parallel analog processing coupled with a MEMs micro-mirror device; for developing intelligent vision systems that is capable of performing adaptive optics at rates exceeding 1 kHz and 3D imaging at bandwidths exceeding 100 Hz. The design and modeling methodologies associated with our smart vision chip are presented along with experimental results that characterize its performance. We also present design and modeling methodologies of micro-mirror devices along with experimental results that characterize their performance in typical adaptive optic systems. Finally, we present modeling and simulation methodologies of adaptive optics systems along with experimental results used to design and test an adaptive optic system. The design and modeling methodologies that are presented lend themselves to facilitating the design and development of a wide variety of other sophisticated vision systems. In addition to speed, the approach offers advantages in low cost batch fabrication, compact size, low power consumption, and radiation tolerance, making it ideal for many applications.
{"title":"Design and performance evaluation of a silicon eye using micro-mirrors","authors":"N. Clark, P. Furth","doi":"10.1109/MWSCAS.2000.951402","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951402","url":null,"abstract":"Develops a new paradigm, based on massively parallel analog processing coupled with a MEMs micro-mirror device; for developing intelligent vision systems that is capable of performing adaptive optics at rates exceeding 1 kHz and 3D imaging at bandwidths exceeding 100 Hz. The design and modeling methodologies associated with our smart vision chip are presented along with experimental results that characterize its performance. We also present design and modeling methodologies of micro-mirror devices along with experimental results that characterize their performance in typical adaptive optic systems. Finally, we present modeling and simulation methodologies of adaptive optics systems along with experimental results used to design and test an adaptive optic system. The design and modeling methodologies that are presented lend themselves to facilitating the design and development of a wide variety of other sophisticated vision systems. In addition to speed, the approach offers advantages in low cost batch fabrication, compact size, low power consumption, and radiation tolerance, making it ideal for many applications.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131094801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951601
P. B. Wu, R. Mack, R. Massara
An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.
{"title":"A multi-level netlist partitioning approach to hierarchical layout design of analog ICs","authors":"P. B. Wu, R. Mack, R. Massara","doi":"10.1109/MWSCAS.2000.951601","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951601","url":null,"abstract":"An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130440315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951634
Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, Chen-Yi Lee
A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient key equation solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35/spl mu/m CMOS IP4M standard cells, where the total gate count is about 16K/spl sim/17K. Test results show that the RS decoder chip can run up to 87MHz.
{"title":"A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm","authors":"Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, Chen-Yi Lee","doi":"10.1109/MWSCAS.2000.951634","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951634","url":null,"abstract":"A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient key equation solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35/spl mu/m CMOS IP4M standard cells, where the total gate count is about 16K/spl sim/17K. Test results show that the RS decoder chip can run up to 87MHz.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131151979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951662
A. Goldovsky, H. Srinivas, R. Kolagotla, R. Hengst
This paper presents a new prefix tree adder that is faster than previously published adder designs. The speed improvement is achieved by rearranging the logic for the computation of the sum bits in the final stage of the adder so as to exploit the differing delays with which the group-transmit, group-generate, and carries (at each and every bit position) are generated. Previous adder designs, either used group transmit signals or group propagate signals to build prefix tree for carry generation. They did not exploit the fact that in the last stage of the parallel prefix carry tree, this difference can allow rearranging of the logic for reduced logic depth. For designs where a uniform layout of the adder is not a big concern (e.g., in communication and signal processing custom chips), the negative effect of interconnect delays at the last stage of the adder can be reduced by employing a left-to-right routing of the most-significant group generate and group-transmit signals. This is useful for large word-length (greater or equal to 32) adders. Incorporating these improvements into the adder design has resulted in about 15% improvement in speed over previously proposed adder designs. A 32-bit radix-2 prefix tree adder implementation of the proposed scheme has a delay of 0.7 ns at 1.5 volts 100 C in the Lucent's 0.16-/spl mu/m static CMOS technology.
{"title":"A folded 32-bit prefix tree adder in 0.16-/spl mu/m static CMOS","authors":"A. Goldovsky, H. Srinivas, R. Kolagotla, R. Hengst","doi":"10.1109/MWSCAS.2000.951662","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951662","url":null,"abstract":"This paper presents a new prefix tree adder that is faster than previously published adder designs. The speed improvement is achieved by rearranging the logic for the computation of the sum bits in the final stage of the adder so as to exploit the differing delays with which the group-transmit, group-generate, and carries (at each and every bit position) are generated. Previous adder designs, either used group transmit signals or group propagate signals to build prefix tree for carry generation. They did not exploit the fact that in the last stage of the parallel prefix carry tree, this difference can allow rearranging of the logic for reduced logic depth. For designs where a uniform layout of the adder is not a big concern (e.g., in communication and signal processing custom chips), the negative effect of interconnect delays at the last stage of the adder can be reduced by employing a left-to-right routing of the most-significant group generate and group-transmit signals. This is useful for large word-length (greater or equal to 32) adders. Incorporating these improvements into the adder design has resulted in about 15% improvement in speed over previously proposed adder designs. A 32-bit radix-2 prefix tree adder implementation of the proposed scheme has a delay of 0.7 ns at 1.5 volts 100 C in the Lucent's 0.16-/spl mu/m static CMOS technology.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126063299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.952855
C. Fayomi, G. Roberts, M. Sawan
This paper presents a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. Simulation results using a 0.18 /spl mu/m digital CMOS process show that a resolution greater than 16 bits can be obtained with a 1.65 V supply voltage. Operation is also possible for supply voltages close to transistor threshold (e.g., 0.5 V).
{"title":"Low-voltage CMOS analog switch for high precision sample-and-hold circuit","authors":"C. Fayomi, G. Roberts, M. Sawan","doi":"10.1109/MWSCAS.2000.952855","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.952855","url":null,"abstract":"This paper presents a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. Simulation results using a 0.18 /spl mu/m digital CMOS process show that a resolution greater than 16 bits can be obtained with a 1.65 V supply voltage. Operation is also possible for supply voltages close to transistor threshold (e.g., 0.5 V).","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126615532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951480
Yuke Wang, R. Drechsler, Xiaoyu Song
Ordered Kronecker functional decision diagrams (OKFDD) are an extension of the popular ordered binary decision diagrams (OBDD) and as such provide a more compact representation of Boolean functions than OBDDs. Symmetric functions are useful in logic synthesis. In this paper, we present an optimal algorithm for detecting symmetric functions represented in OKFDDs.
{"title":"Optimal symmetry detection for OKFDDs","authors":"Yuke Wang, R. Drechsler, Xiaoyu Song","doi":"10.1109/MWSCAS.2000.951480","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951480","url":null,"abstract":"Ordered Kronecker functional decision diagrams (OKFDD) are an extension of the popular ordered binary decision diagrams (OBDD) and as such provide a more compact representation of Boolean functions than OBDDs. Symmetric functions are useful in logic synthesis. In this paper, we present an optimal algorithm for detecting symmetric functions represented in OKFDDs.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125759998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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