Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951662
A. Goldovsky, H. Srinivas, R. Kolagotla, R. Hengst
This paper presents a new prefix tree adder that is faster than previously published adder designs. The speed improvement is achieved by rearranging the logic for the computation of the sum bits in the final stage of the adder so as to exploit the differing delays with which the group-transmit, group-generate, and carries (at each and every bit position) are generated. Previous adder designs, either used group transmit signals or group propagate signals to build prefix tree for carry generation. They did not exploit the fact that in the last stage of the parallel prefix carry tree, this difference can allow rearranging of the logic for reduced logic depth. For designs where a uniform layout of the adder is not a big concern (e.g., in communication and signal processing custom chips), the negative effect of interconnect delays at the last stage of the adder can be reduced by employing a left-to-right routing of the most-significant group generate and group-transmit signals. This is useful for large word-length (greater or equal to 32) adders. Incorporating these improvements into the adder design has resulted in about 15% improvement in speed over previously proposed adder designs. A 32-bit radix-2 prefix tree adder implementation of the proposed scheme has a delay of 0.7 ns at 1.5 volts 100 C in the Lucent's 0.16-/spl mu/m static CMOS technology.
{"title":"A folded 32-bit prefix tree adder in 0.16-/spl mu/m static CMOS","authors":"A. Goldovsky, H. Srinivas, R. Kolagotla, R. Hengst","doi":"10.1109/MWSCAS.2000.951662","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951662","url":null,"abstract":"This paper presents a new prefix tree adder that is faster than previously published adder designs. The speed improvement is achieved by rearranging the logic for the computation of the sum bits in the final stage of the adder so as to exploit the differing delays with which the group-transmit, group-generate, and carries (at each and every bit position) are generated. Previous adder designs, either used group transmit signals or group propagate signals to build prefix tree for carry generation. They did not exploit the fact that in the last stage of the parallel prefix carry tree, this difference can allow rearranging of the logic for reduced logic depth. For designs where a uniform layout of the adder is not a big concern (e.g., in communication and signal processing custom chips), the negative effect of interconnect delays at the last stage of the adder can be reduced by employing a left-to-right routing of the most-significant group generate and group-transmit signals. This is useful for large word-length (greater or equal to 32) adders. Incorporating these improvements into the adder design has resulted in about 15% improvement in speed over previously proposed adder designs. A 32-bit radix-2 prefix tree adder implementation of the proposed scheme has a delay of 0.7 ns at 1.5 volts 100 C in the Lucent's 0.16-/spl mu/m static CMOS technology.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126063299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951595
H. Chiueh, J. Choma, J. Draper
A Temperature Monitoring Interface Circuit for PowerPC systems has been designed, implemented, and tested. This design yields a suitable balance of hardware and software components in the Integrated Thermal Management (ITEM) System. Powerview and Lager tools were used to design this chip in one man-month. This circuit was fabricated in an HP 0.5 /spl mu/m single-poly 3-metal process through MOSIS. Laboratory testing agreed with simulation results in verifying the functionality and performance of this circuit to 50 MHz, which is the targeted system speed of the ITEM multi-node computer system.
{"title":"Implementation of a Temperature Monitoring Interface Circuit for PowerPC systems","authors":"H. Chiueh, J. Choma, J. Draper","doi":"10.1109/MWSCAS.2000.951595","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951595","url":null,"abstract":"A Temperature Monitoring Interface Circuit for PowerPC systems has been designed, implemented, and tested. This design yields a suitable balance of hardware and software components in the Integrated Thermal Management (ITEM) System. Powerview and Lager tools were used to design this chip in one man-month. This circuit was fabricated in an HP 0.5 /spl mu/m single-poly 3-metal process through MOSIS. Laboratory testing agreed with simulation results in verifying the functionality and performance of this circuit to 50 MHz, which is the targeted system speed of the ITEM multi-node computer system.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951396
A. Low, P. Hasler
This paper presents an overview of series voltage regulators, beginning with single-transistor designs and exploring the various design issues and concepts. The regulating characteristics of nFET and pFET single-transistor regulators are compared analytically and experimentally to determine an optimal starting topology. The design of these simple regulators is taken a step further by applying floating-gate techniques to improve the flexibility of the existing design and the ability to customize the regulator bias points.
{"title":"Basics of floating-gate low-dropout voltage regulators","authors":"A. Low, P. Hasler","doi":"10.1109/MWSCAS.2000.951396","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951396","url":null,"abstract":"This paper presents an overview of series voltage regulators, beginning with single-transistor designs and exploring the various design issues and concepts. The regulating characteristics of nFET and pFET single-transistor regulators are compared analytically and experimentally to determine an optimal starting topology. The design of these simple regulators is taken a step further by applying floating-gate techniques to improve the flexibility of the existing design and the ability to customize the regulator bias points.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127705214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951592
Shaoyi Wang, C. Zukowski
Selective precharge is a low-power circuit technique that can significantly reduce the average energy use in large fan-in logic arrays. In this paper, we investigate application of this technique to two specific real examples; a content addressable memory (CAM) used in a routing table and a programmable logic array (PLA) used for table-lookup function evaluation. We show that significant energy savings is possible, and we discuss the impact of various array characteristics.
{"title":"Energy reduction from using selective precharge in two different logic arrays","authors":"Shaoyi Wang, C. Zukowski","doi":"10.1109/MWSCAS.2000.951592","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951592","url":null,"abstract":"Selective precharge is a low-power circuit technique that can significantly reduce the average energy use in large fan-in logic arrays. In this paper, we investigate application of this technique to two specific real examples; a content addressable memory (CAM) used in a routing table and a programmable logic array (PLA) used for table-lookup function evaluation. We show that significant energy savings is possible, and we discuss the impact of various array characteristics.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129206943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951444
J. Coleman
Multibit delta-sigma conversion requires an internal DAC so extraordinarily accurate that signal processing to move DAC hardware-mismatch error outside the signal band appears necessary. Here the error-shaping DACs reported previously are shown mathematically to be special cases of a general architecture convenient for analysis and simulation.
{"title":"Mathematical unification of dynamic-element-matching methods for spectral shaping of hardware-mismatch errors","authors":"J. Coleman","doi":"10.1109/MWSCAS.2000.951444","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951444","url":null,"abstract":"Multibit delta-sigma conversion requires an internal DAC so extraordinarily accurate that signal processing to move DAC hardware-mismatch error outside the signal band appears necessary. Here the error-shaping DACs reported previously are shown mathematically to be special cases of a general architecture convenient for analysis and simulation.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"21 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132285776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951601
P. B. Wu, R. Mack, R. Massara
An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.
{"title":"A multi-level netlist partitioning approach to hierarchical layout design of analog ICs","authors":"P. B. Wu, R. Mack, R. Massara","doi":"10.1109/MWSCAS.2000.951601","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951601","url":null,"abstract":"An algorithmic netlist partitioning approach for the hierarchical design of analog layout is presented. In addition to considering routability, partitioning operates under analog performance and area efficiency constraints. The multi-level partitioner is embedded with built-in move operators to enable designers to balance quality and design time. The effectiveness of the approach is shown by example results.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130440315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951442
M.E. Schlannann, R. Geiger
A simple transresistance amplifier is introduced that is both linear and compact. It consists of only two transistors and a current source. Despite its simplicity, its linearity properties are attractive when compared to existing transresistance structures. Simulation results comparing the performance of the new structure with several other single-ended and balanced structures are presented along with experimental results.
{"title":"A simple 2-transistor transresistor","authors":"M.E. Schlannann, R. Geiger","doi":"10.1109/MWSCAS.2000.951442","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951442","url":null,"abstract":"A simple transresistance amplifier is introduced that is both linear and compact. It consists of only two transistors and a current source. Despite its simplicity, its linearity properties are attractive when compared to existing transresistance structures. Simulation results comparing the performance of the new structure with several other single-ended and balanced structures are presented along with experimental results.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130728449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951683
Ko-Chi Kuo, A. Leuciuc
This paper presents a new configuration for linear MOS voltage-to-current converters (transconductors). The proposed circuit combines two previously reported linearization methods. The novel topology exhibits very good linearity for both balanced and unbalanced inputs. The linearity is preserved during the tuning process for a moderate range of transconductance values.
{"title":"A novel linear tunable MOS transconductor","authors":"Ko-Chi Kuo, A. Leuciuc","doi":"10.1109/MWSCAS.2000.951683","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951683","url":null,"abstract":"This paper presents a new configuration for linear MOS voltage-to-current converters (transconductors). The proposed circuit combines two previously reported linearization methods. The novel topology exhibits very good linearity for both balanced and unbalanced inputs. The linearity is preserved during the tuning process for a moderate range of transconductance values.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116650800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951670
Ramakrishnan Rajamoni, R. Bhagavathula, Ravi Pendse
Cache memories are used to reduce the memory latency in systems. While instruction references of a CPU exhibit high temporal and spatial locality, disk references exhibit very minimal temporal and spatial locality. Owing to the fact that most of the block replacement algorithms exploit the available locality to improve cache performance, they are more effective with CPU instruction caches than with disk caches. This paper presents the results of an investigation of cache write policies and the impact of the Least Recently Used (LRU) and the Segmented LRU (SLRU) block replacement algorithms on the performance of disk caches. To obtain optimal performance at all workloads and cache sizes, an adaptive write caching policy is introduced. The adaptive write caching policy does a dynamic selection of the write policy at run time. Simulations reveal that when the cache size is less than 2 MB, caches employing adaptive write caching policy are 17% faster over caches employing write-back policy. For cache sizes of 16 MB and above the performance improvement is 9%. The performance improvement of caches employing adaptive write caching policy over caches employing write-through policy is 2.65% for cache sizes of 2 MB and is 27%, for cache sizes of 16 MB and above. The adaptive write caching policy yields optimum performance for many of the disk workloads and disk cache sizes.
{"title":"Timing analysis of block replacement algorithms on disk caches","authors":"Ramakrishnan Rajamoni, R. Bhagavathula, Ravi Pendse","doi":"10.1109/MWSCAS.2000.951670","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951670","url":null,"abstract":"Cache memories are used to reduce the memory latency in systems. While instruction references of a CPU exhibit high temporal and spatial locality, disk references exhibit very minimal temporal and spatial locality. Owing to the fact that most of the block replacement algorithms exploit the available locality to improve cache performance, they are more effective with CPU instruction caches than with disk caches. This paper presents the results of an investigation of cache write policies and the impact of the Least Recently Used (LRU) and the Segmented LRU (SLRU) block replacement algorithms on the performance of disk caches. To obtain optimal performance at all workloads and cache sizes, an adaptive write caching policy is introduced. The adaptive write caching policy does a dynamic selection of the write policy at run time. Simulations reveal that when the cache size is less than 2 MB, caches employing adaptive write caching policy are 17% faster over caches employing write-back policy. For cache sizes of 16 MB and above the performance improvement is 9%. The performance improvement of caches employing adaptive write caching policy over caches employing write-through policy is 2.65% for cache sizes of 2 MB and is 27%, for cache sizes of 16 MB and above. The adaptive write caching policy yields optimum performance for many of the disk workloads and disk cache sizes.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116929534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-08-08DOI: 10.1109/MWSCAS.2000.951634
Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, Chen-Yi Lee
A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient key equation solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35/spl mu/m CMOS IP4M standard cells, where the total gate count is about 16K/spl sim/17K. Test results show that the RS decoder chip can run up to 87MHz.
{"title":"A (204,188) Reed-Solomon decoder using decomposed Euclidean algorithm","authors":"Hsie-Chia Chang, Chih-Yu Chen, Shu-Hui Tsai, Chen-Yi Lee","doi":"10.1109/MWSCAS.2000.951634","DOIUrl":"https://doi.org/10.1109/MWSCAS.2000.951634","url":null,"abstract":"A (204, 188) Reed-Solomon decoder for DVB application is presented. The RS decoder features an area-efficient key equation solver using a novel decomposed Euclidean algorithm. We implement the RS decoder using 0.35/spl mu/m CMOS IP4M standard cells, where the total gate count is about 16K/spl sim/17K. Test results show that the RS decoder chip can run up to 87MHz.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131151979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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