Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745188
R. Murgai, J. Jain, M. Fujita
The most common way to build the reduced ordered binary decision diagram (ROBDD) of a complex gate (or function) f of a network is bottom-up, i.e., by first building the ROBDDs of the sub-expressions of f and then suitably combining them. Such a method, however, has been found to suffer from memory explosion, even when the ROBDD of f is not large. This leads to the following fundamental question: Given an arbitrary boolean expression f(x/sub 1/,x/sub 2/,...x/sub n/) and the ROBDDs of t/sub t/s (in terms of circuit inputs), how should the ROBDD of f be constructed so that the intermediate memory repaired to build the ROBDD is minimized, and a heavy time penalty is not incurred? In this paper, we address this question for a restricted f: a multi-way AND or OR operation. We propose various schemes for scheduling the binary operations of the expression f. These schemes are based on an analysis of the sizes and support-sets of the intermediate ROBDDs. One of our main contributions is to prove that under certain conditions, these schemes provide the optimum solution. We tested the proposed schemes on complex functions present within ISCAS85 as well as large industrial circuits. On average, our best scheme (which is based on size as well as support-set of the component ROBDDs) yields a 25% reduction in ROBDD sizes as compared to the technique implemented in SIS [1992]. In some cases. A reduction of up to 4 orders of magnitude was seen. Since ROBDDs are a key technology in various synthesis and verification tasks. Our work can be of immediate use in all these applications.
{"title":"Efficient scheduling techniques for ROBDD construction","authors":"R. Murgai, J. Jain, M. Fujita","doi":"10.1109/ICVD.1999.745188","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745188","url":null,"abstract":"The most common way to build the reduced ordered binary decision diagram (ROBDD) of a complex gate (or function) f of a network is bottom-up, i.e., by first building the ROBDDs of the sub-expressions of f and then suitably combining them. Such a method, however, has been found to suffer from memory explosion, even when the ROBDD of f is not large. This leads to the following fundamental question: Given an arbitrary boolean expression f(x/sub 1/,x/sub 2/,...x/sub n/) and the ROBDDs of t/sub t/s (in terms of circuit inputs), how should the ROBDD of f be constructed so that the intermediate memory repaired to build the ROBDD is minimized, and a heavy time penalty is not incurred? In this paper, we address this question for a restricted f: a multi-way AND or OR operation. We propose various schemes for scheduling the binary operations of the expression f. These schemes are based on an analysis of the sizes and support-sets of the intermediate ROBDDs. One of our main contributions is to prove that under certain conditions, these schemes provide the optimum solution. We tested the proposed schemes on complex functions present within ISCAS85 as well as large industrial circuits. On average, our best scheme (which is based on size as well as support-set of the component ROBDDs) yields a 25% reduction in ROBDD sizes as compared to the technique implemented in SIS [1992]. In some cases. A reduction of up to 4 orders of magnitude was seen. Since ROBDDs are a key technology in various synthesis and verification tasks. Our work can be of immediate use in all these applications.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124599961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745139
A. Kountouris, C. Wolinski
Identifying operation mutual exclusiveness is important in order to improve the quality of high-level synthesis results, by reducing either the required number of control steps or the needed hardware resources by conditional resource sharing. To this end we propose the hierarchical conditional dependency graph representation and an algorithm for identification of mutually exclusive operations. A hierarchical control organization permits one to minimize the number of pair-wise exclusiveness tests during the identification process. Using graph transformations and reasoning on arithmetic inequalities, the proposed approach can produce results independent of description styles and identify more mutually exclusive operation pairs than previous approaches.
{"title":"Hierarchical conditional dependency graphs for mutual exclusiveness identification","authors":"A. Kountouris, C. Wolinski","doi":"10.1109/ICVD.1999.745139","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745139","url":null,"abstract":"Identifying operation mutual exclusiveness is important in order to improve the quality of high-level synthesis results, by reducing either the required number of control steps or the needed hardware resources by conditional resource sharing. To this end we propose the hierarchical conditional dependency graph representation and an algorithm for identification of mutually exclusive operations. A hierarchical control organization permits one to minimize the number of pair-wise exclusiveness tests during the identification process. Using graph transformations and reasoning on arithmetic inequalities, the proposed approach can produce results independent of description styles and identify more mutually exclusive operation pairs than previous approaches.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124816604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745204
Jue Wu, E. Rudnick
A new diagnostic fault simulator is described that diagnoses both feedback and non-feedback bridge faults while using information from fault simulation of single stuck-at faults. A realistic fault model is used which considers the existence of the Byzantine Generals Problem. The approach has been demonstrated for two-line bridge faults on several large combinational benchmark circuits and has achieved over 98% accuracy for non-feedback bridge faults and over 80% accuracy for feedback bridge faults with good diagnostic resolution.
{"title":"A diagnostic fault simulator for fast diagnosis of bridge faults","authors":"Jue Wu, E. Rudnick","doi":"10.1109/ICVD.1999.745204","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745204","url":null,"abstract":"A new diagnostic fault simulator is described that diagnoses both feedback and non-feedback bridge faults while using information from fault simulation of single stuck-at faults. A realistic fault model is used which considers the existence of the Byzantine Generals Problem. The approach has been demonstrated for two-line bridge faults on several large combinational benchmark circuits and has achieved over 98% accuracy for non-feedback bridge faults and over 80% accuracy for feedback bridge faults with good diagnostic resolution.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131936549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745161
Vishnu A. Patankar, Alok K. Jain, R. Bryant
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM processors, uses features such as a 5-stage instruction pipeline, predicated execution, forwarding logic and multi-cycle instructions. The instruction set of the processor was defined as a set of abstract assertions. An implementation mapping was used to relate the abstract states in these assertions to detailed circuit states in the gate-level implementation of the processor. Symbolic Trajectory Evaluation was used to verify that the circuit fulfills each abstract assertion under the implementation mapping. The verification was done concurrently with the design implementation of the processor. Our verification did uncover 4 bugs that were reported back to the designer.
{"title":"Formal verification of an ARM processor","authors":"Vishnu A. Patankar, Alok K. Jain, R. Bryant","doi":"10.1109/ICVD.1999.745161","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745161","url":null,"abstract":"This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM processors, uses features such as a 5-stage instruction pipeline, predicated execution, forwarding logic and multi-cycle instructions. The instruction set of the processor was defined as a set of abstract assertions. An implementation mapping was used to relate the abstract states in these assertions to detailed circuit states in the gate-level implementation of the processor. Symbolic Trajectory Evaluation was used to verify that the circuit fulfills each abstract assertion under the implementation mapping. The verification was done concurrently with the design implementation of the processor. Our verification did uncover 4 bugs that were reported back to the designer.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128834003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745183
P. Pan, Guohua Chen
Retiming is a transformation that optimizes a sequential circuit by relocating the registers. When the circuit has an initial state, one must compute an equivalent initial state for the retimed circuit. In this paper we propose a new efficient retiming algorithm for performance optimization. The retiming determined by the algorithm is the best with respect to initial state computation. It is the easiest retiming for finding an equivalent initial state, and if logic modification is required, it incurs the minimum amount of modification.
{"title":"Optimal retiming for initial state computation","authors":"P. Pan, Guohua Chen","doi":"10.1109/ICVD.1999.745183","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745183","url":null,"abstract":"Retiming is a transformation that optimizes a sequential circuit by relocating the registers. When the circuit has an initial state, one must compute an equivalent initial state for the retimed circuit. In this paper we propose a new efficient retiming algorithm for performance optimization. The retiming determined by the algorithm is the best with respect to initial state computation. It is the easiest retiming for finding an equivalent initial state, and if logic modification is required, it incurs the minimum amount of modification.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126724651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745158
Z. Kalbarczyk, J. Patel, Myeong S. Lee, R. Iyer
This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. The methodology spans the entire range of analysis from the device level to the system level. In this study we focus on two low levels of the simulation hierarchy-the device level and the circuit level. The primary fault model is obtained via simulation of the transistor-level effect of radiation particles penetrating the device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The resulting outputs are recorded in the fault dictionary and can be used to analyze the impact of transients at the higher simulation levels, i.e., the chip level and the system level. The study demonstrated that the proposed hierarchical fault injection methodology is able to precisely capture the generation of transients in digital devices and thus provides a basis for realistic system evaluation.
{"title":"An approach to evaluating the effects of realistic faults in digital circuits","authors":"Z. Kalbarczyk, J. Patel, Myeong S. Lee, R. Iyer","doi":"10.1109/ICVD.1999.745158","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745158","url":null,"abstract":"This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. The methodology spans the entire range of analysis from the device level to the system level. In this study we focus on two low levels of the simulation hierarchy-the device level and the circuit level. The primary fault model is obtained via simulation of the transistor-level effect of radiation particles penetrating the device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The resulting outputs are recorded in the fault dictionary and can be used to analyze the impact of transients at the higher simulation levels, i.e., the chip level and the system level. The study demonstrated that the proposed hierarchical fault injection methodology is able to precisely capture the generation of transients in digital devices and thus provides a basis for realistic system evaluation.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122963714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745206
S. Chakrabarti, Sandip Das, D. K. Das, B. Bhattacharya
A new technique of synthesizing symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit will be 100% robustly path-delay fault testable, if the constituent unate functions are synthesized with two-level irredundant circuits. Non-consecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The hardware overhead of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results reveal that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn reduces testing time as compared to those of the best known earlier methods.
{"title":"Synthesis of symmetric functions for path-delay fault testability","authors":"S. Chakrabarti, Sandip Das, D. K. Das, B. Bhattacharya","doi":"10.1109/ICVD.1999.745206","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745206","url":null,"abstract":"A new technique of synthesizing symmetric Boolean functions is presented that achieves complete robust path-delay fault testability. We show that every consecutive symmetric function can be expressed as a logical composition (e.g., AND, NOR) of two unate symmetric functions, and the resulting composite circuit will be 100% robustly path-delay fault testable, if the constituent unate functions are synthesized with two-level irredundant circuits. Non-consecutive symmetric functions can also be synthesized by decomposing them into a set of consecutive symmetric functions. The hardware overhead of the proposed design can further be reduced by a novel algebraic factorization technique based on some combinatorial clues. The overall synthesis guarantees complete robust path-delay fault testability, and can be completed in linear time. The results reveal that the proposed method ensures a significant reduction in hardware, as well as in the number of paths, which in turn reduces testing time as compared to those of the best known earlier methods.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121085576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745274
O. Narayan, J. Roychowdhury
We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components. An important feature of the WaMPDE is its ability to capture frequency modulation (FM) in a natural and compact manner. This is made possible by a key new concept: that of warped time, related to normal time through separate time scales. Using warped time, we obtain a completely general formulation that captures complex dynamics in autonomous nonlinear systems of arbitrary size or complexity. We present computationally efficient numerical methods for solving large practical problems using the WaMPDE. Our approach explicitly calculates a time-varying local frequency that matches intuitive expectations. Applications to voltage-controlled oscillators demonstrate speedups of two orders of magnitude.
{"title":"Analysing forced oscillators with multiple time scales","authors":"O. Narayan, J. Roychowdhury","doi":"10.1109/ICVD.1999.745274","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745274","url":null,"abstract":"We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components. An important feature of the WaMPDE is its ability to capture frequency modulation (FM) in a natural and compact manner. This is made possible by a key new concept: that of warped time, related to normal time through separate time scales. Using warped time, we obtain a completely general formulation that captures complex dynamics in autonomous nonlinear systems of arbitrary size or complexity. We present computationally efficient numerical methods for solving large practical problems using the WaMPDE. Our approach explicitly calculates a time-varying local frequency that matches intuitive expectations. Applications to voltage-controlled oscillators demonstrate speedups of two orders of magnitude.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745165
T. Arons, A. Pnueli
In this paper Tomasulo's algorithm for out-of-order execution is shown to be a refinement of the sequential instruction execution algorithm. Correctness of Tomasulo's algorithm is established by proving that the register files of Tomasulo's algorithm and the sequential algorithm agree once all instructions have been completed.
{"title":"Verifying Tomasulo's algorithm by refinement","authors":"T. Arons, A. Pnueli","doi":"10.1109/ICVD.1999.745165","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745165","url":null,"abstract":"In this paper Tomasulo's algorithm for out-of-order execution is shown to be a refinement of the sequential instruction execution algorithm. Correctness of Tomasulo's algorithm is established by proving that the register files of Tomasulo's algorithm and the sequential algorithm agree once all instructions have been completed.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114495335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745152
P. Chakrabarti, P. Dasgupta, P. Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose
Static simulation is a method to compile event driven simulations into a single composite state machine. Code generated based on this does not require the event management overheads of an event driven simulator resulting in significant speedup on this overhead. In this paper we present an implementation of static simulation, highlight the problems of pure static unfolding and suggest methods to control the possibility of state explosion. Specific methods suggested include special schemes for handling lumped delays, selective tracking, unclocking of individual blocks and partial composition.
{"title":"Controlling state explosion in static simulation by selective composition","authors":"P. Chakrabarti, P. Dasgupta, P. Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose","doi":"10.1109/ICVD.1999.745152","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745152","url":null,"abstract":"Static simulation is a method to compile event driven simulations into a single composite state machine. Code generated based on this does not require the event management overheads of an event driven simulator resulting in significant speedup on this overhead. In this paper we present an implementation of static simulation, highlight the problems of pure static unfolding and suggest methods to control the possibility of state explosion. Specific methods suggested include special schemes for handling lumped delays, selective tracking, unclocking of individual blocks and partial composition.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115860941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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