Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745187
Chitrasena Bhat, N. Chiplunkar
One of the main objective in the process of mapping a circuit onto a look-Up Table (LUT) based FPGA is to minimize the number of LUTs required to implement the circuit. A new top-down technology mapper algorithm is discussed in this paper which aims at minimizing number of LUTs needed for mapping the digital circuit. The algorithm makes use of combination of node selection and covering heuristics using which maximum number of DAG nodes are covered by a selected LUT. The results obtained are better than Chortle, Level-map and Flow-map-r technology mapper algorithms.
{"title":"Heuristic technology mapper for LUT based FPGAs","authors":"Chitrasena Bhat, N. Chiplunkar","doi":"10.1109/ICVD.1999.745187","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745187","url":null,"abstract":"One of the main objective in the process of mapping a circuit onto a look-Up Table (LUT) based FPGA is to minimize the number of LUTs required to implement the circuit. A new top-down technology mapper algorithm is discussed in this paper which aims at minimizing number of LUTs needed for mapping the digital circuit. The algorithm makes use of combination of node selection and covering heuristics using which maximum number of DAG nodes are covered by a selected LUT. The results obtained are better than Chortle, Level-map and Flow-map-r technology mapper algorithms.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130920761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745127
Y. Higami, K. Saluja, K. Kinoshita
In IDDQ testing, long testing time is one of the significant problems, because IDDQ measurement is a time consuming process. In order to reduce the testing time, it is important do reduce the number of IDDQ observation vectors rather than the number of total test vectors. In this paper we, propose efficient techniques to select small number of IDDQ observation vectors. The proposed techniques are use of a concept of essential vectors and concurrent fault simulation. Experimental results for ISCAS '89 benchmark circuits show that the proposed technique reduces the number of IDDQ observation vectors with short computational time.
{"title":"Efficient techniques for reducing IDDQ observation time for sequential circuits","authors":"Y. Higami, K. Saluja, K. Kinoshita","doi":"10.1109/ICVD.1999.745127","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745127","url":null,"abstract":"In IDDQ testing, long testing time is one of the significant problems, because IDDQ measurement is a time consuming process. In order to reduce the testing time, it is important do reduce the number of IDDQ observation vectors rather than the number of total test vectors. In this paper we, propose efficient techniques to select small number of IDDQ observation vectors. The proposed techniques are use of a concept of essential vectors and concurrent fault simulation. Experimental results for ISCAS '89 benchmark circuits show that the proposed technique reduces the number of IDDQ observation vectors with short computational time.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131014372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745159
D. Das, N. Touba
An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for rapidly testing the interconnect in the FPGAs each time the system is reconfigured. A low-cost configuration-dependent test method is used to both detect and locate faults in the interconnect. The "original configuration" is modified by only changing the logic function of the CLBs to form "test configurations" that can be used to quickly test the interconnect using the "walking-1" approach. The test procedure is rapid enough to be performed on the fly whenever the system is reconfigured. All stuck-at faults and bridging faults in the interconnect are guaranteed to be detected and located with a short test length. The fault location information can he used to reconfigure the system to avoid the faulty hardware.
{"title":"A low cost approach for detecting, locating, and avoiding interconnect faults in FPGA-based reconfigurable systems","authors":"D. Das, N. Touba","doi":"10.1109/ICVD.1999.745159","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745159","url":null,"abstract":"An FPGA-based reconfigurable system may contain boards of FPGAs which are reconfigured for different applications and must work correctly. This paper presents a novel approach for rapidly testing the interconnect in the FPGAs each time the system is reconfigured. A low-cost configuration-dependent test method is used to both detect and locate faults in the interconnect. The \"original configuration\" is modified by only changing the logic function of the CLBs to form \"test configurations\" that can be used to quickly test the interconnect using the \"walking-1\" approach. The test procedure is rapid enough to be performed on the fly whenever the system is reconfigured. All stuck-at faults and bridging faults in the interconnect are guaranteed to be detected and located with a short test length. The fault location information can he used to reconfigure the system to avoid the faulty hardware.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132377106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745153
Rathish Jayabharathi, M. d'Abreu, J. Abraham
Chip performance and density are increasing tremendously and the CAD tools are always lagging behind. In this paper, we introduce a functional timing verifier using a novel fuzzy delay model which bridges the gap between the front-end timing verification and the back-end delay fault testing. The proposed fuzzy delay model can handle uncertainties with respect to timing characteristics, and manufacturing anomalies. Experimental results are presented for the ISCAS-85 benchmark circuits.
{"title":"FzCRITIC-a functional timing verifier using a novel fuzzy delay model","authors":"Rathish Jayabharathi, M. d'Abreu, J. Abraham","doi":"10.1109/ICVD.1999.745153","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745153","url":null,"abstract":"Chip performance and density are increasing tremendously and the CAD tools are always lagging behind. In this paper, we introduce a functional timing verifier using a novel fuzzy delay model which bridges the gap between the front-end timing verification and the back-end delay fault testing. The proposed fuzzy delay model can handle uncertainties with respect to timing characteristics, and manufacturing anomalies. Experimental results are presented for the ISCAS-85 benchmark circuits.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114342556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745121
P. Flores, José C. Costa, H. Neto, J. Monteiro, Joao Marques-Silva
For a significant number of electronic systems used in safety-critical applications circuit testing is performed periodically. For these systems, power dissipation due to Built-in Self Test (BIST) can represent a significant percentage of the overall power dissipation. One approach to minimize power consumption in these systems consists of test pattern sequence reordering. Moreover a key observation is that test patterns are in general expected to exhibit don't cares, which can naturally be exploited during test pattern sequence reordering. In this paper we develop an optimization model and describe an efficient algorithm for reordering pattern sequences in the presence of don't cares. Preliminary experimental results amply confirm that the resulting power savings due to pattern sequence reordering using don't cares can be significant.
{"title":"Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation","authors":"P. Flores, José C. Costa, H. Neto, J. Monteiro, Joao Marques-Silva","doi":"10.1109/ICVD.1999.745121","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745121","url":null,"abstract":"For a significant number of electronic systems used in safety-critical applications circuit testing is performed periodically. For these systems, power dissipation due to Built-in Self Test (BIST) can represent a significant percentage of the overall power dissipation. One approach to minimize power consumption in these systems consists of test pattern sequence reordering. Moreover a key observation is that test patterns are in general expected to exhibit don't cares, which can naturally be exploited during test pattern sequence reordering. In this paper we develop an optimization model and describe an efficient algorithm for reordering pattern sequences in the presence of don't cares. Preliminary experimental results amply confirm that the resulting power savings due to pattern sequence reordering using don't cares can be significant.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114318885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745149
S. Khatri, R. Brayton, A. Sangiovanni-Vincentelli
We introduce a scheme to simplify a multi-valued network using redundancy removal techniques. Recent methods for binary redundancy removal avoid the use of state traversal. Additionally, one method finds multiple compatible redundancies simultaneously. We extend these powerful advances in the field of binary redundancy removal to perform redundancy removal for multi-valued networks. First we perform a one-hot encoding of all the multi-valued variables of the design. Multi-valued variables are written out as binary variables, using this one-hot encoding. At the end of this step, we have a binary network which is equivalent to the multi-valued network module encoding. Next binary redundancy removal is invoked on the resulting network. In the case a binary signal s/sub i/ is determined to be stuck-at-0 redundant this means that the multi-valued signal s can never take on a value i. Further if the binary signal s/sub i/ is determined to be stuck-at-1 redundant, this means that the multi-valued signal s takes on a constant value i. All redundant binary signals are recorded in a file. The original multi-valued network is modified based on the binary redundancies thus computed. Initial experiments using this technique show a 10-20% reduction in the size of the multi-valued description.
{"title":"Sequential multi-valued network simplification using redundancy removal","authors":"S. Khatri, R. Brayton, A. Sangiovanni-Vincentelli","doi":"10.1109/ICVD.1999.745149","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745149","url":null,"abstract":"We introduce a scheme to simplify a multi-valued network using redundancy removal techniques. Recent methods for binary redundancy removal avoid the use of state traversal. Additionally, one method finds multiple compatible redundancies simultaneously. We extend these powerful advances in the field of binary redundancy removal to perform redundancy removal for multi-valued networks. First we perform a one-hot encoding of all the multi-valued variables of the design. Multi-valued variables are written out as binary variables, using this one-hot encoding. At the end of this step, we have a binary network which is equivalent to the multi-valued network module encoding. Next binary redundancy removal is invoked on the resulting network. In the case a binary signal s/sub i/ is determined to be stuck-at-0 redundant this means that the multi-valued signal s can never take on a value i. Further if the binary signal s/sub i/ is determined to be stuck-at-1 redundant, this means that the multi-valued signal s takes on a constant value i. All redundant binary signals are recorded in a file. The original multi-valued network is modified based on the binary redundancies thus computed. Initial experiments using this technique show a 10-20% reduction in the size of the multi-valued description.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"52 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132757588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745192
P. Prabhakaran, P. Banerjee, Jim E. Crenshaw, M. Sarrafzadeh
Interconnect power dissipation is becoming a major component of power consumption in a circuit especially in sub-micron technologies. The energy dissipated by a particular interconnection link is determined by the switching activity on that link and also on its capacitance. The switching activity is determined by the schedule and binding, whereas the capacitance is determined by the floorplan. Scheduling, binding and floorplanning are closely inter-related. A simultaneous scheduling, binding and floorplanning algorithm is presented which attempts to minimize interconnect energy dissipation. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower power, latency and area. We show that it is possible to reduce the interconnect energy dissipation by upto around 60 percent for high-level synthesis benchmark circuits.
{"title":"Simultaneous scheduling, binding and floorplanning for interconnect power optimization","authors":"P. Prabhakaran, P. Banerjee, Jim E. Crenshaw, M. Sarrafzadeh","doi":"10.1109/ICVD.1999.745192","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745192","url":null,"abstract":"Interconnect power dissipation is becoming a major component of power consumption in a circuit especially in sub-micron technologies. The energy dissipated by a particular interconnection link is determined by the switching activity on that link and also on its capacitance. The switching activity is determined by the schedule and binding, whereas the capacitance is determined by the floorplan. Scheduling, binding and floorplanning are closely inter-related. A simultaneous scheduling, binding and floorplanning algorithm is presented which attempts to minimize interconnect energy dissipation. In comparison to a traditional approach which separates high-level synthesis from physical design, our algorithm is able to make these stages interact very closely, resulting in solutions with lower power, latency and area. We show that it is possible to reduce the interconnect energy dissipation by upto around 60 percent for high-level synthesis benchmark circuits.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123421914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745205
Shashank K. Mehta, S. Seth
Among significant components of testing cost are test-length, reject ratio, and lost-yield. In this paper a new approach is proposed to estimate the reject ratio. The empirical model is based on test-data properties that are believed to be invariant for a wide range of manufacturing technologies and types of tests. The analysis is carried out entirely in terms of the device test data, as might be available from a wafer probe. Experimental results demonstrate the robustness of the model.
{"title":"Empirical computation of reject ratio in VLSI testing","authors":"Shashank K. Mehta, S. Seth","doi":"10.1109/ICVD.1999.745205","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745205","url":null,"abstract":"Among significant components of testing cost are test-length, reject ratio, and lost-yield. In this paper a new approach is proposed to estimate the reject ratio. The empirical model is based on test-data properties that are believed to be invariant for a wide range of manufacturing technologies and types of tests. The analysis is carried out entirely in terms of the device test data, as might be available from a wafer probe. Experimental results demonstrate the robustness of the model.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127425223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745216
Gi-Joon Nam, K. Sakallah, Rob A. Rutenbar
In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulation methods can prove the unroutability of a given circuit, which is a clear advantage over classical net-at-a-time approaches. Previous attempts at FPGA routing using Boolean methods were based on Binary Decision Diagrams (BDDs) which limited their scope to small FPGAs. In this paper we employ an efficient search-based Boolean satisfiability approach to solve the routing problem and show that such an approach extends the range of Boolean methods to larger FPGAs. Furthermore, we show the possibility that more relaxed formulations of the routing constraints, allowing higher degrees of freedom for net routing, can be easily accommodated. Preliminary experimental results suggest that our approach is quite viable for FPGAs of practical size.
{"title":"Satisfiability-based detailed FPGA routing","authors":"Gi-Joon Nam, K. Sakallah, Rob A. Rutenbar","doi":"10.1109/ICVD.1999.745216","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745216","url":null,"abstract":"In this paper we address the problem of detailed FPGA routing using Boolean formulation methods. In the context of FPGA routing where routing resources are fixed, Boolean formulation methods can prove the unroutability of a given circuit, which is a clear advantage over classical net-at-a-time approaches. Previous attempts at FPGA routing using Boolean methods were based on Binary Decision Diagrams (BDDs) which limited their scope to small FPGAs. In this paper we employ an efficient search-based Boolean satisfiability approach to solve the routing problem and show that such an approach extends the range of Boolean methods to larger FPGAs. Furthermore, we show the possibility that more relaxed formulations of the routing constraints, allowing higher degrees of freedom for net routing, can be easily accommodated. Preliminary experimental results suggest that our approach is quite viable for FPGAs of practical size.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120901758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745148
R. Brayton, S. Khatri
We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.
{"title":"Multi-valued logic synthesis","authors":"R. Brayton, S. Khatri","doi":"10.1109/ICVD.1999.745148","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745148","url":null,"abstract":"We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128164814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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