Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745215
Jayadeva
Recent developments have aroused the interest of researchers in the application of chaotic neural networks to combinatorial optimization problems. In this paper, we introduce a new approach, which is termed Sequential Chaotic Annealing. The approach combines chaotic neural networks and ideas from the theory of nonlinear optimization. The proposed neural networks are adaptive in the sense that the network "learns" the right cost or energy function to optimize. Sequential Chaotic Annealing is applied to multilayer channel routing using the reserved wiring model and restricted doglegging. We show that the proposed approach improves convergence to valid solutions and reduces the sensitivity to the initial states of the neurons.
{"title":"Sequential chaotic annealing and its application to multilayer channel routing","authors":"Jayadeva","doi":"10.1109/ICVD.1999.745215","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745215","url":null,"abstract":"Recent developments have aroused the interest of researchers in the application of chaotic neural networks to combinatorial optimization problems. In this paper, we introduce a new approach, which is termed Sequential Chaotic Annealing. The approach combines chaotic neural networks and ideas from the theory of nonlinear optimization. The proposed neural networks are adaptive in the sense that the network \"learns\" the right cost or energy function to optimize. Sequential Chaotic Annealing is applied to multilayer channel routing using the reserved wiring model and restricted doglegging. We show that the proposed approach improves convergence to valid solutions and reduces the sensitivity to the initial states of the neurons.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132600048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745156
I. Pomeranz, S. Reddy
Static test compaction procedures for synchronous sequential circuits may saturate and be unable to further reduce the test sequence length before the test length reaches its minimum value, resulting in test sequences that may be longer than necessary. We propose a method to take a static compaction procedure out of saturation and allow it to continue reducing the test sequence length. The proposed method is based on the replacement of test vectors in the test sequence every time the compaction procedure reaches saturation. Test vector replacement is done such that the fault coverage of the sequence is maintained. After one or more test vectors are replaced, the test sequence is different from the one obtained after the compaction procedure saturated, and the compaction procedure can be applied to further reduce the test length. Experimental results with an effective static compaction procedure demonstrate that reductions in test length can be obtained by the proposed vector replacement method.
{"title":"VERSE: a vector replacement procedure for improving test compaction in synchronous sequential circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ICVD.1999.745156","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745156","url":null,"abstract":"Static test compaction procedures for synchronous sequential circuits may saturate and be unable to further reduce the test sequence length before the test length reaches its minimum value, resulting in test sequences that may be longer than necessary. We propose a method to take a static compaction procedure out of saturation and allow it to continue reducing the test sequence length. The proposed method is based on the replacement of test vectors in the test sequence every time the compaction procedure reaches saturation. Test vector replacement is done such that the fault coverage of the sequence is maintained. After one or more test vectors are replaced, the test sequence is different from the one obtained after the compaction procedure saturated, and the compaction procedure can be applied to further reduce the test length. Experimental results with an effective static compaction procedure demonstrate that reductions in test length can be obtained by the proposed vector replacement method.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124651407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745130
S. Zachariah, S. Chakravarty
Pseudo stuck-at is a popular model, used by many commercial tool vendors, for evaluating and selecting I/sub DDQ/ tests. We show that pseudo stuck-at fault coverage numbers are very pessimistic, and equally good vectors can be selected much faster using the leakage fault model. This, and the fact that a fast simulation algorithm exists for leakage faults, prompts us to propose the use of the leakage fault model.
{"title":"A comparative study of pseudo stuck-at and leakage fault model","authors":"S. Zachariah, S. Chakravarty","doi":"10.1109/ICVD.1999.745130","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745130","url":null,"abstract":"Pseudo stuck-at is a popular model, used by many commercial tool vendors, for evaluating and selecting I/sub DDQ/ tests. We show that pseudo stuck-at fault coverage numbers are very pessimistic, and equally good vectors can be selected much faster using the leakage fault model. This, and the fact that a fast simulation algorithm exists for leakage faults, prompts us to propose the use of the leakage fault model.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126122307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-07DOI: 10.1109/ICVD.1999.745207
S. Chakrabarti, A. Chatterjee
In this paper we propose a novel fault-based transient test generation methodology for locating faults in hierarchical nonlinear analog circuits. A heuristic optimization algorithm generates test stimuli that can distinguish fault-effects based on voltage measurements at observable circuit nodes. hierarchical fault dictionaries are generated for the purpose of fault location. The cost of simulation during dictionary construction is significantly reduced as the proposed method uses hierarchical behavioral modeling of circuits and fault dropping techniques. The proposed algorithms can also be used to generate tests for fault detection. A complete diagnostic test generation system has been implemented and tested successfully.
{"title":"Diagnostic test pattern generation for analog circuits using hierarchical models","authors":"S. Chakrabarti, A. Chatterjee","doi":"10.1109/ICVD.1999.745207","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745207","url":null,"abstract":"In this paper we propose a novel fault-based transient test generation methodology for locating faults in hierarchical nonlinear analog circuits. A heuristic optimization algorithm generates test stimuli that can distinguish fault-effects based on voltage measurements at observable circuit nodes. hierarchical fault dictionaries are generated for the purpose of fault location. The cost of simulation during dictionary construction is significantly reduced as the proposed method uses hierarchical behavioral modeling of circuits and fault dropping techniques. The proposed algorithms can also be used to generate tests for fault detection. A complete diagnostic test generation system has been implemented and tested successfully.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123353202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-07DOI: 10.1109/ICVD.1999.745116
Nagaraj Ns, P. Balsara, C. Cantrell
Dominance of interconnect parasitics in impacting functionality, performance and reliability in deep sub-micron (DSM) designs is a well known topic. Reduced metal pitches, process variations, new materials for metallization/dielectrics emphasizes an increased need for "accurate" technology modeling of interconnect. In the mean time, continued design integration, increased chip sizes and market pressures call for faster but "accurate" EDA methodologies and tools. This tutorial provides a complete perspective of the TCAD interconnect modeling issues and how these could be addressed in ECAD methodologies and tools.
{"title":"Bridging the gap between TCAD and ECAD methodologies in deep sub-micron interconnect extraction and analysis","authors":"Nagaraj Ns, P. Balsara, C. Cantrell","doi":"10.1109/ICVD.1999.745116","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745116","url":null,"abstract":"Dominance of interconnect parasitics in impacting functionality, performance and reliability in deep sub-micron (DSM) designs is a well known topic. Reduced metal pitches, process variations, new materials for metallization/dielectrics emphasizes an increased need for \"accurate\" technology modeling of interconnect. In the mean time, continued design integration, increased chip sizes and market pressures call for faster but \"accurate\" EDA methodologies and tools. This tutorial provides a complete perspective of the TCAD interconnect modeling issues and how these could be addressed in ECAD methodologies and tools.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"333 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115980401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-07DOI: 10.1109/ICVD.1999.745141
M. Khaira
Can you imagine working on a PC powered by a processor with 100 BIPS (Billion Instructions Per Sec) of performance? Is a processor with 1 Billion transistors a reality? This talk describes what the Micro-2010 will be like and identifies the challenges involved in its design. We expect all aspects of life to be impacted by Micro-2010. Applications like tele-presence, augmented reality, and reality animation indicate that such microprocessor performance will be a critical enabling technology. This talk makes an attempt to describe the characteristic features of the microprocessors of 2010, and identifies the challenges involved in their design and test. Micro-2010 will run at a frequency in excess of 4 gigaHertz. Getting to that level of performance while meeting the power budget (<100 Watts) and area budget (<$500 cost) will require breakthroughs in circuit design methodologies, CAD tools and technologies, and process technology. If current design methodology trends continue, designing Micro-2010 will require every single VLSI design engineer graduating after 2005 to be hired into the team designing it! This implies that major breakthroughs in design methodology, enabled by a new generation of CAD tools, is essential for these designs to become a reality. The semiconductor process in 2010 will have a minimum feature size less than 0.1 micron and the transistors a gate oxide of the thickness of less than the height of 10 layers of silicon dioxide molecules. These dimensions are smaller than the wavelength of visible light and will require major breakthroughs in process technology. Given the expected volume of shipment of Micro-2010, an errata like the FDIV cannot be tolerated without severe financial ramifications. Avoiding errata in a 1 Billion Transistor design is practically impossible. The talk will identify specific research directions in the areas of design and CAD tools to meet the challenges of design of the Micro-2010 and propose potential solutions.
{"title":"Micro-2010: lead performance microprocessor of the year 2010-myth or reality?","authors":"M. Khaira","doi":"10.1109/ICVD.1999.745141","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745141","url":null,"abstract":"Can you imagine working on a PC powered by a processor with 100 BIPS (Billion Instructions Per Sec) of performance? Is a processor with 1 Billion transistors a reality? This talk describes what the Micro-2010 will be like and identifies the challenges involved in its design. We expect all aspects of life to be impacted by Micro-2010. Applications like tele-presence, augmented reality, and reality animation indicate that such microprocessor performance will be a critical enabling technology. This talk makes an attempt to describe the characteristic features of the microprocessors of 2010, and identifies the challenges involved in their design and test. Micro-2010 will run at a frequency in excess of 4 gigaHertz. Getting to that level of performance while meeting the power budget (<100 Watts) and area budget (<$500 cost) will require breakthroughs in circuit design methodologies, CAD tools and technologies, and process technology. If current design methodology trends continue, designing Micro-2010 will require every single VLSI design engineer graduating after 2005 to be hired into the team designing it! This implies that major breakthroughs in design methodology, enabled by a new generation of CAD tools, is essential for these designs to become a reality. The semiconductor process in 2010 will have a minimum feature size less than 0.1 micron and the transistors a gate oxide of the thickness of less than the height of 10 layers of silicon dioxide molecules. These dimensions are smaller than the wavelength of visible light and will require major breakthroughs in process technology. Given the expected volume of shipment of Micro-2010, an errata like the FDIV cannot be tolerated without severe financial ramifications. Avoiding errata in a 1 Billion Transistor design is practically impossible. The talk will identify specific research directions in the areas of design and CAD tools to meet the challenges of design of the Micro-2010 and propose potential solutions.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115574002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-07DOI: 10.1109/ICVD.1999.745193
M. Stan
We provide analytical "back of the envelope" calculations for the choice of optimal supply and threshold voltages and sizing for minimum energy-delay product. Based on such calculations we then show that a circuit design style with separate logic and buffer stages offers a better energy-delay product in the presence of interconnect parasitics.
{"title":"Optimal voltages and sizing for low power [CMOS VLSI]","authors":"M. Stan","doi":"10.1109/ICVD.1999.745193","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745193","url":null,"abstract":"We provide analytical \"back of the envelope\" calculations for the choice of optimal supply and threshold voltages and sizing for minimum energy-delay product. Based on such calculations we then show that a circuit design style with separate logic and buffer stages offers a better energy-delay product in the presence of interconnect parasitics.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"402 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115318087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-07DOI: 10.1109/ICVD.1999.745223
B. Pandita, S. Roy
This paper describes the design at implementation of Viterbi decoder using FPGAs. In this paper we explore an FPGA based implementation methodology for rapidly prototyping designs. We use high level synthesis to achieve this. Some of the implementation issues related to the Viterbi decoder such as organization of path memory, decision memory reading techniques, and the clocking mechanism have been discussed.
{"title":"Design and implementation of a Viterbi decoder using FPGAs","authors":"B. Pandita, S. Roy","doi":"10.1109/ICVD.1999.745223","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745223","url":null,"abstract":"This paper describes the design at implementation of Viterbi decoder using FPGAs. In this paper we explore an FPGA based implementation methodology for rapidly prototyping designs. We use high level synthesis to achieve this. Some of the implementation issues related to the Viterbi decoder such as organization of path memory, decision memory reading techniques, and the clocking mechanism have been discussed.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127822627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-07DOI: 10.1109/ICVD.1999.745132
A. Kahng
We assess the prospects for new tools and flows in the interface between layout design and manufacturability. We begin with a review of classic elements of this interface, then focus on more recently critical issues: (i) layout design for reduced CMP variability; (ii) layout design for PSM; and (iii) layout design for OPC. Our discussion highlights the many ways in which layout affords effective means of optimizing manufacturability, as well as opportunities for research and development.
{"title":"IC layout and manufacturability: critical links and design flow implications","authors":"A. Kahng","doi":"10.1109/ICVD.1999.745132","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745132","url":null,"abstract":"We assess the prospects for new tools and flows in the interface between layout design and manufacturability. We begin with a review of classic elements of this interface, then focus on more recently critical issues: (i) layout design for reduced CMP variability; (ii) layout design for PSM; and (iii) layout design for OPC. Our discussion highlights the many ways in which layout affords effective means of optimizing manufacturability, as well as opportunities for research and development.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129991651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-07DOI: 10.1109/ICVD.1999.745128
R. D. Blanton
The quality of CMOS circuits can be increased by performing I/sub DDQ/ testing. For regular circuits constructed from identical modules, defects localized to a single module detectable by current testing can be sensitized by exhaustively applying all input patterns to each circuit module. Regular circuits for which every module in arbitrarily large circuit can have all input patterns applied are defined to be I/sub DDQ/-testable. The I/sub DDQ/-testing properties of a class of regular circuits called tress are investigated. We present the conditions for one-dimensional and tree array circuits to be I/sub DDQ/-testable. We also present conditions for these circuits to be CI/sub DDQ/-testable, that is, I/sub DDQ/-testable with a constant number of tests independent of the circuit's size. Practical circuits such as comparators and carry-lookahead adders are used to illustrate the derived conditions.
{"title":"I/sub DDQ/-testability of tree circuits","authors":"R. D. Blanton","doi":"10.1109/ICVD.1999.745128","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745128","url":null,"abstract":"The quality of CMOS circuits can be increased by performing I/sub DDQ/ testing. For regular circuits constructed from identical modules, defects localized to a single module detectable by current testing can be sensitized by exhaustively applying all input patterns to each circuit module. Regular circuits for which every module in arbitrarily large circuit can have all input patterns applied are defined to be I/sub DDQ/-testable. The I/sub DDQ/-testing properties of a class of regular circuits called tress are investigated. We present the conditions for one-dimensional and tree array circuits to be I/sub DDQ/-testable. We also present conditions for these circuits to be CI/sub DDQ/-testable, that is, I/sub DDQ/-testable with a constant number of tests independent of the circuit's size. Practical circuits such as comparators and carry-lookahead adders are used to illustrate the derived conditions.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122481943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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