Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745194
V. Agrawal, M. Bushnell, G. Parthasarathy, R. Ramadoss
This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized when every gate has no more than one output transition per clock cycle. This condition is achieved for a gate when the gate delay equals or exceeds the maximum difference between path delays at gate inputs. In practice, path delays are adjusted either by increasing gate delays or by inserting delay buffers. The minimum transient energy design is obtained when no delay buffer is added. This design requires possible increases in gate delays to meet the minimum energy condition at all gates. However, the delay of the critical path may be increased. In an alternative design, where the critical path delay is not allowed to increase, delay buffers may have to be added. The theory in this paper allows trade-offs between minimum transient energy and critical path delay. We formulate the problem as a linear program to obtain the minimum transient energy design with the smallest number of delay buffers for a given overall delay of the circuit. An optimized four-bit ALU circuit is found to consume 53% peak and 73% average power compared to the original circuit.
{"title":"Digital circuit design for minimum transient energy and a linear programming method","authors":"V. Agrawal, M. Bushnell, G. Parthasarathy, R. Ramadoss","doi":"10.1109/ICVD.1999.745194","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745194","url":null,"abstract":"This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized when every gate has no more than one output transition per clock cycle. This condition is achieved for a gate when the gate delay equals or exceeds the maximum difference between path delays at gate inputs. In practice, path delays are adjusted either by increasing gate delays or by inserting delay buffers. The minimum transient energy design is obtained when no delay buffer is added. This design requires possible increases in gate delays to meet the minimum energy condition at all gates. However, the delay of the critical path may be increased. In an alternative design, where the critical path delay is not allowed to increase, delay buffers may have to be added. The theory in this paper allows trade-offs between minimum transient energy and critical path delay. We formulate the problem as a linear program to obtain the minimum transient energy design with the smallest number of delay buffers for a given overall delay of the circuit. An optimized four-bit ALU circuit is found to consume 53% peak and 73% average power compared to the original circuit.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128790443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745146
Robert A. Thacker, W. Belluomini, C. Myers
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification. This information is used throughout the synthesis procedure to optimize the design. In order to synthesize a timed circuit, it is necessary to explore the timed state space of the specification. The memory required to store the timed state space of a complex specification can be prohibitive for large designs when explicit representation methods are used. This paper describes the application of BDDs and MTBDDs to the representation of timed state spaces and the synthesis of timed circuits. These implicit techniques significantly improve the memory efficiency of timed state space exploration and allow more complex designs to be synthesized. Implicit methods also allow the derivation of solution spaces containing all valid solutions to the synthesis problem facilitating subsequent optimization and technology mapping steps.
{"title":"Timed circuit synthesis using implicit methods","authors":"Robert A. Thacker, W. Belluomini, C. Myers","doi":"10.1109/ICVD.1999.745146","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745146","url":null,"abstract":"The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification. This information is used throughout the synthesis procedure to optimize the design. In order to synthesize a timed circuit, it is necessary to explore the timed state space of the specification. The memory required to store the timed state space of a complex specification can be prohibitive for large designs when explicit representation methods are used. This paper describes the application of BDDs and MTBDDs to the representation of timed state spaces and the synthesis of timed circuits. These implicit techniques significantly improve the memory efficiency of timed state space exploration and allow more complex designs to be synthesized. Implicit methods also allow the derivation of solution spaces containing all valid solutions to the synthesis problem facilitating subsequent optimization and technology mapping steps.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115800924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745164
N. Utamaphethai, R. D. Blanton, John Paul Shen
We describe a rigorous ATPG-like methodology for validating the branch prediction mechanism of the PowerPC604 which can be easily generalized and made applicable to other processors. Test sequences based on finite state machine (FSM) testing are derived from small FSM-like models of the branch prediction mechanism. These sequences are translated into PowerPC instruction sequences. Simulation results show that 100% coverage of the targeted functionality is achieved using a very small number of simulation cycles. Simulation of some real programs against the same targeted functionality produces coverages that range between 34% and 75% with four orders of magnitude more cycles. We also use mutation analysis to modify some functionality of the behavioral model to further illustrate the effectiveness of our generated sequence. Simulation results show that all 54 mutants in the branch prediction functionality can be detected by measuring transition coverage.
{"title":"Superscalar processor validation at the microarchitecture level","authors":"N. Utamaphethai, R. D. Blanton, John Paul Shen","doi":"10.1109/ICVD.1999.745164","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745164","url":null,"abstract":"We describe a rigorous ATPG-like methodology for validating the branch prediction mechanism of the PowerPC604 which can be easily generalized and made applicable to other processors. Test sequences based on finite state machine (FSM) testing are derived from small FSM-like models of the branch prediction mechanism. These sequences are translated into PowerPC instruction sequences. Simulation results show that 100% coverage of the targeted functionality is achieved using a very small number of simulation cycles. Simulation of some real programs against the same targeted functionality produces coverages that range between 34% and 75% with four orders of magnitude more cycles. We also use mutation analysis to modify some functionality of the behavioral model to further illustrate the effectiveness of our generated sequence. Simulation results show that all 54 mutants in the branch prediction functionality can be detected by measuring transition coverage.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114574166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745150
Shugang Wei, K. Shimizu
Residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, (-2,-1,0,1,2) and (-3,-2,-1,0,1,2,3), are introduced. The former is used for the input and output, and the latter for the inner arithmetic circuit of the presented multiplier. So that, by using integers 4/sup P/ and 4/sup P//spl plusmn/1 as moduli of residue number system (RNS), where p is a positive integer, both the partial product generating circuit and the circuit for sum of the partial products in the multiplier can be efficiently constructed based on the SD number representations. The module m addition, m=4/sup P/ or m=4/sup P//spl plusmn/1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary modulo m SD adder tree based on the multiple-valued addition circuits, and consequently the module m multiplication is performed in O(log/sub 2/p) time.
{"title":"Residue arithmetic multiplier based on the radix-4 signed-digit multiple-valued arithmetic circuits","authors":"Shugang Wei, K. Shimizu","doi":"10.1109/ICVD.1999.745150","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745150","url":null,"abstract":"Residue arithmetic multiplier based on the radix-4 signed-digit arithmetic is presented. Conventional residue arithmetic circuits have been designed using binary number arithmetic system, but the carry propagation arises which limits the speed of arithmetic operations in residue modules. In this paper, two radix-4 signed-digit (SD) number representations, (-2,-1,0,1,2) and (-3,-2,-1,0,1,2,3), are introduced. The former is used for the input and output, and the latter for the inner arithmetic circuit of the presented multiplier. So that, by using integers 4/sup P/ and 4/sup P//spl plusmn/1 as moduli of residue number system (RNS), where p is a positive integer, both the partial product generating circuit and the circuit for sum of the partial products in the multiplier can be efficiently constructed based on the SD number representations. The module m addition, m=4/sup P/ or m=4/sup P//spl plusmn/1, can be performed by an SD adder or an end-around-carry SD adder with the multiple-valued circuits and the addition time is independent of the word length of operands. The modulo m multiplier can be compactly constructed using a binary modulo m SD adder tree based on the multiple-valued addition circuits, and consequently the module m multiplication is performed in O(log/sub 2/p) time.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114586692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745129
M. Jamoussi
In this paper, a new M-testability approach is presented as a further development of C-testability concept (limited to regular iterative arrays) to cope with more general arrays (i.e. of non-identical cells). M-testability is proposed based on a developed Classified-Level Approach (CLA), applied to the interconnected cells as a first step toward their test-vector prediction, under the assumption of at most one-faulty cell. The test-vector prediction is conducted on each of the defined cell classes. Using an elaborated Variable Testability Measure (VTM), the number of test vectors are predicted for each cell, then for the entire array. Applicable regardless of the fault type, M-tetability is experimented on various iterative arrays and generated results are debated.
{"title":"Test-vector prediction of M-testable iterative arrays","authors":"M. Jamoussi","doi":"10.1109/ICVD.1999.745129","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745129","url":null,"abstract":"In this paper, a new M-testability approach is presented as a further development of C-testability concept (limited to regular iterative arrays) to cope with more general arrays (i.e. of non-identical cells). M-testability is proposed based on a developed Classified-Level Approach (CLA), applied to the interconnected cells as a first step toward their test-vector prediction, under the assumption of at most one-faulty cell. The test-vector prediction is conducted on each of the defined cell classes. Using an elaborated Variable Testability Measure (VTM), the number of test vectors are predicted for each cell, then for the entire array. Applicable regardless of the fault type, M-tetability is experimented on various iterative arrays and generated results are debated.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126135905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745198
C. S. Raghu, S. Bhowmik, Poorvaja Ramani, S. Sundaram
Increased focus on high performance circuit design and shorter development cycle time for ASIC libraries, are driving the need for automatic circuit optimizers in the ASIC library development environment. High performance input/output circuits are the key differentiator cells in the ASIC library market. Automating the design process of these circuits using an optimizer, not only ensures high performance cells but also provides faster design cycle. COST has been used to optimize cells in the development of many ASIC libraries. In this paper we have described the essential components of the COST optimization system and presented a method for optimizing I/O circuits. We have compared the performance of the two cost function heuristics implemented in our optimization system on ASIC input/output circuits.
{"title":"COST: Circuit Optimization SysTem in ASIC library development environment","authors":"C. S. Raghu, S. Bhowmik, Poorvaja Ramani, S. Sundaram","doi":"10.1109/ICVD.1999.745198","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745198","url":null,"abstract":"Increased focus on high performance circuit design and shorter development cycle time for ASIC libraries, are driving the need for automatic circuit optimizers in the ASIC library development environment. High performance input/output circuits are the key differentiator cells in the ASIC library market. Automating the design process of these circuits using an optimizer, not only ensures high performance cells but also provides faster design cycle. COST has been used to optimize cells in the development of many ASIC libraries. In this paper we have described the essential components of the COST optimization system and presented a method for optimizing I/O circuits. We have compared the performance of the two cost function heuristics implemented in our optimization system on ASIC input/output circuits.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124889104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745178
D. V. R. Murthy, S. Ramachandran, S. Srinivasan
A novel implementation of Two Dimensional Discrete Cosine Transform (2D-DCT) using Embedded Programmable Logic Devices (EPLDs) has been proposed in this paper. The key feature of this scheme is that it's architecture is regular, linear, pipelined and it fits into just four numbers of commercially available EPLDs. It is capable of processing images of size 512/spl times/512 pixels at rates of 25 frames per second. The chip set offers device independent design and can be used in conjunction with other processors. The algorithm implemented can be easily modified and remapped as per needs with a minimum of effort since the architecture is realized using modular Hardware Description Language (HDL). The hardware complexity and accuracy of the proposed DCT processor compare favourably with those of other known implementation techniques.
{"title":"Parallel implementation of 2D-discrete cosine transform using EPLDs","authors":"D. V. R. Murthy, S. Ramachandran, S. Srinivasan","doi":"10.1109/ICVD.1999.745178","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745178","url":null,"abstract":"A novel implementation of Two Dimensional Discrete Cosine Transform (2D-DCT) using Embedded Programmable Logic Devices (EPLDs) has been proposed in this paper. The key feature of this scheme is that it's architecture is regular, linear, pipelined and it fits into just four numbers of commercially available EPLDs. It is capable of processing images of size 512/spl times/512 pixels at rates of 25 frames per second. The chip set offers device independent design and can be used in conjunction with other processors. The algorithm implemented can be easily modified and remapped as per needs with a minimum of effort since the architecture is realized using modular Hardware Description Language (HDL). The hardware complexity and accuracy of the proposed DCT processor compare favourably with those of other known implementation techniques.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124265806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745136
Rashmi Goswami, V. Srinivasan, M. Balakrishnan
An MPEG-2 video data simulator has been designed in a constrained design space. A hierarchical FSM model has been developed for MPEG-2 video data simulator. This model can be used for any sequence of moving pictures. This model was verified by behavioral (C-language) simulation for a particular case (color-bars data and I I I picture sequence). After an evaluation of the implementation options available in our fairly constrained design space, firmware implementation was selected and implemented.
在受限的设计空间中设计了一个MPEG-2视频数据模拟器。建立了MPEG-2视频数据模拟器的分层FSM模型。该模型可用于任何序列的运动图像。该模型通过特定情况下的行为(c语言)模拟(色条数据和I I I图像序列)进行了验证。在对我们相当有限的设计空间中可用的实现选项进行评估后，选择并实现了固件实现。
{"title":"MPEG-2 video data simulator: a case study in constrained HW-SW codesign","authors":"Rashmi Goswami, V. Srinivasan, M. Balakrishnan","doi":"10.1109/ICVD.1999.745136","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745136","url":null,"abstract":"An MPEG-2 video data simulator has been designed in a constrained design space. A hierarchical FSM model has been developed for MPEG-2 video data simulator. This model can be used for any sequence of moving pictures. This model was verified by behavioral (C-language) simulation for a particular case (color-bars data and I I I picture sequence). After an evaluation of the implementation options available in our fairly constrained design space, firmware implementation was selected and implemented.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123092828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745180
A. Gautam, J. Rao, R. Rathi, H. Udayakumar
TMS320C2700 is the first TI DSP with a new architecture combining the features of a traditional DSP and Micro-Controller, targeted for Hard Disk Drives, DVD and Embedded Control applications. The development of this reusable DSP Core and the Emulation Test Chip with an aim of fast turn-around to market posed many design and methodology challenges. These challenges included efficient layout of a datapath and bus-dominant Core, meeting all the performance and reliability requirements, clocking methodology for a reusable Core, and the design of a 1 million gate Emulation Chip with 82 K/spl times/16 on-chip RAM and many peripherals. This paper describes the various design-in approaches used to meet these goals, reducing the iterations in the design cycle, ultimately resulting in a first pass working silicon for the design.
{"title":"A design-in methodology to ensure first time success of complex digital signal processors","authors":"A. Gautam, J. Rao, R. Rathi, H. Udayakumar","doi":"10.1109/ICVD.1999.745180","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745180","url":null,"abstract":"TMS320C2700 is the first TI DSP with a new architecture combining the features of a traditional DSP and Micro-Controller, targeted for Hard Disk Drives, DVD and Embedded Control applications. The development of this reusable DSP Core and the Emulation Test Chip with an aim of fast turn-around to market posed many design and methodology challenges. These challenges included efficient layout of a datapath and bus-dominant Core, meeting all the performance and reliability requirements, clocking methodology for a reusable Core, and the design of a 1 million gate Emulation Chip with 82 K/spl times/16 on-chip RAM and many peripherals. This paper describes the various design-in approaches used to meet these goals, reducing the iterations in the design cycle, ultimately resulting in a first pass working silicon for the design.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129640885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745163
J. Deka, P. Dasgupta, P. Chakrabarti
Model checking transition systems with delays using timed logics such as TCTL is an attractive technique for proper verification of hardware descriptions. TCTL model checking requires the construction of time regions which depends not only on the timed graph, but also the TCTL formula. This limits the efficiency of a pure top-down approach for model checking. We propose a restricted version of TCTL, namely DCTL, which can be checked in a pure top-down manner without augmenting the region graph a priori.
{"title":"An efficiently checkable subset of TCTL for formal verification of transition systems with delays","authors":"J. Deka, P. Dasgupta, P. Chakrabarti","doi":"10.1109/ICVD.1999.745163","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745163","url":null,"abstract":"Model checking transition systems with delays using timed logics such as TCTL is an attractive technique for proper verification of hardware descriptions. TCTL model checking requires the construction of time regions which depends not only on the timed graph, but also the TCTL formula. This limits the efficiency of a pure top-down approach for model checking. We propose a restricted version of TCTL, namely DCTL, which can be checked in a pure top-down manner without augmenting the region graph a priori.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132614682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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