Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745220
P. Variyam, J. Hou, A. Chatterjee
In this paper, we present a novel test generation strategy based on partial numerical fault simulation. Existing fault-based test generation methodologies for analog circuits are based on accurate but expensive fault simulation. In the proposed methodology, fault simulation is terminated before convergence for reasons of simulation speed. The relative fitness of various input stimuli is evaluated based on the results of this partial numerical simulation. A comparison of this new methodology with existing accurate fault simulation based test generation methods, shows up to 15 times speed-up in test generation.
{"title":"Test generation for analog circuits using partial numerical simulation","authors":"P. Variyam, J. Hou, A. Chatterjee","doi":"10.1109/ICVD.1999.745220","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745220","url":null,"abstract":"In this paper, we present a novel test generation strategy based on partial numerical fault simulation. Existing fault-based test generation methodologies for analog circuits are based on accurate but expensive fault simulation. In the proposed methodology, fault simulation is terminated before convergence for reasons of simulation speed. The relative fitness of various input stimuli is evaluated based on the results of this partial numerical simulation. A comparison of this new methodology with existing accurate fault simulation based test generation methods, shows up to 15 times speed-up in test generation.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133971289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745117
Li-Fu Chang, Abhay Dubey, Keh-Jeng Chang, R. Mathews, Ken Wong
With the advent of deep-submicron technologies, more and more process-induced effects become first-order influences to the performance of VLSI chips. In this paper we will describe a set of wafer-level electrical measurement methods which we have used to measure process-induced effects for several deep-submicron technologies. Seven important interconnect performance parameters have been identified as a minimum set of parameters needed to accurately accommodate the effects and predict the resistance and capacitance of the state-of-the-art interconnect systems. Therefore, interconnect parasitic estimation, or interchangeably in this paper, RC extraction, has to be improved to incorporate those parameters. It is also essential that process/TCAD describes those parameters in a format that allows more accurate parasitic estimation.
{"title":"Incorporating process induced effects into RC extraction","authors":"Li-Fu Chang, Abhay Dubey, Keh-Jeng Chang, R. Mathews, Ken Wong","doi":"10.1109/ICVD.1999.745117","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745117","url":null,"abstract":"With the advent of deep-submicron technologies, more and more process-induced effects become first-order influences to the performance of VLSI chips. In this paper we will describe a set of wafer-level electrical measurement methods which we have used to measure process-induced effects for several deep-submicron technologies. Seven important interconnect performance parameters have been identified as a minimum set of parameters needed to accurately accommodate the effects and predict the resistance and capacitance of the state-of-the-art interconnect systems. Therefore, interconnect parasitic estimation, or interchangeably in this paper, RC extraction, has to be improved to incorporate those parameters. It is also essential that process/TCAD describes those parameters in a format that allows more accurate parasitic estimation.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121417557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745277
C. Ravikumar, Ajay Mittal
Increasingly, VLSI systems are being designed using macro blocks and predesigned cores. Since the clock rate at which these circuits operate is steadily increasing, it is important to perform delay testing on modern VLSI chips and systems. Algorithms for delay test generation and delay fault simulation are known to be compute-intensive. Many of these algorithms require gate-level descriptions of circuits which are difficult to generate and may be even impossible to provide when the designer has made use of predesigned cores. Hierarchical testing appears to be an attractive alternative in such cases. Tests generated for logic blocks may be reused to generate tests for larger systems comprising of the logic blocks, hence reducing the total effort in test generation. Tests show in this paper that the computational effort spent in fault simulation can also be reduced using a hierarchical approach. The simulator HIDEFS described in this paper exploits the modular nature of the circuit to save on the memory requirement as well as execution time requirement of fault simulation.
{"title":"Hierarchical delay fault simulation","authors":"C. Ravikumar, Ajay Mittal","doi":"10.1109/ICVD.1999.745277","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745277","url":null,"abstract":"Increasingly, VLSI systems are being designed using macro blocks and predesigned cores. Since the clock rate at which these circuits operate is steadily increasing, it is important to perform delay testing on modern VLSI chips and systems. Algorithms for delay test generation and delay fault simulation are known to be compute-intensive. Many of these algorithms require gate-level descriptions of circuits which are difficult to generate and may be even impossible to provide when the designer has made use of predesigned cores. Hierarchical testing appears to be an attractive alternative in such cases. Tests generated for logic blocks may be reused to generate tests for larger systems comprising of the logic blocks, hence reducing the total effort in test generation. Tests show in this paper that the computational effort spent in fault simulation can also be reduced using a hierarchical approach. The simulator HIDEFS described in this paper exploits the modular nature of the circuit to save on the memory requirement as well as execution time requirement of fault simulation.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123214804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745152
P. Chakrabarti, P. Dasgupta, P. Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose
Static simulation is a method to compile event driven simulations into a single composite state machine. Code generated based on this does not require the event management overheads of an event driven simulator resulting in significant speedup on this overhead. In this paper we present an implementation of static simulation, highlight the problems of pure static unfolding and suggest methods to control the possibility of state explosion. Specific methods suggested include special schemes for handling lumped delays, selective tracking, unclocking of individual blocks and partial composition.
{"title":"Controlling state explosion in static simulation by selective composition","authors":"P. Chakrabarti, P. Dasgupta, P. Das, Arnob Roy, Shuvendu K. Lahiri, Mrinal Bose","doi":"10.1109/ICVD.1999.745152","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745152","url":null,"abstract":"Static simulation is a method to compile event driven simulations into a single composite state machine. Code generated based on this does not require the event management overheads of an event driven simulator resulting in significant speedup on this overhead. In this paper we present an implementation of static simulation, highlight the problems of pure static unfolding and suggest methods to control the possibility of state explosion. Specific methods suggested include special schemes for handling lumped delays, selective tracking, unclocking of individual blocks and partial composition.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115860941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745221
F. Chang, Melissa Kwok, K. Rachlin, R. Pack
In this paper, we show that the use of SubWavelength mask design for improved IC performance and yield presents new challenges for traditional deep submicron ECAD physical verification tools. We demonstrate the need for new approaches and propose two tools for the silicon-level physical verification of SubWavelength designs. Fortunately, these tools work within current physical verification design flows.
{"title":"Silicon-level physical verification of SubWavelength/sup TM/ designs","authors":"F. Chang, Melissa Kwok, K. Rachlin, R. Pack","doi":"10.1109/ICVD.1999.745221","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745221","url":null,"abstract":"In this paper, we show that the use of SubWavelength mask design for improved IC performance and yield presents new challenges for traditional deep submicron ECAD physical verification tools. We demonstrate the need for new approaches and propose two tools for the silicon-level physical verification of SubWavelength designs. Fortunately, these tools work within current physical verification design flows.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130555132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745181
S. Ramanathan, V. Visvanathan, S. Nandy
ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific instruction-set processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms.
{"title":"Synthesis of configurable architectures for DSP algorithms","authors":"S. Ramanathan, V. Visvanathan, S. Nandy","doi":"10.1109/ICVD.1999.745181","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745181","url":null,"abstract":"ASICs offer the best realization of DSP algorithms in terms of performance, but the cost is prohibitive, especially when the volumes involved are low. However, if the architecture synthesis trajectory for such algorithms is such that the target architecture can be identified as an interconnection of elementary parameterized computational structures, then it is possible to attain a close match, both in terms of performance and power with respect to an ASIC, for any algorithmic parameters of the given algorithm. Such an architecture is weakly programmable (configurable) and can be viewed as an application specific instruction-set processor (ASIP). In this work, we present a methodology to synthesize ASIPs for DSP algorithms.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129551298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745154
P. Maurer
This paper presents new, highly-efficient techniques for simulating extremely large circuits, assuming that hierarchical design techniques have been used. Both hierarchical and partitioned circuits consist of a master circuit and several sub-circuits. Hierarchical circuits permit sub-circuits to be reused, while partitioned circuits permit only a single use of each sub-circuit. Both types of circuits permit multiple levels of hierarchy. In partitioned circuits, triggering is used to perform simulations that are several times faster than Levelized Compiled Code (LCC) simulation. For hierarchical simulation, the concept of boundary activity is introduced. Optimization with respect to boundary activity can produce simulations that are much faster than ordinary flat simulations. It is further shown that hierarchical design can permit the efficient simulation of circuits that cannot be simulated on a single workstation using ordinary flat simulation. Aggressive use of hierarchy is used to demonstrate the simulation of circuits containing as many as four billion (4,000,000,000) gates.
{"title":"Efficient simulation for hierarchical and partitioned circuits","authors":"P. Maurer","doi":"10.1109/ICVD.1999.745154","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745154","url":null,"abstract":"This paper presents new, highly-efficient techniques for simulating extremely large circuits, assuming that hierarchical design techniques have been used. Both hierarchical and partitioned circuits consist of a master circuit and several sub-circuits. Hierarchical circuits permit sub-circuits to be reused, while partitioned circuits permit only a single use of each sub-circuit. Both types of circuits permit multiple levels of hierarchy. In partitioned circuits, triggering is used to perform simulations that are several times faster than Levelized Compiled Code (LCC) simulation. For hierarchical simulation, the concept of boundary activity is introduced. Optimization with respect to boundary activity can produce simulations that are much faster than ordinary flat simulations. It is further shown that hierarchical design can permit the efficient simulation of circuits that cannot be simulated on a single workstation using ordinary flat simulation. Aggressive use of hierarchy is used to demonstrate the simulation of circuits containing as many as four billion (4,000,000,000) gates.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125951866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745120
A. Chandrakasan, A. Dancy, J. Goodman, T. Simon
This paper describes the system design of a low-power wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties such as the network configuration and data statistics are exploited to minimize computational switching. Embedded power supplies systems are also used to minimize energy dissipation under varying temperature, process parameters and computational workload. Since the camera operates in a burst mode with long idle periods, emphasis must be placed on reducing system standby power dissipation.
{"title":"A low-power wireless camera system","authors":"A. Chandrakasan, A. Dancy, J. Goodman, T. Simon","doi":"10.1109/ICVD.1999.745120","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745120","url":null,"abstract":"This paper describes the system design of a low-power wireless camera. A system level approach is used to reduce energy dissipation and maximize battery lifetime. System properties such as the network configuration and data statistics are exploited to minimize computational switching. Embedded power supplies systems are also used to minimize energy dissipation under varying temperature, process parameters and computational workload. Since the camera operates in a burst mode with long idle periods, emphasis must be placed on reducing system standby power dissipation.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"08 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127181853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745165
T. Arons, A. Pnueli
In this paper Tomasulo's algorithm for out-of-order execution is shown to be a refinement of the sequential instruction execution algorithm. Correctness of Tomasulo's algorithm is established by proving that the register files of Tomasulo's algorithm and the sequential algorithm agree once all instructions have been completed.
{"title":"Verifying Tomasulo's algorithm by refinement","authors":"T. Arons, A. Pnueli","doi":"10.1109/ICVD.1999.745165","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745165","url":null,"abstract":"In this paper Tomasulo's algorithm for out-of-order execution is shown to be a refinement of the sequential instruction execution algorithm. Correctness of Tomasulo's algorithm is established by proving that the register files of Tomasulo's algorithm and the sequential algorithm agree once all instructions have been completed.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114495335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745276
C. Ravikumar, Manish Sharma, R. Patney
Testing and fault diagnosis of core-based systems are both difficult problems. Being able to identify which module in the core-based system is faulty has become very important. In this paper, we present algorithms to introduce test points for improving the diagnosability of a digital system. We define a measure of diagnosability known as module resolution which relates to the number of circuit modules that are suspected to be faulty after the diagnostic test procedure has been completed. We present a technique to partition the system into subsystems such that they can be tested in isolation. We also concurrently arrive at a test schedule which minimizes the overall effort in diagnostic testing. We have developed a tool called DEBIT for identifying the number, type, and location of test points in the circuit. We report the results of applying the tool on several benchmark circuits.
{"title":"Improving the diagnosability of digital circuits","authors":"C. Ravikumar, Manish Sharma, R. Patney","doi":"10.1109/ICVD.1999.745276","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745276","url":null,"abstract":"Testing and fault diagnosis of core-based systems are both difficult problems. Being able to identify which module in the core-based system is faulty has become very important. In this paper, we present algorithms to introduce test points for improving the diagnosability of a digital system. We define a measure of diagnosability known as module resolution which relates to the number of circuit modules that are suspected to be faulty after the diagnostic test procedure has been completed. We present a technique to partition the system into subsystems such that they can be tested in isolation. We also concurrently arrive at a test schedule which minimizes the overall effort in diagnostic testing. We have developed a tool called DEBIT for identifying the number, type, and location of test points in the circuit. We report the results of applying the tool on several benchmark circuits.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124581095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：