Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745134
F. Schellenberg
Design for Manufacturing (DFM) practices for productivity improvement have been applied with great success in many industries, including automobile manufacturing, engine design, and consumer electronics. Until now, Moore's Law for IC productivity has been dominated by innovation and invention, not a drive for efficiency. With IC fab costs dramatically increasing, DFM procedures are becoming far more attractive. In this paper, we briefly review the general DFM practices that have been successful in other industries, and report on the results from an example in the semiconductor industry, produced by the SEMATECH Litho/Design Workshops. The results of these workshops have assisted the adoption of advanced lithographic DFM technologies, such as OPC (Optimized Process Correction) and accelerated progress along the Moore's Law productivity curve.
{"title":"Design for manufacturing in the semiconductor industry: the Litho/Design Workshops","authors":"F. Schellenberg","doi":"10.1109/ICVD.1999.745134","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745134","url":null,"abstract":"Design for Manufacturing (DFM) practices for productivity improvement have been applied with great success in many industries, including automobile manufacturing, engine design, and consumer electronics. Until now, Moore's Law for IC productivity has been dominated by innovation and invention, not a drive for efficiency. With IC fab costs dramatically increasing, DFM procedures are becoming far more attractive. In this paper, we briefly review the general DFM practices that have been successful in other industries, and report on the results from an example in the semiconductor industry, produced by the SEMATECH Litho/Design Workshops. The results of these workshops have assisted the adoption of advanced lithographic DFM technologies, such as OPC (Optimized Process Correction) and accelerated progress along the Moore's Law productivity curve.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127957641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745185
B. Gupta, H. Narayanan, M. Desai
In this paper we address the state assignment problem for Finite State Machines (FSMs). In particular we study the effect of certain sparse state encoding strategies on the area and performance of the FSM when implemented using multi-level logic circuits. We present the results of a systematic study conducted for characterizing the effects of some encoding schemes on the area and delay of FSM implementations. Based on these results, we conclude that two-hot encodings preserve the speed advantages of one-hot encodings while reducing the area of the implemented circuit. We show that the problem of finding an optimal two-hot encoding can be posed as a constrained partitioning problem on a certain graph. We describe a greedy heuristic algorithm for this partitioning problem. Finally, we present some results and comparisons between the circuits obtained using two-hot encodings as opposed to those obtained using one-hot encoding, and to those obtained using JEDI and NOVA. The results are encouraging, particularly for FSMs with a large number of states.
{"title":"A state assignment scheme targeting performance and area","authors":"B. Gupta, H. Narayanan, M. Desai","doi":"10.1109/ICVD.1999.745185","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745185","url":null,"abstract":"In this paper we address the state assignment problem for Finite State Machines (FSMs). In particular we study the effect of certain sparse state encoding strategies on the area and performance of the FSM when implemented using multi-level logic circuits. We present the results of a systematic study conducted for characterizing the effects of some encoding schemes on the area and delay of FSM implementations. Based on these results, we conclude that two-hot encodings preserve the speed advantages of one-hot encodings while reducing the area of the implemented circuit. We show that the problem of finding an optimal two-hot encoding can be posed as a constrained partitioning problem on a certain graph. We describe a greedy heuristic algorithm for this partitioning problem. Finally, we present some results and comparisons between the circuits obtained using two-hot encodings as opposed to those obtained using one-hot encoding, and to those obtained using JEDI and NOVA. The results are encouraging, particularly for FSMs with a large number of states.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131099031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745218
Joonbae Park, Y. Koo, Wonchan Kim
A two-step approach for fast locking of a DLL (delay-locked-loop) circuit is discussed. The locking process consists of two steps; the coarse tuning in digital domain by tapping a delay position for fast coarse locking, and the accurate phase synchronization between the external clock and the internal clock in analog operation mode. With this two step approach, fast locking and low phase error can be simultaneously achieved.
{"title":"A semi-digital delay locked loop for clock skew minimization","authors":"Joonbae Park, Y. Koo, Wonchan Kim","doi":"10.1109/ICVD.1999.745218","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745218","url":null,"abstract":"A two-step approach for fast locking of a DLL (delay-locked-loop) circuit is discussed. The locking process consists of two steps; the coarse tuning in digital domain by tapping a delay position for fast coarse locking, and the accurate phase synchronization between the external clock and the internal clock in analog operation mode. With this two step approach, fast locking and low phase error can be simultaneously achieved.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123920000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745122
M. Mehendale, S. Sherlekar
The paper presents low power code generation of multiplication-free linear transforms targeted to both the register-rich RISC architectures and the single-register accumulator based DSP architectures. For register rich architectures, we present ordered chain-type DAC as the optimum structure for low power code generation of 1-dimensional transforms. For 2-dimensional transforms, we present an algorithm that performs instruction scheduling followed by register assignment for low power. For single-register architectures, we present a node re-ordering technique for reducing power dissipation. We present results to highlight the effectiveness of these techniques.
{"title":"Low power code generation of multiplication-free linear transforms","authors":"M. Mehendale, S. Sherlekar","doi":"10.1109/ICVD.1999.745122","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745122","url":null,"abstract":"The paper presents low power code generation of multiplication-free linear transforms targeted to both the register-rich RISC architectures and the single-register accumulator based DSP architectures. For register rich architectures, we present ordered chain-type DAC as the optimum structure for low power code generation of 1-dimensional transforms. For 2-dimensional transforms, we present an algorithm that performs instruction scheduling followed by register assignment for low power. For single-register architectures, we present a node re-ordering technique for reducing power dissipation. We present results to highlight the effectiveness of these techniques.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122405247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745123
N. Raghavan, V. Akella, Smita Bakshi
In synchronous circuits, the clock signal switches at every clock cycle and drives a large capacitance. As a result, the clock signal is a major source of dynamic power dissipation. Significant power savings can be obtained by identifying periods of inactivity in parts of the circuit, and disabling the clock to those parts of the circuit at the appropriate times. Selectively disabling the clock in this manner is referred to as clock gating. In this paper/sup 1/, we present a methodology to identify registers and flip flops in a circuit for which the clock input can be gated with a control signal. We also generate the combinational logic to produce this control signal. We present an algorithm to estimate the power saving obtained by gating the clock and the performance penalty (if any) associated with the introduction of gating logic. The algorithm generates the clock gating logic which is inserted appropriately into the original circuit to produce a low power, gated clock version of the circuit.
{"title":"Automatic insertion of gated clocks at register transfer level","authors":"N. Raghavan, V. Akella, Smita Bakshi","doi":"10.1109/ICVD.1999.745123","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745123","url":null,"abstract":"In synchronous circuits, the clock signal switches at every clock cycle and drives a large capacitance. As a result, the clock signal is a major source of dynamic power dissipation. Significant power savings can be obtained by identifying periods of inactivity in parts of the circuit, and disabling the clock to those parts of the circuit at the appropriate times. Selectively disabling the clock in this manner is referred to as clock gating. In this paper/sup 1/, we present a methodology to identify registers and flip flops in a circuit for which the clock input can be gated with a control signal. We also generate the combinational logic to produce this control signal. We present an algorithm to estimate the power saving obtained by gating the clock and the performance penalty (if any) associated with the introduction of gating logic. The algorithm generates the clock gating logic which is inserted appropriately into the original circuit to produce a low power, gated clock version of the circuit.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123502379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745191
Xiaodong Zhang, K. Roy, S. Bhawmik
Due to the increasing use of portable computing and wireless communications systems, energy consumption is of major concern in today's VLSI circuits. With that in mind we present an energy conscious weighted random pattern testing technique for Built-In-Self-Test (BIST) applications. Energy consumption during BIST operation can be minimized while achieving high fault coverage. Simple measures of observability and controllability of circuit nodes are proposed based on primary input signal probability (probability that a signal is logic ONE). Such measures help determine the testability of a circuit. We developed a tool, POWERTEST, which uses a genetic algorithm based search to determine optimal weight sets (signal probabilities or input signal distribution) at primary inputs to minimize energy dissipations. The inputs conforming to the primary input weight set can be generated using cellular automata or LFSR (Linear Feedback Shift Register). We observed that a single input distribution (or weights) may not be sufficient for some random-pattern resistant circuits, while multiple distributions consume larger area. As a trade-off, two distributions have been used in our analysis. Results on ISCAS benchmark circuits show that energy reduction of up to 97.82% can be achieved (compared to equi-probable random-pattern testing with identical fault coverage) while achieving high fault coverage.
{"title":"POWERTEST: a tool for energy conscious weighted random pattern testing","authors":"Xiaodong Zhang, K. Roy, S. Bhawmik","doi":"10.1109/ICVD.1999.745191","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745191","url":null,"abstract":"Due to the increasing use of portable computing and wireless communications systems, energy consumption is of major concern in today's VLSI circuits. With that in mind we present an energy conscious weighted random pattern testing technique for Built-In-Self-Test (BIST) applications. Energy consumption during BIST operation can be minimized while achieving high fault coverage. Simple measures of observability and controllability of circuit nodes are proposed based on primary input signal probability (probability that a signal is logic ONE). Such measures help determine the testability of a circuit. We developed a tool, POWERTEST, which uses a genetic algorithm based search to determine optimal weight sets (signal probabilities or input signal distribution) at primary inputs to minimize energy dissipations. The inputs conforming to the primary input weight set can be generated using cellular automata or LFSR (Linear Feedback Shift Register). We observed that a single input distribution (or weights) may not be sufficient for some random-pattern resistant circuits, while multiple distributions consume larger area. As a trade-off, two distributions have been used in our analysis. Results on ISCAS benchmark circuits show that energy reduction of up to 97.82% can be achieved (compared to equi-probable random-pattern testing with identical fault coverage) while achieving high fault coverage.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125039616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745157
Pradip A. Thaker, M. Zaghloul, M. Amin
RTL-based high level design methodology suffers a major drawback in the area of testability analysis due to lack of effective RTL fault models. Testability of a design is considered structure dependent. Since the structure of a design changes drastically with every logic synthesis run, testability analysis is performed only after final logic synthesis and therefore findings of such effort are too late to be implemented in the design without a significant schedule impact. In this paper we analyze the testability relationship between the RT level design and different structural (gate level) implementations resulting from optimization driven logic synthesis runs. We empirically establish that the testability properties of structural implementations are derived from architectural descriptions at the RT level and therefore logic synthesis does not significantly impact them. Furthermore, various different structural implementations resulting from logic synthesis (with different optimization constraints) exhibit poor testability in the same RTL design space. The data presented in this paper provides a missing key ingredient towards successful RTL fault modeling. We also propose the use of preliminary gate level netlist for early analysis to estimate testability properties of the final implementation.
{"title":"Study of correlation of testability aspects of RTL description and resulting structural implementations","authors":"Pradip A. Thaker, M. Zaghloul, M. Amin","doi":"10.1109/ICVD.1999.745157","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745157","url":null,"abstract":"RTL-based high level design methodology suffers a major drawback in the area of testability analysis due to lack of effective RTL fault models. Testability of a design is considered structure dependent. Since the structure of a design changes drastically with every logic synthesis run, testability analysis is performed only after final logic synthesis and therefore findings of such effort are too late to be implemented in the design without a significant schedule impact. In this paper we analyze the testability relationship between the RT level design and different structural (gate level) implementations resulting from optimization driven logic synthesis runs. We empirically establish that the testability properties of structural implementations are derived from architectural descriptions at the RT level and therefore logic synthesis does not significantly impact them. Furthermore, various different structural implementations resulting from logic synthesis (with different optimization constraints) exhibit poor testability in the same RTL design space. The data presented in this paper provides a missing key ingredient towards successful RTL fault modeling. We also propose the use of preliminary gate level netlist for early analysis to estimate testability properties of the final implementation.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125399535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745182
S. Bobba, I. Hajj, Naresh R Shanbhag
Power minimization is an important objective in present day VLSI design. Macromodels for power dissipation can be used to estimate power at a high-level of abstraction. High-level power estimation methods provide the designer with more flexibility to explore design trade-offs early in the design cycle. In this paper, we present closed-form analytical expressions for power consumption of macro-blocks in terms of the word-statistics. We present an analytical expression for total bit transition activity of a signal line in terms of the word-statistics. We also present analytical power models for macro-blocks in DSP architectures in terms of total bit transition activity and other parameters. Experimental results validating the analytical expressions are also included in this paper.
{"title":"Analytical expressions for power dissipation of macro-blocks in DSP architectures","authors":"S. Bobba, I. Hajj, Naresh R Shanbhag","doi":"10.1109/ICVD.1999.745182","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745182","url":null,"abstract":"Power minimization is an important objective in present day VLSI design. Macromodels for power dissipation can be used to estimate power at a high-level of abstraction. High-level power estimation methods provide the designer with more flexibility to explore design trade-offs early in the design cycle. In this paper, we present closed-form analytical expressions for power consumption of macro-blocks in terms of the word-statistics. We present an analytical expression for total bit transition activity of a signal line in terms of the word-statistics. We also present analytical power models for macro-blocks in DSP architectures in terms of total bit transition activity and other parameters. Experimental results validating the analytical expressions are also included in this paper.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129349114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745202
Keerthi Heragu, J. Patel, V. Agrawal
We propose a simulation-based technique that uses a genetic algorithm (GA) to generate tests for delay faults on segments of any given length. At every line, we assume that an upper bound on the number of testable segment faults that originate there is known. Such a bound is efficiently computed by an implication-based technique. The fitness function for the GA is derived from an objective function that favors vectors which might detect a large number of faults. This is accomplished by a simulator used as a base engine, by dynamically identifying a line m with the highest upper bound for the number of segments on which faults can and are yet to be tested, and by ranking vectors according to their ability to target the simultaneous objectives of invoking a transition on m and maximizing the number of signals that propagate robustly in the fanout cone of m. Rather than limiting the number of generations of evolution in the GA, we obtain improved results by using the diversity of the individuals in a population as a stopping criterion. Results indicate that for small segment lengths, reasonable robust segment delay test coverages can be obtained for most benchmark circuits. Also, the tests generated using the segment delay fault model detect a large number of transition and path delay faults. For example in the benchmark circuit c3540, tests generated for faults on segments of length 5 had a transition fault coverage of 96.1% and were able to detect 9,246 path faults.
{"title":"A test generator for segment delay faults","authors":"Keerthi Heragu, J. Patel, V. Agrawal","doi":"10.1109/ICVD.1999.745202","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745202","url":null,"abstract":"We propose a simulation-based technique that uses a genetic algorithm (GA) to generate tests for delay faults on segments of any given length. At every line, we assume that an upper bound on the number of testable segment faults that originate there is known. Such a bound is efficiently computed by an implication-based technique. The fitness function for the GA is derived from an objective function that favors vectors which might detect a large number of faults. This is accomplished by a simulator used as a base engine, by dynamically identifying a line m with the highest upper bound for the number of segments on which faults can and are yet to be tested, and by ranking vectors according to their ability to target the simultaneous objectives of invoking a transition on m and maximizing the number of signals that propagate robustly in the fanout cone of m. Rather than limiting the number of generations of evolution in the GA, we obtain improved results by using the diversity of the individuals in a population as a stopping criterion. Results indicate that for small segment lengths, reasonable robust segment delay test coverages can be obtained for most benchmark circuits. Also, the tests generated using the segment delay fault model detect a large number of transition and path delay faults. For example in the benchmark circuit c3540, tests generated for faults on segments of length 5 had a transition fault coverage of 96.1% and were able to detect 9,246 path faults.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127916560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-01-10DOI: 10.1109/ICVD.1999.745162
Srivatsan Srinivasan, Parminder Chhabra, P. Jaini, A. Aziz, L. John
Formal verification of cache coherence in a multiprocessor environment is essential in ascertaining the validity of a cache coherence protocol. Although a number of cache coherence verification techniques are available, very few authors have reported results on verification of cache coherence protocols using symbolic model checking. In this paper we present the verification of a three state snoop-based cache coherence protocol using model checking in VIS. As symbolic model checking is beset with the state explosion problem, directly verifying the protocol for a large number of processors is infeasible. We have developed a set of modeling strategies that we found useful in verifying cache coherence of two to five processor configurations. In this paper, we report the techniques we adopted in modeling and verifying the protocol.
{"title":"Formal verification of a snoop-based cache coherence protocol using symbolic model checking","authors":"Srivatsan Srinivasan, Parminder Chhabra, P. Jaini, A. Aziz, L. John","doi":"10.1109/ICVD.1999.745162","DOIUrl":"https://doi.org/10.1109/ICVD.1999.745162","url":null,"abstract":"Formal verification of cache coherence in a multiprocessor environment is essential in ascertaining the validity of a cache coherence protocol. Although a number of cache coherence verification techniques are available, very few authors have reported results on verification of cache coherence protocols using symbolic model checking. In this paper we present the verification of a three state snoop-based cache coherence protocol using model checking in VIS. As symbolic model checking is beset with the state explosion problem, directly verifying the protocol for a large number of processors is infeasible. We have developed a set of modeling strategies that we found useful in verifying cache coherence of two to five processor configurations. In this paper, we report the techniques we adopted in modeling and verifying the protocol.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"52 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132511392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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