Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529643
N. Yildiz, V. Tavsanoglu
Cellular nonlinear/neural networks (CNN's) are one of the analog systems that is hard to emulate or simulate on digital systems. It is known that CNN systems are linear for Gabor-type spatial filters. Although it is possible to represent the state equations of the discrete CNN in matrix notation, it is almost impossible to implement the huge state matrix on a digital system without optimization. In this paper some well known linear equation solving methods are optimized for CNN and required computational powers and memories are compared.
{"title":"On the digital simulation of linear cellular neural networks","authors":"N. Yildiz, V. Tavsanoglu","doi":"10.1109/ECCTD.2007.4529643","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529643","url":null,"abstract":"Cellular nonlinear/neural networks (CNN's) are one of the analog systems that is hard to emulate or simulate on digital systems. It is known that CNN systems are linear for Gabor-type spatial filters. Although it is possible to represent the state equations of the discrete CNN in matrix notation, it is almost impossible to implement the huge state matrix on a digital system without optimization. In this paper some well known linear equation solving methods are optimized for CNN and required computational powers and memories are compared.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122232605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529632
D. Crookes, Richard M. Jiang
In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation cycles of partial products to as much as N/4, and eliminate most of the invertion operations which consume power in a conventional multiplier in generating the partial products. Unlike other high-radix methods, the pre-multiplication in the new algorithm employs a BSD method which requires no extra adder, and thus removes the extra delay for additions which hinders other high-radix algorithms.
{"title":"A low-power high-radix serial-parallel multiplier","authors":"D. Crookes, Richard M. Jiang","doi":"10.1109/ECCTD.2007.4529632","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529632","url":null,"abstract":"In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation cycles of partial products to as much as N/4, and eliminate most of the invertion operations which consume power in a conventional multiplier in generating the partial products. Unlike other high-radix methods, the pre-multiplication in the new algorithm employs a BSD method which requires no extra adder, and thus removes the extra delay for additions which hinders other high-radix algorithms.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"117 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129460201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529753
O. Boncalo, M. Udrescu, L. Prodan, M. Vladutiu, A. Amaricai
This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [T.A. DeLong et al., 1996] [E. Jenn et al., 1994], and were adapted to the specific features of quantum computation, including the available error models [J. P. Hayes et al., 2004] [E. Knill et al., 1997]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.
本文讨论了利用故障注入技术评估量子电路容错算法和方法的问题。本文提出的基于突变体的断层注入技术是从经典的断层注入技术中得到启发的[j]。Jenn et al.， 1994]，并适应了量子计算的具体特点，包括可用的误差模型[J]。李海涛，陈晓明，等。[j]。Knill等，1997]。由于hdl具有描述行为和结构电路的能力，以及其层次性，因此采用hdl进行故障注入。实验模拟的故障注入运动除了提供更真实的描述外，还为量子容错评估提供了定量手段。
{"title":"Assessing quantum circuits reliability with mutant-based simulated fault injection","authors":"O. Boncalo, M. Udrescu, L. Prodan, M. Vladutiu, A. Amaricai","doi":"10.1109/ECCTD.2007.4529753","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529753","url":null,"abstract":"This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [T.A. DeLong et al., 1996] [E. Jenn et al., 1994], and were adapted to the specific features of quantum computation, including the available error models [J. P. Hayes et al., 2004] [E. Knill et al., 1997]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126992485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529543
Natalia A. Fernandez-Garcia, J. Albó-Canals, V. Brea, J. Riera-Babures, D. Cabello, X. Vilasís-Cardona
The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.
{"title":"Verification of Split&Shift techniques for CNN hardware reduction","authors":"Natalia A. Fernandez-Garcia, J. Albó-Canals, V. Brea, J. Riera-Babures, D. Cabello, X. Vilasís-Cardona","doi":"10.1109/ECCTD.2007.4529543","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529543","url":null,"abstract":"The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129215785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529696
L. Marco, E. Alarcón
One of the major drawbacks that precludes the use of sliding-mode control wideband signal tracking in buck-based switching power amplifiers is the lack of a design-oriented analysis of tracking bandwidth limits. In this paper the tracking limits for a linear-surface sliding-mode controlled ideal buck converter are addressed for different representative cases, namely, for a single tone, two tones, multiple tone, and a generalization to an arbitrary wideband signal. Analytical design-oriented equations are matched with simulations both for synthetic single-tone and arbitrary wideband noise signal as well as for the envelope signal corresponding to the EDGE standard in an envelope elimination and restoration technique polar RF transmitter architecture.
{"title":"Derivation of the sliding domain for a buck-based switching amplifier in wideband signal tracking applications","authors":"L. Marco, E. Alarcón","doi":"10.1109/ECCTD.2007.4529696","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529696","url":null,"abstract":"One of the major drawbacks that precludes the use of sliding-mode control wideband signal tracking in buck-based switching power amplifiers is the lack of a design-oriented analysis of tracking bandwidth limits. In this paper the tracking limits for a linear-surface sliding-mode controlled ideal buck converter are addressed for different representative cases, namely, for a single tone, two tones, multiple tone, and a generalization to an arbitrary wideband signal. Analytical design-oriented equations are matched with simulations both for synthetic single-tone and arbitrary wideband noise signal as well as for the envelope signal corresponding to the EDGE standard in an envelope elimination and restoration technique polar RF transmitter architecture.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123899027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529713
Piotr Zegarmistrz, Z. Galias
In this work we investigate the problem of reconstruction of conductances in resistor grids. The algorithm proposed by Curtis and Morrow is studied here in terms of numerical stability. We also test its performance in the presence of measurement errors. We show that measurement errors can deteriorate the performance of the algorithm even for small grid sizes and that the algorithm is numerically unstable for larger grids. We propose several methods for improving the algorithm and test the performance of its modified versions.
{"title":"On reconstruction of conductances in resistor grids from boundary measurements","authors":"Piotr Zegarmistrz, Z. Galias","doi":"10.1109/ECCTD.2007.4529713","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529713","url":null,"abstract":"In this work we investigate the problem of reconstruction of conductances in resistor grids. The algorithm proposed by Curtis and Morrow is studied here in terms of numerical stability. We also test its performance in the presence of measurement errors. We show that measurement errors can deteriorate the performance of the algorithm even for small grid sizes and that the algorithm is numerically unstable for larger grids. We propose several methods for improving the algorithm and test the performance of its modified versions.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127742950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529748
Ryo Imabayashi, Y. Uwate, Y. Nishio
In this study, the breakdown of synchronization observed from four coupled chaotic oscillators is investigated. In order to understand the phenomenon, the model of coupled modified van der Pol oscillators with noise is considered. The comparison of the coupled chaotic oscillators with the coupled modified van der Pol oscillators with noise gives us some interesting results.
{"title":"Breakdown of synchronization in chaotic oscillators and noisy oscillators","authors":"Ryo Imabayashi, Y. Uwate, Y. Nishio","doi":"10.1109/ECCTD.2007.4529748","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529748","url":null,"abstract":"In this study, the breakdown of synchronization observed from four coupled chaotic oscillators is investigated. In order to understand the phenomenon, the model of coupled modified van der Pol oscillators with noise is considered. The comparison of the coupled chaotic oscillators with the coupled modified van der Pol oscillators with noise gives us some interesting results.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127819439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529612
H. Barthélemy, S. Bourdel, J. Gaubert, S. Meillére
In this paper a simple FSK/OOK modulator based on a proposed CMOS coupled voltage controlled oscillators is presented. In FSK mode the circuit is a non-continuous phase FSK (NCPFSK) which exhibits a relatively low phase discontinuity at the frequency transition times. The proposed modulator is built from CMOS inverters. The circuit is self biased and the frequency of oscillations can be easily shifted by opening and closing the open loop of each oscillators. Regarding technology, the modulator, which uses any active inductor, is able to operate at high frequency and provides digital output with suitable phase noise. Simulation result from typical parameters of a 0.35 mum CMOS Process is given. The circuit functioning has been also acted from measurements completed from prototypes fabricated with HFE4069 from Philips Semiconductor [1].
本文提出了一种基于CMOS耦合压控振荡器的简单FSK/OOK调制器。在FSK模式下，电路是一个非连续相位FSK (NCPFSK)，在频率转换时间表现出相对较低的相位不连续。所提出的调制器由CMOS逆变器构成。该电路是自偏置的，通过打开和关闭每个振荡器的开环可以很容易地改变振荡的频率。在技术方面，该调制器采用任意有源电感，能够在高频率下工作，并提供具有合适相位噪声的数字输出。给出了0.35 μ m CMOS工艺典型参数的仿真结果。电路的功能也已经从飞利浦半导体的HFE4069制造的原型完成的测量中发挥作用[1]。
{"title":"OOK/NCP-FSK modulator based on coupled open-closed-loop VCOs","authors":"H. Barthélemy, S. Bourdel, J. Gaubert, S. Meillére","doi":"10.1109/ECCTD.2007.4529612","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529612","url":null,"abstract":"In this paper a simple FSK/OOK modulator based on a proposed CMOS coupled voltage controlled oscillators is presented. In FSK mode the circuit is a non-continuous phase FSK (NCPFSK) which exhibits a relatively low phase discontinuity at the frequency transition times. The proposed modulator is built from CMOS inverters. The circuit is self biased and the frequency of oscillations can be easily shifted by opening and closing the open loop of each oscillators. Regarding technology, the modulator, which uses any active inductor, is able to operate at high frequency and provides digital output with suitable phase noise. Simulation result from typical parameters of a 0.35 mum CMOS Process is given. The circuit functioning has been also acted from measurements completed from prototypes fabricated with HFE4069 from Philips Semiconductor [1].","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128594029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529539
Davide Brandano, M. Delgado-Restituto, J. Ruiz-Amaya, Á. Rodríguez-Vázquez
An Electrostatic Discharge (ESD) protected Low- Noise Amplifier (LNA) for the 2.4 GHz ISM band designed in a 0.13 mum standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8 dB power gain, reflexion coefficients S11, S22 < -30 dB over the 2.4 GHz ISM band, a peak noise figure of 1.8 dB, and an IIP3 of 1 dBm, while drawing less than 4.5 mA dc biasing current from the 1.2 V power supply. Further, the LNA withstands a Human Body Model (HBM) ESD stress up to plusmn2.0 kV, by means of the additional custom protection circuitry.
{"title":"A 5.3mW, 2.4GHz ESD protected Low-Noise Amplifier in a 0.13μm RFCMOS technology","authors":"Davide Brandano, M. Delgado-Restituto, J. Ruiz-Amaya, Á. Rodríguez-Vázquez","doi":"10.1109/ECCTD.2007.4529539","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529539","url":null,"abstract":"An Electrostatic Discharge (ESD) protected Low- Noise Amplifier (LNA) for the 2.4 GHz ISM band designed in a 0.13 mum standard RFCMOS technology is presented. The amplifier, including packaging effects, achieves 16.8 dB power gain, reflexion coefficients S11, S22 < -30 dB over the 2.4 GHz ISM band, a peak noise figure of 1.8 dB, and an IIP3 of 1 dBm, while drawing less than 4.5 mA dc biasing current from the 1.2 V power supply. Further, the LNA withstands a Human Body Model (HBM) ESD stress up to plusmn2.0 kV, by means of the additional custom protection circuitry.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129233824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529728
Z. Garczarczyk
In this paper a diagnostic method for analog electronic circuits is presented. The approach is based on determination of the variations of circuit functions with use of higher order sensitivity coefficients. Knowing values of sensitivity coefficients one can formulate multivariate polynomial equations. The solution of test equations with respect to element's deviations results in fault identification. This task can be realized by using Grobner bases to transform a nonlinear equation into triangular form. It is solved by successive computation of the univariate polynomial equation and back substitution. Solution of the polynomial equation is treated as the eigenvalue problem of companion matrix by QR algorithm. Numerical results are presented to clarify method and prove its efficiency.
{"title":"Polynomial fault diagnosis of linear analog circuits","authors":"Z. Garczarczyk","doi":"10.1109/ECCTD.2007.4529728","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529728","url":null,"abstract":"In this paper a diagnostic method for analog electronic circuits is presented. The approach is based on determination of the variations of circuit functions with use of higher order sensitivity coefficients. Knowing values of sensitivity coefficients one can formulate multivariate polynomial equations. The solution of test equations with respect to element's deviations results in fault identification. This task can be realized by using Grobner bases to transform a nonlinear equation into triangular form. It is solved by successive computation of the univariate polynomial equation and back substitution. Solution of the polynomial equation is treated as the eigenvalue problem of companion matrix by QR algorithm. Numerical results are presented to clarify method and prove its efficiency.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116666308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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