Pub Date : 2025-04-14DOI: 10.1109/TNANO.2025.3560672
N. Aruna Kumari;Brajesh Kumar Kaushik
In this article, a comprehensive performance analysis of the emerging and novel TreeFET is demonstrated at 3-nm technology node. The TreeFET is realized by combining nanosheet FET (NSFET) and fin-like interbridge (IB) structures. Initially, the TreeFET is compared with traditional NSFET under the same footprint (FP). The ON current (ION) and switching ratio (ION/IOFF) enhance with TreeFET by 56% and 35.4% compared to the NSFET with matched OFF current (IOFF). Further, the dimensional impact of TreeFET is studied in detail by altering the geometry of IB. On top of that, as the IB height (HIB) is a crucial metric for deciding the performance, the impact of HIB on analog/RF performance is also studied. Although the parasitic capacitance rises with higher HIB, better RF performance is observed with HIB of 30 nm compared to 10 nm due to the significant increase in ON current. Further, it is noted that the electrical performance is degraded with the rise in temperature. Moreover, the circuit level demonstration of TreeFET is carried out at both HIB of 10 nm and 30 nm for the CMOS inverter and ring oscillator (RO). The CMOS inverter switching current (ISC), power-delay product (PDP), and energy-delay product (EDP) are increased by 1.61×, 53%, and 38%, respectively with an increase in HIB. However, for 19-stage RO, an improvement of 11.55% in oscillation frequency (fOSC) is noticed with HIB of 30 nm. Moreover, the PDP and EDP variations are presented for 19-stage RO with variations in HIB. The analysis enables a profound understanding of the performance of emerging TreeFET devices at both device and circuit levels.
{"title":"Comprehensive Analysis of TreeFET: A Circuit Perspective","authors":"N. Aruna Kumari;Brajesh Kumar Kaushik","doi":"10.1109/TNANO.2025.3560672","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3560672","url":null,"abstract":"In this article, a comprehensive performance analysis of the emerging and novel TreeFET is demonstrated at 3-nm technology node. The TreeFET is realized by combining nanosheet FET (NSFET) and fin-like interbridge (IB) structures. Initially, the TreeFET is compared with traditional NSFET under the same footprint (FP). The ON current (<italic>I</i><sub>ON</sub>) and switching ratio (<italic>I</i><sub>ON</sub>/<italic>I</i><sub>OFF</sub>) enhance with TreeFET by 56% and 35.4% compared to the NSFET with matched OFF current (<italic>I</i><sub>OFF</sub>). Further, the dimensional impact of TreeFET is studied in detail by altering the geometry of IB. On top of that, as the IB height (<italic>H</i><sub>IB</sub>) is a crucial metric for deciding the performance, the impact of <italic>H</i><sub>IB</sub> on analog/RF performance is also studied. Although the parasitic capacitance rises with higher <italic>H</i><sub>IB</sub>, better RF performance is observed with <italic>H</i><sub>IB</sub> of 30 nm compared to 10 nm due to the significant increase in ON current. Further, it is noted that the electrical performance is degraded with the rise in temperature. Moreover, the circuit level demonstration of TreeFET is carried out at both <italic>H</i><sub>IB</sub> of 10 nm and 30 nm for the CMOS inverter and ring oscillator (RO). The CMOS inverter switching current (<italic>I</i><sub>SC</sub>), power-delay product (PDP), and energy-delay product (EDP) are increased by 1.61×, 53%, and 38%, respectively with an increase in <italic>H</i><sub>IB</sub>. However, for 19-stage RO, an improvement of 11.55% in oscillation frequency (<italic>f</i><sub>OSC</sub>) is noticed with <italic>H</i><sub>IB</sub> of 30 nm. Moreover, the PDP and EDP variations are presented for 19-stage RO with variations in <italic>H</i><sub>IB</sub>. The analysis enables a profound understanding of the performance of emerging TreeFET devices at both device and circuit levels.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"231-238"},"PeriodicalIF":2.1,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-04DOI: 10.1109/TNANO.2025.3558256
Devendra Chack;Gaurav Kumar
The advancement of future photonic integrated circuits for data center networks relies crucially on the development of highly efficient, low-power, and compact switches. This paper presents the design of non-blocking 4 × 4 and 8 × 8 silicon photonics switches intended using Multimode Interferometer (MMI)-Mach-Zehnder interferometer (MZI) structures. These proposed switches consist of 2 × 2 MMI-MZI switches realized by changing the phase of an optical signal using the thermo-optic effect. At 1550 nm, the proposed 2 × 2 switch exhibits an insertion loss of 0.04 dB and crosstalk of < 39.95 dB. Similarly, the C-band showcases an insertion loss of < 0.06 dB and crosstalk of < −33 dB. To support complex network topologies and enhance network efficiency, a data center network necessitates a higher quantity of port switches. The results show that at 1550 nm, the insertion loss for the 4 × 4 and 8 × 8 switches is 0.47 dB and 1.02 dB, respectively. Furthermore, the insertion loss for the C-band is < 0.50 dB and < 1.5 dB, respectively. The switches exhibit crosstalk of −37.59 dB and −34.67 dB at 1550 nm, respectively. Additionally, they demonstrate crosstalk of < −30 dB for the C-band. This suggests the potential for further scalability in terms of port counts. The switches are designed using the eigenmode expansion method, and the micro heater is designed with a finite element heat transfer solver. These advantages and excellent performance make the device a promising candidate for use in advanced communication systems and photonic integrated circuits.
{"title":"On-chip Non-Blocking 4 × 4 and 8 × 8 Photonic Switches Using MMI-MZI Configuration for Next-Generation Data Center Networks","authors":"Devendra Chack;Gaurav Kumar","doi":"10.1109/TNANO.2025.3558256","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3558256","url":null,"abstract":"The advancement of future photonic integrated circuits for data center networks relies crucially on the development of highly efficient, low-power, and compact switches. This paper presents the design of non-blocking 4 × 4 and 8 × 8 silicon photonics switches intended using Multimode Interferometer (MMI)-Mach-Zehnder interferometer (MZI) structures. These proposed switches consist of 2 × 2 MMI-MZI switches realized by changing the phase of an optical signal using the thermo-optic effect. At 1550 nm, the proposed 2 × 2 switch exhibits an insertion loss of 0.04 dB and crosstalk of < 39.95 dB. Similarly, the C-band showcases an insertion loss of < 0.06 dB and crosstalk of < −33 dB. To support complex network topologies and enhance network efficiency, a data center network necessitates a higher quantity of port switches. The results show that at 1550 nm, the insertion loss for the 4 × 4 and 8 × 8 switches is 0.47 dB and 1.02 dB, respectively. Furthermore, the insertion loss for the C-band is < 0.50 dB and < 1.5 dB, respectively. The switches exhibit crosstalk of −37.59 dB and −34.67 dB at 1550 nm, respectively. Additionally, they demonstrate crosstalk of < −30 dB for the C-band. This suggests the potential for further scalability in terms of port counts. The switches are designed using the eigenmode expansion method, and the micro heater is designed with a finite element heat transfer solver. These advantages and excellent performance make the device a promising candidate for use in advanced communication systems and photonic integrated circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"216-223"},"PeriodicalIF":2.1,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1109/TNANO.2025.3556856
E. Miranda;E. Piros;F. L. Aguirre;T. Kim;P. Schreyer;J. Gehrunger;T. Schwarz;T. Oster;K. Hofmann;J. Suñé;C. Hochberger;L. Alff
We investigate in this letter the role the voltage ramp rate plays in the conduction and programming characteristics of bipolar-type memristive devices. It is shown that speeding up the writing or erasing process of a memristor is beneficial in terms of energy consumption but has a side cost associated with power dissipation. This happens because of the dynamical aspects of the set and reset transitions which are ultimately dictated by the physics of metal ions and oxygen vacancies migration. It is shown that by adding a constant base voltage to the voltage sweep, shorter programming times can be achieved but no significant impact on the power dissipation-energy consumption relationship is observed. Modeling and simulations are carried out with the aid of the Dynamic Memdiode Model and its implementation in LTspice using the Method of Elementary Solvers. Since the device model parameters and simulation conditions can vary in a wide range, the complete schematics are provided so that the interested readers can test different casuistries by themselves.
{"title":"Analysis of the Voltage Ramp Rate Effects on the Programming Characteristics of Bipolar-Type Memristive Devices","authors":"E. Miranda;E. Piros;F. L. Aguirre;T. Kim;P. Schreyer;J. Gehrunger;T. Schwarz;T. Oster;K. Hofmann;J. Suñé;C. Hochberger;L. Alff","doi":"10.1109/TNANO.2025.3556856","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3556856","url":null,"abstract":"We investigate in this letter the role the voltage ramp rate plays in the conduction and programming characteristics of bipolar-type memristive devices. It is shown that speeding up the writing or erasing process of a memristor is beneficial in terms of energy consumption but has a side cost associated with power dissipation. This happens because of the dynamical aspects of the set and reset transitions which are ultimately dictated by the physics of metal ions and oxygen vacancies migration. It is shown that by adding a constant base voltage to the voltage sweep, shorter programming times can be achieved but no significant impact on the power dissipation-energy consumption relationship is observed. Modeling and simulations are carried out with the aid of the Dynamic Memdiode Model and its implementation in LTspice using the Method of Elementary Solvers. Since the device model parameters and simulation conditions can vary in a wide range, the complete schematics are provided so that the interested readers can test different casuistries by themselves.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"205-208"},"PeriodicalIF":2.1,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947287","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Among the various Backside Interconnections (BSI) methods, Direct Backside Contact (DBC) is essential in minimizing the area of logic standard cells and SRAM bitcells with 3-dimensional Stacked FETs (3DSFET) beyond the 1 nm node. Additionally, from an SRAM design perspective, the DBC structure offers the advantage of allowing the use of NMOS for the Pass-Gate (PG) transistor, as was done previously. In this study, we demonstrated SRAM transistors operation by adopting the highly promising 3DSFET with DBC structure. And we validated the SRAM bitcell operation through TCAD simulation by applying hardware verification of the SRAM transistor. As a result, we can propose an innovative structure that is compatible with both logic transistor performance and SRAM bitcell configuration beyond 1 nm node.
{"title":"Development of SRAM in 3-Dimensional Stacked FET With Direct Backside Contact Beyond 1Nm Node","authors":"Mingyu Kim;Ilho Myeong;Jaehyun Park;Sungil Park;Deukho Yeon;Daewon Ha;Hyungcheol Shin","doi":"10.1109/TNANO.2025.3552308","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552308","url":null,"abstract":"Among the various Backside Interconnections (BSI) methods, Direct Backside Contact (DBC) is essential in minimizing the area of logic standard cells and SRAM bitcells with 3-dimensional Stacked FETs (3DSFET) beyond the 1 nm node. Additionally, from an SRAM design perspective, the DBC structure offers the advantage of allowing the use of NMOS for the Pass-Gate (PG) transistor, as was done previously. In this study, we demonstrated SRAM transistors operation by adopting the highly promising 3DSFET with DBC structure. And we validated the SRAM bitcell operation through TCAD simulation by applying hardware verification of the SRAM transistor. As a result, we can propose an innovative structure that is compatible with both logic transistor performance and SRAM bitcell configuration beyond 1 nm node.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"201-204"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143808878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/TNANO.2025.3552433
Yijun Cui;Jiang Li;Chongyan Gu;Chenghua Wang;Weiqiang Liu
Resistive random access memory (RRAM) presents a promising solution for energy-efficient logic-in-memory (LiM) systems. This paper introduces a Multi-mode Configurable Physical Unclonable Function (MC-PUF) tailored for secure RRAM-based LiM applications, utilizing a conventional one-transistor-one-RRAM (1T1R) array. The MC-PUF operates in multiple modes by modifying the programming voltages of the RRAM, which captures the distinct variations of each RRAM under varying conditions. In weak write mode, the MC-PUF exploits the inherent variations of RRAM by setting the programming voltages to achieve a 50% switching probability, thereby randomly assigning ‘0’ or ‘1’ states. In parallel competition mode, it generates responses by selecting two parallel RRAMs, with one remaining in a high resistance state (HRS) and the other switching to a low resistance state (LRS). This configuration allows the MC-PUF to generate more challenge-response pairs (CRPs) compared to conventional designs, thus enhancing security through increased entropy. The design was validated through simulations using a compact Spice model and the UMC 55 nm CMOS library, as well as on an experimental hardware platform with commercial RRAM chips. Results from both simulations and hardware implementations indicate that the proposed MC-PUF exhibits high reliability, excellent uniqueness, and superior configurability.
{"title":"A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage","authors":"Yijun Cui;Jiang Li;Chongyan Gu;Chenghua Wang;Weiqiang Liu","doi":"10.1109/TNANO.2025.3552433","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552433","url":null,"abstract":"Resistive random access memory (RRAM) presents a promising solution for energy-efficient logic-in-memory (LiM) systems. This paper introduces a Multi-mode Configurable Physical Unclonable Function (MC-PUF) tailored for secure RRAM-based LiM applications, utilizing a conventional one-transistor-one-RRAM (1T1R) array. The MC-PUF operates in multiple modes by modifying the programming voltages of the RRAM, which captures the distinct variations of each RRAM under varying conditions. In weak write mode, the MC-PUF exploits the inherent variations of RRAM by setting the programming voltages to achieve a 50% switching probability, thereby randomly assigning ‘0’ or ‘1’ states. In parallel competition mode, it generates responses by selecting two parallel RRAMs, with one remaining in a high resistance state (HRS) and the other switching to a low resistance state (LRS). This configuration allows the MC-PUF to generate more challenge-response pairs (CRPs) compared to conventional designs, thus enhancing security through increased entropy. The design was validated through simulations using a compact Spice model and the UMC 55 nm CMOS library, as well as on an experimental hardware platform with commercial RRAM chips. Results from both simulations and hardware implementations indicate that the proposed MC-PUF exhibits high reliability, excellent uniqueness, and superior configurability.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"166-177"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/TNANO.2025.3552525
Himanshu R. Das;Haraprasad Mondal;Rajeev Kumar
Plasmonic based electro-absorption modulators (EAMs) has paved the way for high-speed photonic integrated circuits (PICs). This paper demonstrates the numerical analysis and the structural design of the EAM using various plasmonic materials, such as vanadium dioxide (VO2), indium-tin-oxide (ITO) and graphene, to modulate signals traveling through the waveguide on an SiO2 platform. It also explores key performance metrics, including the extinction ratio (ER) and the figure-of-merit (FOM), which is related to the device's insertion loss (IL). By optimizing the structural parameters and utilizing the plasmonic materials, the device characteristics, especially the effective-mode-index (EMI), is modified to attain the epsilon-near-zero (ENZ) condition. The ITO-based EAM attains a high ER of 22.24 dB/μm with a FOM of 482.45, while the graphene-ITO based EAM obtains an ER of 20.31 dB/μm and a FOM of 296.06 at 1.55 μm wavelength. Both devices have an energy consumption per bit (Ebit) below 2.20 fJ/bit and modulation frequency ($f$) exceeding 1300 GHz at an IL $< $ 0.07 dB/μm. The investigated EAMs hold potential for future-generation PICs.
{"title":"Realization of Compact High-Performance EAM Based on Numerical Analysis of ITO, VO2 and Graphene on SiO2 Platform","authors":"Himanshu R. Das;Haraprasad Mondal;Rajeev Kumar","doi":"10.1109/TNANO.2025.3552525","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552525","url":null,"abstract":"Plasmonic based electro-absorption modulators (EAMs) has paved the way for high-speed photonic integrated circuits (PICs). This paper demonstrates the numerical analysis and the structural design of the EAM using various plasmonic materials, such as vanadium dioxide (VO<sub>2</sub>), indium-tin-oxide (ITO) and graphene, to modulate signals traveling through the waveguide on an SiO<sub>2</sub> platform. It also explores key performance metrics, including the extinction ratio (ER) and the figure-of-merit (FOM), which is related to the device's insertion loss (IL). By optimizing the structural parameters and utilizing the plasmonic materials, the device characteristics, especially the effective-mode-index (EMI), is modified to attain the epsilon-near-zero (ENZ) condition. The ITO-based EAM attains a high ER of 22.24 dB/μm with a FOM of 482.45, while the graphene-ITO based EAM obtains an ER of 20.31 dB/μm and a FOM of 296.06 at 1.55 μm wavelength. Both devices have an energy consumption per bit (E<sub>bit</sub>) below 2.20 fJ/bit and modulation frequency (<inline-formula><tex-math>$f$</tex-math></inline-formula>) exceeding 1300 GHz at an IL <inline-formula><tex-math>$< $</tex-math></inline-formula> 0.07 dB/μm. The investigated EAMs hold potential for future-generation PICs.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"178-188"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Triplet Networks (TNs) consist of three subchannels and are widely utilized in machine learning applications. The efficacy of TNs is highly dependent on the loss function employed during training. This paper proposes a novel loss function for TNs, referred to as the Adaptive Separately Constrained Triplet Loss (A-SCTL). The unique feature of A-SCTL is the separation of intra-class and inter-class constraints, strictly adhering to the objective of similarity-measuring networks. Its adaptive strategy leverages the dynamics between inter-class and intra-class terms to achieve a balanced convergence; without manually adjusting hyperparameters, it enhances flexibility and facilitates adaptation across various applications. Moreover, A-SCTL mitigates possible false solutions and offers insights into network behavior through the dependency of the two constraint terms. Performance metrics of the loss functions are evaluated in deep metric learning classification and face recognition tasks. Simulations illustrate the evolution of the two loss terms and the adaptive hyperparameter across training epochs; the results demonstrate that TNs utilizing A-SCTL outperform other existing loss functions in accuracy. Additionally, this paper details the hardware implementation of A-SCTL and evaluates its associated overhead. Results show that compared to other losses, the additional hardware overhead required for A-SCTL is negligible (0.008% energy per operation) when considering the entire TN system.
{"title":"Adaptive Separately Constrained Triplet Loss (A-SCTL) for High-Performance Triplet Networks","authors":"Ziheng Wang;Farzad Niknia;Shanshan Liu;Honglan Jiang;Siting Liu;Pedro Reviriego;Jun Zhou;Fabrizio Lombardi","doi":"10.1109/TNANO.2025.3552233","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552233","url":null,"abstract":"Triplet Networks (TNs) consist of three subchannels and are widely utilized in machine learning applications. The efficacy of TNs is highly dependent on the loss function employed during training. This paper proposes a novel loss function for TNs, referred to as the Adaptive Separately Constrained Triplet Loss (A-SCTL). The unique feature of A-SCTL is the separation of intra-class and inter-class constraints, strictly adhering to the objective of similarity-measuring networks. Its adaptive strategy leverages the dynamics between inter-class and intra-class terms to achieve a balanced convergence; without manually adjusting hyperparameters, it enhances flexibility and facilitates adaptation across various applications. Moreover, A-SCTL mitigates possible false solutions and offers insights into network behavior through the dependency of the two constraint terms. Performance metrics of the loss functions are evaluated in deep metric learning classification and face recognition tasks. Simulations illustrate the evolution of the two loss terms and the adaptive hyperparameter across training epochs; the results demonstrate that TNs utilizing A-SCTL outperform other existing loss functions in accuracy. Additionally, this paper details the hardware implementation of A-SCTL and evaluates its associated overhead. Results show that compared to other losses, the additional hardware overhead required for A-SCTL is negligible (0.008% energy per operation) when considering the entire TN system.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"157-165"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/TNANO.2025.3553037
Osama Yousuf;Andreu L. Glasmann;Alexander L. Mazzoni;Sina Najmaei;Gina C. Adam
Hardware accelerators based on emerging device technologies are gaining traction for inference workloads, but effective methods for their training remain an open area of research. We propose an efficient hardware-aware methodology for training neural networks with ternary weights that are mappable to emerging memory device arrays. We study device-network interactions across a variety of scenarios using simulated and experimentally measured datasets from ferroelectric field-effect transistor (FeFET) devices with varying characteristics. We quantify the impact of device non-idealities on network training by investigating device-level metrics, network-level metrics, loss landscapes, as well as parameter optimization trajectories. We validate our approach by mapping a hardware-aware solution to an emulated system with parameters calibrated to experimental measurements, highlighting several trade-offs. Hardware-aware training results on FeFET-based multi-layer perceptron networks, long short-term memory networks, and deep convolutional networks demonstrate competitive performance at lower overheads compared to existing schemes, indicating architectural and computational scalability. It is found that devices with low variability, non-linearity, and high dynamic range exhibit training characteristics closest to a software baseline. We provide evidence that device non-idealities inject noise during backpropagation, leading to sharper loss landscapes and higher-dimensional optimization trajectories, which make device networks more difficult to train than software counterparts. We also identify optimal operating voltages for investigated devices by utilizing our hardware-aware training and inference methodologies.
{"title":"Robust Hardware-Aware Neural Networks for FeFET-Based Accelerators","authors":"Osama Yousuf;Andreu L. Glasmann;Alexander L. Mazzoni;Sina Najmaei;Gina C. Adam","doi":"10.1109/TNANO.2025.3553037","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3553037","url":null,"abstract":"Hardware accelerators based on emerging device technologies are gaining traction for inference workloads, but effective methods for their training remain an open area of research. We propose an efficient hardware-aware methodology for training neural networks with ternary weights that are mappable to emerging memory device arrays. We study device-network interactions across a variety of scenarios using simulated and experimentally measured datasets from ferroelectric field-effect transistor (FeFET) devices with varying characteristics. We quantify the impact of device non-idealities on network training by investigating device-level metrics, network-level metrics, loss landscapes, as well as parameter optimization trajectories. We validate our approach by mapping a hardware-aware solution to an emulated system with parameters calibrated to experimental measurements, highlighting several trade-offs. Hardware-aware training results on FeFET-based multi-layer perceptron networks, long short-term memory networks, and deep convolutional networks demonstrate competitive performance at lower overheads compared to existing schemes, indicating architectural and computational scalability. It is found that devices with low variability, non-linearity, and high dynamic range exhibit training characteristics closest to a software baseline. We provide evidence that device non-idealities inject noise during backpropagation, leading to sharper loss landscapes and higher-dimensional optimization trajectories, which make device networks more difficult to train than software counterparts. We also identify optimal operating voltages for investigated devices by utilizing our hardware-aware training and inference methodologies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"189-200"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143808879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-12DOI: 10.1109/TNANO.2025.3569071
Jiang Li;Yijun Cui;Chenghua Wang;Chongyan Gu;Weiqiang Liu
Emerging nano-device resistive random access memories (RRAMs) have become a promising primitive for PUF designs due to their non-volatility, high density, and low power, breaking through the physical limitations. A ring oscillator based physical unclonable function (RO PUF) is one of the most widely studied PUF designs due to its resilience against noise impacts and flexibility of implementation, but its reliability is susceptible to environmental variation and device aging. Present solutions to improve RO PUF reliability either require complicated RO selection algorithms or require discarding a large number of unstable challenge-response pairs (CRPs). This paper presents a highly reliable RRAM-based configurable RO PUF (RCRO-PUF). The proposed RCRO-PUF utilizes the intrinsic variations of RRAMs as the randomness source and applies the resistance variations of RRAMs to the frequency difference of current-starved (CS) ROs. By operating CS inverters in the subthreshold region, the RCRO-PUF achieves low power as well as high reliability. In addition, a reliability enhancement scheme is proposed to eliminate the effects of environmental variations and device aging. Based on Monte Carlo simulations of a 65 nm CMOS process, the proposed RCRO-PUF consumes only 16.18% of the hardware overhead for a regular RO PUF and has only 7.43 $mu W$ per CRP generation. The reliability of the RCRO-PUF is 99.51% over a broad range of temperatures from $-50,^{circ }$C to $150,^{circ }$C and $pm$20% supply voltage variations. It is also 4.7× more resilient to aging than state-of-the-art aging-resilient RO PUF.
{"title":"A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience","authors":"Jiang Li;Yijun Cui;Chenghua Wang;Chongyan Gu;Weiqiang Liu","doi":"10.1109/TNANO.2025.3569071","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3569071","url":null,"abstract":"Emerging nano-device resistive random access memories (RRAMs) have become a promising primitive for PUF designs due to their non-volatility, high density, and low power, breaking through the physical limitations. A ring oscillator based physical unclonable function (RO PUF) is one of the most widely studied PUF designs due to its resilience against noise impacts and flexibility of implementation, but its reliability is susceptible to environmental variation and device aging. Present solutions to improve RO PUF reliability either require complicated RO selection algorithms or require discarding a large number of unstable challenge-response pairs (CRPs). This paper presents a highly reliable RRAM-based configurable RO PUF (RCRO-PUF). The proposed RCRO-PUF utilizes the intrinsic variations of RRAMs as the randomness source and applies the resistance variations of RRAMs to the frequency difference of current-starved (CS) ROs. By operating CS inverters in the subthreshold region, the RCRO-PUF achieves low power as well as high reliability. In addition, a reliability enhancement scheme is proposed to eliminate the effects of environmental variations and device aging. Based on Monte Carlo simulations of a 65 nm CMOS process, the proposed RCRO-PUF consumes only 16.18% of the hardware overhead for a regular RO PUF and has only 7.43 <inline-formula><tex-math>$mu W$</tex-math></inline-formula> per CRP generation. The reliability of the RCRO-PUF is 99.51% over a broad range of temperatures from <inline-formula><tex-math>$-50,^{circ }$</tex-math></inline-formula>C to <inline-formula><tex-math>$150,^{circ }$</tex-math></inline-formula>C and <inline-formula><tex-math>$pm$</tex-math></inline-formula>20% supply voltage variations. It is also 4.7× more resilient to aging than state-of-the-art aging-resilient RO PUF.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"293-306"},"PeriodicalIF":2.1,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144125448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-11DOI: 10.1109/TNANO.2025.3549522
T. Cusati;D. Marian;A. Toral-Lopez;E. G. Marin;G. Iannaccone;G. Fiori
We investigate the exploitation of one of the latest advancements in the processing of the two-dimensional materials (2DMs) lateral heterostructures (LH) for electronic applications, which involves the generation of subnanometer one-dimensional (1D) channels embedded in a 2D crystal. Such study is done through a multiscale approach combining Density Functional Theory (DFT) and quantum transport calculations to propose and evaluate various Field-Effect Transistors (FETs) based on LH incorporating one-dimensional MoS$_{2}$ channels within monolayer WSe$_{2}$. We assess the ultimate performance of the transistors by considering different device configurations, lengths and orientations.
{"title":"Transistors With MoS$_{2}$ Subnanometer Channels Embedded in 2D WSe$_{2}$","authors":"T. Cusati;D. Marian;A. Toral-Lopez;E. G. Marin;G. Iannaccone;G. Fiori","doi":"10.1109/TNANO.2025.3549522","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3549522","url":null,"abstract":"We investigate the exploitation of one of the latest advancements in the processing of the two-dimensional materials (2DMs) lateral heterostructures (LH) for electronic applications, which involves the generation of subnanometer one-dimensional (1D) channels embedded in a 2D crystal. Such study is done through a multiscale approach combining Density Functional Theory (DFT) and quantum transport calculations to propose and evaluate various Field-Effect Transistors (FETs) based on LH incorporating one-dimensional MoS<inline-formula><tex-math>$_{2}$</tex-math></inline-formula> channels within monolayer WSe<inline-formula><tex-math>$_{2}$</tex-math></inline-formula>. We assess the ultimate performance of the transistors by considering different device configurations, lengths and orientations.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"152-156"},"PeriodicalIF":2.1,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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