Pub Date : 2025-04-29DOI: 10.1109/TNANO.2025.3565276
Amit Verma;Reza Nekovei;Daryoush Shiri
We report on the presence of a Negative Differential Resistance (NDR) in a Gate-All-Around Field Effect Transistor (GAAFET) with 1D nanowires or nanotubes as the active conducting channel. Here, the drain current is seen to decrease sharply at relatively higher gate voltages. The onset of NDR is tunable with device topology. The NDR mechanism in this work is due to the applied gate voltage, not the drain-source voltage, a feature which promises low-voltage application of this effect. The results are based on a self-consistent ensemble Monte Carlo charge-carrier transport model with an electrostatic solver that solves Gauss's law in integral form.
{"title":"Room Temperature Negative Differential Resistance in Gate-All-Around Field-Effect Transistors With 1D Active Channels","authors":"Amit Verma;Reza Nekovei;Daryoush Shiri","doi":"10.1109/TNANO.2025.3565276","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3565276","url":null,"abstract":"We report on the presence of a Negative Differential Resistance (NDR) in a Gate-All-Around Field Effect Transistor (GAAFET) with 1D nanowires or nanotubes as the active conducting channel. Here, the drain current is seen to decrease sharply at relatively higher gate voltages. The onset of NDR is tunable with device topology. The NDR mechanism in this work is due to the applied gate voltage, not the drain-source voltage, a feature which promises low-voltage application of this effect. The results are based on a self-consistent ensemble Monte Carlo charge-carrier transport model with an electrostatic solver that solves Gauss's law in integral form.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"260-263"},"PeriodicalIF":2.1,"publicationDate":"2025-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143943966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-17DOI: 10.1109/TNANO.2025.3561947
Madhulika Verma;Sachin Agrawal
In human being autoimmune diseases are caused by the immune system's attack on body tissues. Therefore, advanced diagnostic tools for their early and accurate detection is highly needed. This study introduces a new underlay metal strip loaded doping-less heterojunction (GaSb/Si) TFET biosensor (UMS-DL-HJ-TFETB) device with exceptional sensitivity and performance. Key design features include an underlay metal strip for improved tunnelling and the cavities are on the source region to achieve a peak drain current sensitivity of 6.7 × 10$^{10}$ at k = 12 and V$_{gs}$ = 0.45 V. With a cut-off frequency of 3.27 × 10$^{8}$ Hz and a response time of 496 ps, the proposed biosensor exhibits excellent RF performance. The device performance in detecting DNA charge densities ranging from $pm$1 × 10$^{11}$ cm$^{-2}$ to $pm$1 × 10$^{12}$ cm$^{-2}$ has also been studied. In addition, five non-uniform distributions which is caused by the steric hindrance effect have been optimized. A comparative analysis is also done for fair evaluation. The simulation results show that the proposed biosensor addresses the limitations of conventional methods, providing high sensitivity, rapid detection and reliable diagnostic accuracy for autoimmune diseases.
{"title":"A Novel Underlay Metal Strip Loaded Doping-Less Heterojunction (GaSb/Si) TFET Biosensor for Autoimmune Disease Detection","authors":"Madhulika Verma;Sachin Agrawal","doi":"10.1109/TNANO.2025.3561947","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3561947","url":null,"abstract":"In human being autoimmune diseases are caused by the immune system's attack on body tissues. Therefore, advanced diagnostic tools for their early and accurate detection is highly needed. This study introduces a new underlay metal strip loaded doping-less heterojunction (GaSb/Si) TFET biosensor (UMS-DL-HJ-TFETB) device with exceptional sensitivity and performance. Key design features include an underlay metal strip for improved tunnelling and the cavities are on the source region to achieve a peak drain current sensitivity of 6.7 × 10<inline-formula><tex-math>$^{10}$</tex-math></inline-formula> at k = 12 and V<inline-formula><tex-math>$_{gs}$</tex-math></inline-formula> = 0.45 V. With a cut-off frequency of 3.27 × 10<inline-formula><tex-math>$^{8}$</tex-math></inline-formula> Hz and a response time of 496 ps, the proposed biosensor exhibits excellent RF performance. The device performance in detecting DNA charge densities ranging from <inline-formula><tex-math>$pm$</tex-math></inline-formula>1 × 10<inline-formula><tex-math>$^{11}$</tex-math></inline-formula> cm<inline-formula><tex-math>$^{-2}$</tex-math></inline-formula> to <inline-formula><tex-math>$pm$</tex-math></inline-formula>1 × 10<inline-formula><tex-math>$^{12}$</tex-math></inline-formula> cm<inline-formula><tex-math>$^{-2}$</tex-math></inline-formula> has also been studied. In addition, five non-uniform distributions which is caused by the steric hindrance effect have been optimized. A comparative analysis is also done for fair evaluation. The simulation results show that the proposed biosensor addresses the limitations of conventional methods, providing high sensitivity, rapid detection and reliable diagnostic accuracy for autoimmune diseases.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"239-248"},"PeriodicalIF":2.1,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-15DOI: 10.1109/TNANO.2025.3560912
Bipul Boro;Rushik Parmar;Gaurav Trivedi
Artificial Intelligence (AI) has advanced to the stage where modern problems can be transformed into AI problems with computational costs. Increased complexity has exponentially raised computation and inference demands, primarily due to Von Neumann architecture limitations. In-memory computing (IMC) revolutionizes this paradigm by eliminating memory read-write overheads. Notably, the utilization of Resistive Random Access Memory (RRAM) in vector-matrix multiplication (VMM) configurations within IMC architectures has demonstrated substantial performance enhancements. In the proposed work, utilizing Digital-to-Time Converters (DTCs) and Time-to-Digital Converters (TDCs) optimizes hardware resources substantially within in-memory computing (IMC) architectures. Our proposed DTC and TDC blocks exhibit power consumptions of $41 mu text{W}$ and $38 mu text{W}$ and delays of $896 text{ps}$ and $530 text{ps}$. Additionally, we introduce a $4T-1R$ structure with Reset Stop Block (RSB) that facilitates 2-bit RRAM reprogramming and entails a latency of $1.07 mu text{s}$ and energy/cell of $0.11 text{pJ}$. The overall energy efficiency of Time-Domain VMM (TDVMM) architecture is $866.6 text{Tops/W}$, which is $1.61 times$ more efficient than contemporary TDVMMs. Furthermore, our design consistently performs with a cycle-to-cycle variability of 23%, showcasing its tolerance to variations.
人工智能（AI）已经发展到可以将现代问题转化为具有计算成本的AI问题的阶段。增加的复杂性使计算和推理需求呈指数级增长，这主要是由于冯·诺依曼架构的限制。内存计算（IMC）通过消除内存读写开销彻底改变了这种范式。值得注意的是，在IMC架构中的矢量矩阵乘法（VMM）配置中使用电阻性随机存取存储器（RRAM）已经证明了显著的性能增强。在提出的工作中，利用数字到时间转换器（dtc）和时间到数字转换器（tdc）在内存计算（IMC）架构中大大优化了硬件资源。我们提出的DTC和TDC块的功耗分别为$41 mu text{W}$和$38 mu text{W}$，延迟分别为$896 text{ps}$和$530 text{ps}$。此外，我们引入了一个带有复位停止块（RSB）的$4T-1R$结构，促进了2位RRAM重编程，并且需要$1.07 mu text{s}$的延迟和$0.11 text{pJ}$的能量/单元。时域VMM （TDVMM）架构的整体能源效率为$866.6 text{Tops/W}$，比当代TDVMM效率高$1.61 $。此外，我们的设计始终以23%的周期变异性执行，展示了其对变化的容忍度。
{"title":"Vector-Matrix Multiplier Architecture for In-Memory Computing Applications With RRAM Arrays","authors":"Bipul Boro;Rushik Parmar;Gaurav Trivedi","doi":"10.1109/TNANO.2025.3560912","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3560912","url":null,"abstract":"Artificial Intelligence (AI) has advanced to the stage where modern problems can be transformed into AI problems with computational costs. Increased complexity has exponentially raised computation and inference demands, primarily due to Von Neumann architecture limitations. In-memory computing (IMC) revolutionizes this paradigm by eliminating memory read-write overheads. Notably, the utilization of Resistive Random Access Memory (RRAM) in vector-matrix multiplication (VMM) configurations within IMC architectures has demonstrated substantial performance enhancements. In the proposed work, utilizing Digital-to-Time Converters (DTCs) and Time-to-Digital Converters (TDCs) optimizes hardware resources substantially within in-memory computing (IMC) architectures. Our proposed DTC and TDC blocks exhibit power consumptions of <inline-formula><tex-math>$41 mu text{W}$</tex-math></inline-formula> and <inline-formula><tex-math>$38 mu text{W}$</tex-math></inline-formula> and delays of <inline-formula><tex-math>$896 text{ps}$</tex-math></inline-formula> and <inline-formula><tex-math>$530 text{ps}$</tex-math></inline-formula>. Additionally, we introduce a <inline-formula><tex-math>$4T-1R$</tex-math></inline-formula> structure with Reset Stop Block (RSB) that facilitates 2-bit RRAM reprogramming and entails a latency of <inline-formula><tex-math>$1.07 mu text{s}$</tex-math></inline-formula> and energy/cell of <inline-formula><tex-math>$0.11 text{pJ}$</tex-math></inline-formula>. The overall energy efficiency of Time-Domain VMM (TDVMM) architecture is <inline-formula><tex-math>$866.6 text{Tops/W}$</tex-math></inline-formula>, which is <inline-formula><tex-math>$1.61 times$</tex-math></inline-formula> more efficient than contemporary TDVMMs. Furthermore, our design consistently performs with a cycle-to-cycle variability of 23%, showcasing its tolerance to variations.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"249-259"},"PeriodicalIF":2.1,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143929831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-14DOI: 10.1109/TNANO.2025.3560672
N. Aruna Kumari;Brajesh Kumar Kaushik
In this article, a comprehensive performance analysis of the emerging and novel TreeFET is demonstrated at 3-nm technology node. The TreeFET is realized by combining nanosheet FET (NSFET) and fin-like interbridge (IB) structures. Initially, the TreeFET is compared with traditional NSFET under the same footprint (FP). The ON current (ION) and switching ratio (ION/IOFF) enhance with TreeFET by 56% and 35.4% compared to the NSFET with matched OFF current (IOFF). Further, the dimensional impact of TreeFET is studied in detail by altering the geometry of IB. On top of that, as the IB height (HIB) is a crucial metric for deciding the performance, the impact of HIB on analog/RF performance is also studied. Although the parasitic capacitance rises with higher HIB, better RF performance is observed with HIB of 30 nm compared to 10 nm due to the significant increase in ON current. Further, it is noted that the electrical performance is degraded with the rise in temperature. Moreover, the circuit level demonstration of TreeFET is carried out at both HIB of 10 nm and 30 nm for the CMOS inverter and ring oscillator (RO). The CMOS inverter switching current (ISC), power-delay product (PDP), and energy-delay product (EDP) are increased by 1.61×, 53%, and 38%, respectively with an increase in HIB. However, for 19-stage RO, an improvement of 11.55% in oscillation frequency (fOSC) is noticed with HIB of 30 nm. Moreover, the PDP and EDP variations are presented for 19-stage RO with variations in HIB. The analysis enables a profound understanding of the performance of emerging TreeFET devices at both device and circuit levels.
{"title":"Comprehensive Analysis of TreeFET: A Circuit Perspective","authors":"N. Aruna Kumari;Brajesh Kumar Kaushik","doi":"10.1109/TNANO.2025.3560672","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3560672","url":null,"abstract":"In this article, a comprehensive performance analysis of the emerging and novel TreeFET is demonstrated at 3-nm technology node. The TreeFET is realized by combining nanosheet FET (NSFET) and fin-like interbridge (IB) structures. Initially, the TreeFET is compared with traditional NSFET under the same footprint (FP). The ON current (<italic>I</i><sub>ON</sub>) and switching ratio (<italic>I</i><sub>ON</sub>/<italic>I</i><sub>OFF</sub>) enhance with TreeFET by 56% and 35.4% compared to the NSFET with matched OFF current (<italic>I</i><sub>OFF</sub>). Further, the dimensional impact of TreeFET is studied in detail by altering the geometry of IB. On top of that, as the IB height (<italic>H</i><sub>IB</sub>) is a crucial metric for deciding the performance, the impact of <italic>H</i><sub>IB</sub> on analog/RF performance is also studied. Although the parasitic capacitance rises with higher <italic>H</i><sub>IB</sub>, better RF performance is observed with <italic>H</i><sub>IB</sub> of 30 nm compared to 10 nm due to the significant increase in ON current. Further, it is noted that the electrical performance is degraded with the rise in temperature. Moreover, the circuit level demonstration of TreeFET is carried out at both <italic>H</i><sub>IB</sub> of 10 nm and 30 nm for the CMOS inverter and ring oscillator (RO). The CMOS inverter switching current (<italic>I</i><sub>SC</sub>), power-delay product (PDP), and energy-delay product (EDP) are increased by 1.61×, 53%, and 38%, respectively with an increase in <italic>H</i><sub>IB</sub>. However, for 19-stage RO, an improvement of 11.55% in oscillation frequency (<italic>f</i><sub>OSC</sub>) is noticed with <italic>H</i><sub>IB</sub> of 30 nm. Moreover, the PDP and EDP variations are presented for 19-stage RO with variations in <italic>H</i><sub>IB</sub>. The analysis enables a profound understanding of the performance of emerging TreeFET devices at both device and circuit levels.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"231-238"},"PeriodicalIF":2.1,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-04DOI: 10.1109/TNANO.2025.3558256
Devendra Chack;Gaurav Kumar
The advancement of future photonic integrated circuits for data center networks relies crucially on the development of highly efficient, low-power, and compact switches. This paper presents the design of non-blocking 4 × 4 and 8 × 8 silicon photonics switches intended using Multimode Interferometer (MMI)-Mach-Zehnder interferometer (MZI) structures. These proposed switches consist of 2 × 2 MMI-MZI switches realized by changing the phase of an optical signal using the thermo-optic effect. At 1550 nm, the proposed 2 × 2 switch exhibits an insertion loss of 0.04 dB and crosstalk of < 39.95 dB. Similarly, the C-band showcases an insertion loss of < 0.06 dB and crosstalk of < −33 dB. To support complex network topologies and enhance network efficiency, a data center network necessitates a higher quantity of port switches. The results show that at 1550 nm, the insertion loss for the 4 × 4 and 8 × 8 switches is 0.47 dB and 1.02 dB, respectively. Furthermore, the insertion loss for the C-band is < 0.50 dB and < 1.5 dB, respectively. The switches exhibit crosstalk of −37.59 dB and −34.67 dB at 1550 nm, respectively. Additionally, they demonstrate crosstalk of < −30 dB for the C-band. This suggests the potential for further scalability in terms of port counts. The switches are designed using the eigenmode expansion method, and the micro heater is designed with a finite element heat transfer solver. These advantages and excellent performance make the device a promising candidate for use in advanced communication systems and photonic integrated circuits.
{"title":"On-chip Non-Blocking 4 × 4 and 8 × 8 Photonic Switches Using MMI-MZI Configuration for Next-Generation Data Center Networks","authors":"Devendra Chack;Gaurav Kumar","doi":"10.1109/TNANO.2025.3558256","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3558256","url":null,"abstract":"The advancement of future photonic integrated circuits for data center networks relies crucially on the development of highly efficient, low-power, and compact switches. This paper presents the design of non-blocking 4 × 4 and 8 × 8 silicon photonics switches intended using Multimode Interferometer (MMI)-Mach-Zehnder interferometer (MZI) structures. These proposed switches consist of 2 × 2 MMI-MZI switches realized by changing the phase of an optical signal using the thermo-optic effect. At 1550 nm, the proposed 2 × 2 switch exhibits an insertion loss of 0.04 dB and crosstalk of < 39.95 dB. Similarly, the C-band showcases an insertion loss of < 0.06 dB and crosstalk of < −33 dB. To support complex network topologies and enhance network efficiency, a data center network necessitates a higher quantity of port switches. The results show that at 1550 nm, the insertion loss for the 4 × 4 and 8 × 8 switches is 0.47 dB and 1.02 dB, respectively. Furthermore, the insertion loss for the C-band is < 0.50 dB and < 1.5 dB, respectively. The switches exhibit crosstalk of −37.59 dB and −34.67 dB at 1550 nm, respectively. Additionally, they demonstrate crosstalk of < −30 dB for the C-band. This suggests the potential for further scalability in terms of port counts. The switches are designed using the eigenmode expansion method, and the micro heater is designed with a finite element heat transfer solver. These advantages and excellent performance make the device a promising candidate for use in advanced communication systems and photonic integrated circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"216-223"},"PeriodicalIF":2.1,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143892502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1109/TNANO.2025.3556856
E. Miranda;E. Piros;F. L. Aguirre;T. Kim;P. Schreyer;J. Gehrunger;T. Schwarz;T. Oster;K. Hofmann;J. Suñé;C. Hochberger;L. Alff
We investigate in this letter the role the voltage ramp rate plays in the conduction and programming characteristics of bipolar-type memristive devices. It is shown that speeding up the writing or erasing process of a memristor is beneficial in terms of energy consumption but has a side cost associated with power dissipation. This happens because of the dynamical aspects of the set and reset transitions which are ultimately dictated by the physics of metal ions and oxygen vacancies migration. It is shown that by adding a constant base voltage to the voltage sweep, shorter programming times can be achieved but no significant impact on the power dissipation-energy consumption relationship is observed. Modeling and simulations are carried out with the aid of the Dynamic Memdiode Model and its implementation in LTspice using the Method of Elementary Solvers. Since the device model parameters and simulation conditions can vary in a wide range, the complete schematics are provided so that the interested readers can test different casuistries by themselves.
{"title":"Analysis of the Voltage Ramp Rate Effects on the Programming Characteristics of Bipolar-Type Memristive Devices","authors":"E. Miranda;E. Piros;F. L. Aguirre;T. Kim;P. Schreyer;J. Gehrunger;T. Schwarz;T. Oster;K. Hofmann;J. Suñé;C. Hochberger;L. Alff","doi":"10.1109/TNANO.2025.3556856","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3556856","url":null,"abstract":"We investigate in this letter the role the voltage ramp rate plays in the conduction and programming characteristics of bipolar-type memristive devices. It is shown that speeding up the writing or erasing process of a memristor is beneficial in terms of energy consumption but has a side cost associated with power dissipation. This happens because of the dynamical aspects of the set and reset transitions which are ultimately dictated by the physics of metal ions and oxygen vacancies migration. It is shown that by adding a constant base voltage to the voltage sweep, shorter programming times can be achieved but no significant impact on the power dissipation-energy consumption relationship is observed. Modeling and simulations are carried out with the aid of the Dynamic Memdiode Model and its implementation in LTspice using the Method of Elementary Solvers. Since the device model parameters and simulation conditions can vary in a wide range, the complete schematics are provided so that the interested readers can test different casuistries by themselves.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"205-208"},"PeriodicalIF":2.1,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947287","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143845471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Among the various Backside Interconnections (BSI) methods, Direct Backside Contact (DBC) is essential in minimizing the area of logic standard cells and SRAM bitcells with 3-dimensional Stacked FETs (3DSFET) beyond the 1 nm node. Additionally, from an SRAM design perspective, the DBC structure offers the advantage of allowing the use of NMOS for the Pass-Gate (PG) transistor, as was done previously. In this study, we demonstrated SRAM transistors operation by adopting the highly promising 3DSFET with DBC structure. And we validated the SRAM bitcell operation through TCAD simulation by applying hardware verification of the SRAM transistor. As a result, we can propose an innovative structure that is compatible with both logic transistor performance and SRAM bitcell configuration beyond 1 nm node.
{"title":"Development of SRAM in 3-Dimensional Stacked FET With Direct Backside Contact Beyond 1Nm Node","authors":"Mingyu Kim;Ilho Myeong;Jaehyun Park;Sungil Park;Deukho Yeon;Daewon Ha;Hyungcheol Shin","doi":"10.1109/TNANO.2025.3552308","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552308","url":null,"abstract":"Among the various Backside Interconnections (BSI) methods, Direct Backside Contact (DBC) is essential in minimizing the area of logic standard cells and SRAM bitcells with 3-dimensional Stacked FETs (3DSFET) beyond the 1 nm node. Additionally, from an SRAM design perspective, the DBC structure offers the advantage of allowing the use of NMOS for the Pass-Gate (PG) transistor, as was done previously. In this study, we demonstrated SRAM transistors operation by adopting the highly promising 3DSFET with DBC structure. And we validated the SRAM bitcell operation through TCAD simulation by applying hardware verification of the SRAM transistor. As a result, we can propose an innovative structure that is compatible with both logic transistor performance and SRAM bitcell configuration beyond 1 nm node.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"201-204"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143808878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/TNANO.2025.3552433
Yijun Cui;Jiang Li;Chongyan Gu;Chenghua Wang;Weiqiang Liu
Resistive random access memory (RRAM) presents a promising solution for energy-efficient logic-in-memory (LiM) systems. This paper introduces a Multi-mode Configurable Physical Unclonable Function (MC-PUF) tailored for secure RRAM-based LiM applications, utilizing a conventional one-transistor-one-RRAM (1T1R) array. The MC-PUF operates in multiple modes by modifying the programming voltages of the RRAM, which captures the distinct variations of each RRAM under varying conditions. In weak write mode, the MC-PUF exploits the inherent variations of RRAM by setting the programming voltages to achieve a 50% switching probability, thereby randomly assigning ‘0’ or ‘1’ states. In parallel competition mode, it generates responses by selecting two parallel RRAMs, with one remaining in a high resistance state (HRS) and the other switching to a low resistance state (LRS). This configuration allows the MC-PUF to generate more challenge-response pairs (CRPs) compared to conventional designs, thus enhancing security through increased entropy. The design was validated through simulations using a compact Spice model and the UMC 55 nm CMOS library, as well as on an experimental hardware platform with commercial RRAM chips. Results from both simulations and hardware implementations indicate that the proposed MC-PUF exhibits high reliability, excellent uniqueness, and superior configurability.
{"title":"A Multi-Mode Configurable Physical Unclonable Function Based on RRAM With Adjustable Programmable Voltage","authors":"Yijun Cui;Jiang Li;Chongyan Gu;Chenghua Wang;Weiqiang Liu","doi":"10.1109/TNANO.2025.3552433","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552433","url":null,"abstract":"Resistive random access memory (RRAM) presents a promising solution for energy-efficient logic-in-memory (LiM) systems. This paper introduces a Multi-mode Configurable Physical Unclonable Function (MC-PUF) tailored for secure RRAM-based LiM applications, utilizing a conventional one-transistor-one-RRAM (1T1R) array. The MC-PUF operates in multiple modes by modifying the programming voltages of the RRAM, which captures the distinct variations of each RRAM under varying conditions. In weak write mode, the MC-PUF exploits the inherent variations of RRAM by setting the programming voltages to achieve a 50% switching probability, thereby randomly assigning ‘0’ or ‘1’ states. In parallel competition mode, it generates responses by selecting two parallel RRAMs, with one remaining in a high resistance state (HRS) and the other switching to a low resistance state (LRS). This configuration allows the MC-PUF to generate more challenge-response pairs (CRPs) compared to conventional designs, thus enhancing security through increased entropy. The design was validated through simulations using a compact Spice model and the UMC 55 nm CMOS library, as well as on an experimental hardware platform with commercial RRAM chips. Results from both simulations and hardware implementations indicate that the proposed MC-PUF exhibits high reliability, excellent uniqueness, and superior configurability.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"166-177"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-18DOI: 10.1109/TNANO.2025.3552525
Himanshu R. Das;Haraprasad Mondal;Rajeev Kumar
Plasmonic based electro-absorption modulators (EAMs) has paved the way for high-speed photonic integrated circuits (PICs). This paper demonstrates the numerical analysis and the structural design of the EAM using various plasmonic materials, such as vanadium dioxide (VO2), indium-tin-oxide (ITO) and graphene, to modulate signals traveling through the waveguide on an SiO2 platform. It also explores key performance metrics, including the extinction ratio (ER) and the figure-of-merit (FOM), which is related to the device's insertion loss (IL). By optimizing the structural parameters and utilizing the plasmonic materials, the device characteristics, especially the effective-mode-index (EMI), is modified to attain the epsilon-near-zero (ENZ) condition. The ITO-based EAM attains a high ER of 22.24 dB/μm with a FOM of 482.45, while the graphene-ITO based EAM obtains an ER of 20.31 dB/μm and a FOM of 296.06 at 1.55 μm wavelength. Both devices have an energy consumption per bit (Ebit) below 2.20 fJ/bit and modulation frequency ($f$) exceeding 1300 GHz at an IL $< $ 0.07 dB/μm. The investigated EAMs hold potential for future-generation PICs.
{"title":"Realization of Compact High-Performance EAM Based on Numerical Analysis of ITO, VO2 and Graphene on SiO2 Platform","authors":"Himanshu R. Das;Haraprasad Mondal;Rajeev Kumar","doi":"10.1109/TNANO.2025.3552525","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552525","url":null,"abstract":"Plasmonic based electro-absorption modulators (EAMs) has paved the way for high-speed photonic integrated circuits (PICs). This paper demonstrates the numerical analysis and the structural design of the EAM using various plasmonic materials, such as vanadium dioxide (VO<sub>2</sub>), indium-tin-oxide (ITO) and graphene, to modulate signals traveling through the waveguide on an SiO<sub>2</sub> platform. It also explores key performance metrics, including the extinction ratio (ER) and the figure-of-merit (FOM), which is related to the device's insertion loss (IL). By optimizing the structural parameters and utilizing the plasmonic materials, the device characteristics, especially the effective-mode-index (EMI), is modified to attain the epsilon-near-zero (ENZ) condition. The ITO-based EAM attains a high ER of 22.24 dB/μm with a FOM of 482.45, while the graphene-ITO based EAM obtains an ER of 20.31 dB/μm and a FOM of 296.06 at 1.55 μm wavelength. Both devices have an energy consumption per bit (E<sub>bit</sub>) below 2.20 fJ/bit and modulation frequency (<inline-formula><tex-math>$f$</tex-math></inline-formula>) exceeding 1300 GHz at an IL <inline-formula><tex-math>$< $</tex-math></inline-formula> 0.07 dB/μm. The investigated EAMs hold potential for future-generation PICs.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"178-188"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Triplet Networks (TNs) consist of three subchannels and are widely utilized in machine learning applications. The efficacy of TNs is highly dependent on the loss function employed during training. This paper proposes a novel loss function for TNs, referred to as the Adaptive Separately Constrained Triplet Loss (A-SCTL). The unique feature of A-SCTL is the separation of intra-class and inter-class constraints, strictly adhering to the objective of similarity-measuring networks. Its adaptive strategy leverages the dynamics between inter-class and intra-class terms to achieve a balanced convergence; without manually adjusting hyperparameters, it enhances flexibility and facilitates adaptation across various applications. Moreover, A-SCTL mitigates possible false solutions and offers insights into network behavior through the dependency of the two constraint terms. Performance metrics of the loss functions are evaluated in deep metric learning classification and face recognition tasks. Simulations illustrate the evolution of the two loss terms and the adaptive hyperparameter across training epochs; the results demonstrate that TNs utilizing A-SCTL outperform other existing loss functions in accuracy. Additionally, this paper details the hardware implementation of A-SCTL and evaluates its associated overhead. Results show that compared to other losses, the additional hardware overhead required for A-SCTL is negligible (0.008% energy per operation) when considering the entire TN system.
{"title":"Adaptive Separately Constrained Triplet Loss (A-SCTL) for High-Performance Triplet Networks","authors":"Ziheng Wang;Farzad Niknia;Shanshan Liu;Honglan Jiang;Siting Liu;Pedro Reviriego;Jun Zhou;Fabrizio Lombardi","doi":"10.1109/TNANO.2025.3552233","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3552233","url":null,"abstract":"Triplet Networks (TNs) consist of three subchannels and are widely utilized in machine learning applications. The efficacy of TNs is highly dependent on the loss function employed during training. This paper proposes a novel loss function for TNs, referred to as the Adaptive Separately Constrained Triplet Loss (A-SCTL). The unique feature of A-SCTL is the separation of intra-class and inter-class constraints, strictly adhering to the objective of similarity-measuring networks. Its adaptive strategy leverages the dynamics between inter-class and intra-class terms to achieve a balanced convergence; without manually adjusting hyperparameters, it enhances flexibility and facilitates adaptation across various applications. Moreover, A-SCTL mitigates possible false solutions and offers insights into network behavior through the dependency of the two constraint terms. Performance metrics of the loss functions are evaluated in deep metric learning classification and face recognition tasks. Simulations illustrate the evolution of the two loss terms and the adaptive hyperparameter across training epochs; the results demonstrate that TNs utilizing A-SCTL outperform other existing loss functions in accuracy. Additionally, this paper details the hardware implementation of A-SCTL and evaluates its associated overhead. Results show that compared to other losses, the additional hardware overhead required for A-SCTL is negligible (0.008% energy per operation) when considering the entire TN system.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"157-165"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143769409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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