Pub Date : 2024-02-27DOI: 10.1109/TNANO.2024.3370717
R. Rajasekar
A novel photonic crystal nanoresonator-based optical bandpass filter is designed with ultra narrow bandwidth, high quality factor, low optical loss and very small compact size. The proposed S-Shaped nanostructure is playing a very significant role on narrow wavelength filtering and effectively localize the incident light signal which leads to the high-quality factor is obtained with 100% transmission. The different light coupling mechanism is used to realize the four dissimilar narrow bandpass filters. These nano-filter performance parameters are numerically investigated by Finite Difference Time Domain Method (FDTD). The nanoresonator coupled waveguides platform is designed with high quality factor as about 3873.70, ultra narrow bandwidth of 60 GHz and 0.13 THz. The presented photonics platform footprint is very compact as about 128.52 μm 2 . These enhanced results highly suitable for optical integrated circuits, 5G and 6G optical wireless network.
{"title":"Numerical Investigation of Nanoresonator Based Ultra Narrow-Band Photonic Filters","authors":"R. Rajasekar","doi":"10.1109/TNANO.2024.3370717","DOIUrl":"10.1109/TNANO.2024.3370717","url":null,"abstract":"A novel photonic crystal nanoresonator-based optical bandpass filter is designed with ultra narrow bandwidth, high quality factor, low optical loss and very small compact size. The proposed S-Shaped nanostructure is playing a very significant role on narrow wavelength filtering and effectively localize the incident light signal which leads to the high-quality factor is obtained with 100% transmission. The different light coupling mechanism is used to realize the four dissimilar narrow bandpass filters. These nano-filter performance parameters are numerically investigated by Finite Difference Time Domain Method (FDTD). The nanoresonator coupled waveguides platform is designed with high quality factor as about 3873.70, ultra narrow bandwidth of 60 GHz and 0.13 THz. The presented photonics platform footprint is very compact as about 128.52 μm\u0000<sup>2</sup>\u0000. These enhanced results highly suitable for optical integrated circuits, 5G and 6G optical wireless network.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"188-194"},"PeriodicalIF":2.4,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140006152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-27DOI: 10.1109/TNANO.2024.3370098
Hao Ding;Lan Chen;Wentao Huang
Carbon nanotube field-effect transistors (CNFETs) possess high current density and carrier mobility, enabling high intrinsic gains below the 20-nm technology node. Thus, they demonstrate superior performance compared to traditional silicon analog integrated circuits (ICs). Here, the relevant parameters of a CNFET in analog IC designs were analyzed and simulated, elucidating the influence of physical parameters on the CNFET device. All simulations were performed at technology nodes smaller than 22 nm. To evaluate the performance of a CNFET analog circuit, the g m /I d method for CNFET was employed, and a nanoscale two-stage operational amplifier was designed using complementary CNFET technology with a channel length of 14 nm. In addition, the impact of CNFET's physical parameters on circuit performance were examined. Our results showcased the advantages of CNFET analog circuits over traditional silicon-based analog circuits, as well as the significant influence of CNFET physical parameters on circuit performance. Consequently, this study provides a reference for productive CNFET technologies.
{"title":"Optimization of a Nanoscale Operational Amplifier Based on a Complementary Carbon Nanotube Field-Effect Transistor by Adjusting Physical Parameters","authors":"Hao Ding;Lan Chen;Wentao Huang","doi":"10.1109/TNANO.2024.3370098","DOIUrl":"10.1109/TNANO.2024.3370098","url":null,"abstract":"Carbon nanotube field-effect transistors (CNFETs) possess high current density and carrier mobility, enabling high intrinsic gains below the 20-nm technology node. Thus, they demonstrate superior performance compared to traditional silicon analog integrated circuits (ICs). Here, the relevant parameters of a CNFET in analog IC designs were analyzed and simulated, elucidating the influence of physical parameters on the CNFET device. All simulations were performed at technology nodes smaller than 22 nm. To evaluate the performance of a CNFET analog circuit, the g\u0000<sub>m</sub>\u0000/I\u0000<sub>d</sub>\u0000 method for CNFET was employed, and a nanoscale two-stage operational amplifier was designed using complementary CNFET technology with a channel length of 14 nm. In addition, the impact of CNFET's physical parameters on circuit performance were examined. Our results showcased the advantages of CNFET analog circuits over traditional silicon-based analog circuits, as well as the significant influence of CNFET physical parameters on circuit performance. Consequently, this study provides a reference for productive CNFET technologies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"180-187"},"PeriodicalIF":2.4,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140006157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-22DOI: 10.1109/TNANO.2024.3368628
Aokun Hu;Wenjie Li;Dongxu Lyu;Guanghui He
Stochastic computing (SC) has emerged as a promising technique for reducing hardware costs in various applications, particularly in multiply-accumulate (MAC) intensive tasks such as neural networks. However, conventional SC still faces challenges in terms of achieving high accuracy and throughput. To enhance the precision, Sobol bit-stream has been widely adopted in SC. On the other hand, the throughput is frequently increased by means of parallel computing architecture. Nevertheless, directly increasing parallelism will incur significant additional hardware costs. In this paper, we propose Pseudo-Sobol bit-streams based on which an efficient parallel stochastic computing architecture for MAC operations is further developed. The proposed design leverages the properties of Pseudo-Sobol bit-streams and integrates the computation and conversion units to improve hardware efficiency. We evaluate the effectiveness of our design in two typical applications, general matrix multiplication (GEMM) and convolution. Experimental results show that our proposed design is capable of increasing energy efficiency by up to 36% and area efficiency by up to 70%.
随机计算（SC）已成为在各种应用中降低硬件成本的一种有前途的技术，特别是在神经网络等多累积（MAC）密集型任务中。然而，传统的随机计算在实现高精度和高吞吐量方面仍面临挑战。为了提高精度，Sobol 比特流被广泛应用于 SC。另一方面，吞吐量经常通过并行计算架构来提高。然而，直接提高并行性会产生大量额外的硬件成本。在本文中，我们提出了伪 Sobol 比特流，并在此基础上进一步开发了用于 MAC 运算的高效并行随机计算架构。我们提出的设计充分利用了伪索波尔比特流的特性，并整合了计算和转换单元，从而提高了硬件效率。我们在通用矩阵乘法（GEMM）和卷积这两个典型应用中评估了设计的有效性。实验结果表明，我们提出的设计能够将能效提高 36%，面积效率提高 70%。
{"title":"Efficient Parallel Stochastic Computing Multiply-Accumulate (MAC) Technique Using Pseudo-Sobol Bit-Streams","authors":"Aokun Hu;Wenjie Li;Dongxu Lyu;Guanghui He","doi":"10.1109/TNANO.2024.3368628","DOIUrl":"10.1109/TNANO.2024.3368628","url":null,"abstract":"Stochastic computing (SC) has emerged as a promising technique for reducing hardware costs in various applications, particularly in multiply-accumulate (MAC) intensive tasks such as neural networks. However, conventional SC still faces challenges in terms of achieving high accuracy and throughput. To enhance the precision, Sobol bit-stream has been widely adopted in SC. On the other hand, the throughput is frequently increased by means of parallel computing architecture. Nevertheless, directly increasing parallelism will incur significant additional hardware costs. In this paper, we propose Pseudo-Sobol bit-streams based on which an efficient parallel stochastic computing architecture for MAC operations is further developed. The proposed design leverages the properties of Pseudo-Sobol bit-streams and integrates the computation and conversion units to improve hardware efficiency. We evaluate the effectiveness of our design in two typical applications, general matrix multiplication (GEMM) and convolution. Experimental results show that our proposed design is capable of increasing energy efficiency by up to 36% and area efficiency by up to 70%.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"170-179"},"PeriodicalIF":2.4,"publicationDate":"2024-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139950618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Inference and on-chip training of Artificial Neural Networks (ANNs) are challenging computational processes for large datasets; hardware implementations are needed to accelerate this computation, while meeting metrics such as operating frequency, power dissipation and accuracy. In this article, a high-performance ASIC-based design is proposed to implement both forward and backward propagations of multi-layer perceptrons (MLPs) at the nanoscales. To attain a higher accuracy, floating-point arithmetic units for a multiply-and-accumulate (MAC) array are employed in the proposed design; moreover, a hybrid implementation scheme is utilized to achieve flexibility (for networks of different size) and comprehensively low hardware overhead. The proposed design is fully pipelined, and its performance is independent of network size, except for the number of cycles and latency. The efficiency of the proposed nanoscale MLP-based design for inference (as taking place over multiple steps) and training (due to the complex processing in backward propagation by eliminating many redundant calculations) is analyzed. Moreover, the impact of different floating-point precision formats on the final accuracy and hardware metrics under the same design constraints is studied. A comparative evaluation of the proposed MLP design for different datasets and floating-point precision formats is provided. Results show that compared to current schemes found in the technical literatures, the proposed design has the best operating frequency and accuracy with still good latency and energy dissipation.
{"title":"ASIC Design of Nanoscale Artificial Neural Networks for Inference/Training by Floating-Point Arithmetic","authors":"Farzad Niknia;Ziheng Wang;Shanshan Liu;Pedro Reviriego;Ahmed Louri;Fabrizio Lombardi","doi":"10.1109/TNANO.2024.3367916","DOIUrl":"10.1109/TNANO.2024.3367916","url":null,"abstract":"Inference and on-chip training of Artificial Neural Networks (ANNs) are challenging computational processes for large datasets; hardware implementations are needed to accelerate this computation, while meeting metrics such as operating frequency, power dissipation and accuracy. In this article, a high-performance ASIC-based design is proposed to implement both forward and backward propagations of multi-layer perceptrons (MLPs) at the nanoscales. To attain a higher accuracy, floating-point arithmetic units for a multiply-and-accumulate (MAC) array are employed in the proposed design; moreover, a hybrid implementation scheme is utilized to achieve flexibility (for networks of different size) and comprehensively low hardware overhead. The proposed design is fully pipelined, and its performance is independent of network size, except for the number of cycles and latency. The efficiency of the proposed nanoscale MLP-based design for inference (as taking place over multiple steps) and training (due to the complex processing in backward propagation by eliminating many redundant calculations) is analyzed. Moreover, the impact of different floating-point precision formats on the final accuracy and hardware metrics under the same design constraints is studied. A comparative evaluation of the proposed MLP design for different datasets and floating-point precision formats is provided. Results show that compared to current schemes found in the technical literatures, the proposed design has the best operating frequency and accuracy with still good latency and energy dissipation.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"208-216"},"PeriodicalIF":2.4,"publicationDate":"2024-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139950623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-09DOI: 10.1109/TNANO.2024.3364254
E. M. Sheta;Azrul Azlan Hamzah;Umi Zulaikha Mohd Azmi;Ishak Mansor;Pankaj Kumar Choudhury
A layered metamaterial comprising periodic blue glass and FTO mediums was investigated for gamma (γ) radiation dosimetry. The device acts on the principle of absorption of the incidence radiation with sharp resonance absorption peaks which undergo shifts in the presence of γ-radiation. The more the radiation dose is, the more shift happens in the resonance absorption spectrum – the feature that can be exploited in the design of polarization insensitive γ-radiation dosimetry device.
{"title":"On the γ-Radiation Dosimetry Using a Layered Metamaterial Structure Comprising FTO and Blue Glass","authors":"E. M. Sheta;Azrul Azlan Hamzah;Umi Zulaikha Mohd Azmi;Ishak Mansor;Pankaj Kumar Choudhury","doi":"10.1109/TNANO.2024.3364254","DOIUrl":"10.1109/TNANO.2024.3364254","url":null,"abstract":"A layered metamaterial comprising periodic blue glass and FTO mediums was investigated for gamma (γ) radiation dosimetry. The device acts on the principle of absorption of the incidence radiation with sharp resonance absorption peaks which undergo shifts in the presence of γ-radiation. The more the radiation dose is, the more shift happens in the resonance absorption spectrum – the feature that can be exploited in the design of polarization insensitive γ-radiation dosimetry device.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"158-163"},"PeriodicalIF":2.4,"publicationDate":"2024-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139950622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a physics-based compact model for Voltage-Controlled Magnetic Anisotropy (VCMA) MRAM, calibrated against fabricated devices. Our model addresses inherent stochasticity, offering a robust tool for the design and simulation of VCMA MRAM peripheral circuits. Achieving a tenfold increase in simulation speed compared to existing stochastic Landau-Lifshitz-Gilbert-Slonczewski (sLLGS) based models ( $10times$ to $100times$ ), and overcoming accuracy problems related to VCMA macro-spin sLLGS simulations, our approach enables efficient exploration of MRAM based circuits. The model efficiency and accuracy are demonstrated through a practical use case.
{"title":"Stochastic Aware Modeling of Voltage Controlled Magnetic Anisotropy MRAM","authors":"Bowen Wang;Fernando García-Redondo;Marie Garcia Bardon;Hyungrock Oh;Mohit Gupta;Woojin Kim;Diego Favaro;Yukai Chen;Wim Dehaene","doi":"10.1109/TNANO.2024.3361718","DOIUrl":"10.1109/TNANO.2024.3361718","url":null,"abstract":"This paper presents a physics-based compact model for Voltage-Controlled Magnetic Anisotropy (VCMA) MRAM, calibrated against fabricated devices. Our model addresses inherent stochasticity, offering a robust tool for the design and simulation of VCMA MRAM peripheral circuits. Achieving a tenfold increase in simulation speed compared to existing stochastic Landau-Lifshitz-Gilbert-Slonczewski (sLLGS) based models (\u0000<inline-formula><tex-math>$10times$</tex-math></inline-formula>\u0000 to \u0000<inline-formula><tex-math>$100times$</tex-math></inline-formula>\u0000), and overcoming accuracy problems related to VCMA macro-spin sLLGS simulations, our approach enables efficient exploration of MRAM based circuits. The model efficiency and accuracy are demonstrated through a practical use case.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"144-150"},"PeriodicalIF":2.1,"publicationDate":"2024-02-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139956881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-30DOI: 10.1109/TNANO.2024.3360312
Manoj Kumar;Ming-Hung Wu;Tuo-Hung Hou;Manan Suri
We propose a Non-Volatile Ternary Content Addressable Memory (nvTCAM) by utilizing two Resistive Random-Access Memory (RRAM) cells integrated with individual selector transistors (i.e., 2-Transistor, 2-RRAM). A 2T2R cell configured either in complementary resistive switching mode (i.e., if one 1T1R cell is in low resistance state then the other cell will be in high resistance state or vice-versa) or both RRAMs in high resistance state is utilized to implement a single nvTCAM unit. Through Monte-Carlo (MC) simulations and power supply scaling (i.e., $V_{DD}$ varying from 1.4 V to 2.2 V) effects, reliability of the proposed cell was studied. Moreover, we performed the simulations for various sizes of word length from 1-bit to 64-bits and calculated the energy and delay parameters. We compared the proposed nvTCAM cell with various existing CMOS/NVM (Non-Volatile Memory) designs. Our proposed nvTCAM design provides $geq 2times$ area efficiency as compared to CMOS-NVM counterparts and even upto $sim 6times$ area saving with respect to CMOS-based volatile TCAM. The proposed design achieves atleast 1.68× to 2.27× energy efficiency, as compared to existing CMOS/RRAM implementations. Moreover the energy saving is further increased upto $sim 1400times$ as compared to magnetic/ferroelectric-based nvTCAM counterparts.
{"title":"CMOS-RRAM Based Non-Volatile Ternary Content Addressable Memory (nvTCAM)","authors":"Manoj Kumar;Ming-Hung Wu;Tuo-Hung Hou;Manan Suri","doi":"10.1109/TNANO.2024.3360312","DOIUrl":"10.1109/TNANO.2024.3360312","url":null,"abstract":"We propose a Non-Volatile Ternary Content Addressable Memory (nvTCAM) by utilizing two Resistive Random-Access Memory (RRAM) cells integrated with individual selector transistors (i.e., 2-Transistor, 2-RRAM). A 2T2R cell configured either in complementary resistive switching mode (i.e., if one 1T1R cell is in low resistance state then the other cell will be in high resistance state or vice-versa) or both RRAMs in high resistance state is utilized to implement a single nvTCAM unit. Through Monte-Carlo (MC) simulations and power supply scaling (i.e., \u0000<inline-formula><tex-math>$V_{DD}$</tex-math></inline-formula>\u0000 varying from 1.4 V to 2.2 V) effects, reliability of the proposed cell was studied. Moreover, we performed the simulations for various sizes of word length from 1-bit to 64-bits and calculated the energy and delay parameters. We compared the proposed nvTCAM cell with various existing CMOS/NVM (Non-Volatile Memory) designs. Our proposed nvTCAM design provides \u0000<inline-formula><tex-math>$geq 2times$</tex-math></inline-formula>\u0000 area efficiency as compared to CMOS-NVM counterparts and even upto \u0000<inline-formula><tex-math>$sim 6times$</tex-math></inline-formula>\u0000 area saving with respect to CMOS-based volatile TCAM. The proposed design achieves atleast 1.68× to 2.27× energy efficiency, as compared to existing CMOS/RRAM implementations. Moreover the energy saving is further increased upto \u0000<inline-formula><tex-math>$sim 1400times$</tex-math></inline-formula>\u0000 as compared to magnetic/ferroelectric-based nvTCAM counterparts.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"203-207"},"PeriodicalIF":2.4,"publicationDate":"2024-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139956601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A systematized experimental interpretation of BaTiO 3 (B), ZnO (Z), and BaTiO 3 /ZnO (B/Z) based sensors, fabricated via a facile solution-based method is reported. The structural properties analysis of all the sensors fabricated reveals the formation of characteristic respective dominant peaks (hexagonal, tetragonal, and heterostructure (hexagonal and tetragonal) for B, Z, and B/Z respectively). The decrease of band gap (2.97 eV-B/Z) due to double heterojunction formation is evident from tauc plot analysis. The fabricated multi-sensing sensors were subjected to both gas (CO (carbon monoxide) & (CH 4 ) methane) and acceleration sensing systems individually to explore sensing properties. Comparably, the B/Z sensor showed improved gas sensing properties in terms of better response time (s), recovery time (s), and sensor response (%) at lower concentrations (10 ppm) for CO gas ∼1.12, ∼2.2 and ∼61.54 and CH 4 gas ∼4.12, ∼58.69, ∼14 respectively at room temperature. Likewise, the B/Z sensor exhibited a maximum output voltage of 2.31 V at a 13 Hz resonant frequency and a sensitivity of 1.9316 Vg −1 compared to the other fabricated sensors.
{"title":"Experimental Evaluation of Tailored Double Heterojunction Non-Toxic Metal Oxide-Based Nanostructured Sensor for Multi-Sensing Application","authors":"Binowesley R;Kirubaveni Savarimuthu;Kiruthika Ramany;Govindaraj Rajamanickam","doi":"10.1109/TNANO.2024.3359697","DOIUrl":"10.1109/TNANO.2024.3359697","url":null,"abstract":"A systematized experimental interpretation of BaTiO\u0000<sub>3</sub>\u0000 (B), ZnO (Z), and BaTiO\u0000<sub>3</sub>\u0000/ZnO (B/Z) based sensors, fabricated via a facile solution-based method is reported. The structural properties analysis of all the sensors fabricated reveals the formation of characteristic respective dominant peaks (hexagonal, tetragonal, and heterostructure (hexagonal and tetragonal) for B, Z, and B/Z respectively). The decrease of band gap (2.97 eV-B/Z) due to double heterojunction formation is evident from tauc plot analysis. The fabricated multi-sensing sensors were subjected to both gas (CO (carbon monoxide) & (CH\u0000<sub>4</sub>\u0000) methane) and acceleration sensing systems individually to explore sensing properties. Comparably, the B/Z sensor showed improved gas sensing properties in terms of better response time (s), recovery time (s), and sensor response (%) at lower concentrations (10 ppm) for CO gas ∼1.12, ∼2.2 and ∼61.54 and CH\u0000<sub>4</sub>\u0000 gas ∼4.12, ∼58.69, ∼14 respectively at room temperature. Likewise, the B/Z sensor exhibited a maximum output voltage of 2.31 V at a 13 Hz resonant frequency and a sensitivity of 1.9316 Vg\u0000<sup>−1</sup>\u0000 compared to the other fabricated sensors.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"164-169"},"PeriodicalIF":2.4,"publicationDate":"2024-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139950616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Resistive random access memory (RRAM) with edge-contacted graphene electrode has much lower power consumption and excellent scalability as in other's previous studies, which shows great potential for in-memory computing, neuromorphic integrated circuits, Big Data analytics, etc. A physics-based SPICE compact model of RRAM with graphene electrode is proposed to capture the electro-thermal characteristics of the device with consideration of various physical effects in resistive switching processes, such as the temperature-dependent conductive filament (CF) evolution, tunneling between CF tip and electrode, graphene electrode oxidation, and self-heating effect. The equivalent thermal circuit (ETC) model is developed to capture the temperature response in RRAM. The influence of graphene electrode oxidation on the resistance of the device is taken into consideration. The compact model is verified by comparing the simulated characteristics of the set/reset process and forming process with other's published experimental data.
{"title":"A Compact Model for Electro-Thermal Simulation of Resistive Random Access Memory With Graphene Electrode","authors":"Xingyu Zhai;Yun Li;Wen-Yan Yin;Shuo Zhang;Wenxuan Zang;Yanbin Yang;Hao Xie;Wenchao Chen","doi":"10.1109/TNANO.2024.3358950","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3358950","url":null,"abstract":"Resistive random access memory (RRAM) with edge-contacted graphene electrode has much lower power consumption and excellent scalability as in other's previous studies, which shows great potential for in-memory computing, neuromorphic integrated circuits, Big Data analytics, etc. A physics-based SPICE compact model of RRAM with graphene electrode is proposed to capture the electro-thermal characteristics of the device with consideration of various physical effects in resistive switching processes, such as the temperature-dependent conductive filament (CF) evolution, tunneling between CF tip and electrode, graphene electrode oxidation, and self-heating effect. The equivalent thermal circuit (ETC) model is developed to capture the temperature response in RRAM. The influence of graphene electrode oxidation on the resistance of the device is taken into consideration. The compact model is verified by comparing the simulated characteristics of the set/reset process and forming process with other's published experimental data.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"151-157"},"PeriodicalIF":2.4,"publicationDate":"2024-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139908649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Stochastic computing (SC) division circuits have gained importance in recent years compared to other arithmetic circuits due to their low complexity as a result of an accuracy tradeoff. Designing a division circuit is already complex in conventional binary-based hardware systems. Developing an accurate and efficient SC division circuit is an open research problem. Prior work proposed different SC division circuits by using multiplexers and JK-flip-flop units, which may require correlated or uncorrelated input bit-streams. This study is primarily centered on exploring a cost-effective and highly efficient bit-stream generator specifically designed for SC division circuits. In conjunction with this objective, we assess the performance of multiple bit-stream generators and analyze the impact of correlation on SC division. We compare different designs in terms of accuracy and hardware cost. Moreover, we discuss a low-cost and energy-efficient bit-stream generator via powers-of-2 Van der Corput (VDC) sequences. Among the tested sequence generators, our best results were achieved with VDC sequences. Our evaluation results demonstrate that the novel VDC-based design yields promising outputs, resulting in a 15.5% reduction in the area-delay product and an 18.05% saving in energy consumption for the same accuracy level compared to conventional bit-stream generators. Significantly, our investigation reveals that employing the proposed generator improves the precision compared to the state-of-the-art. We validate the proposed architecture with an image processing case study, achieving high PSNR and structural similarity values.
与其他算术电路相比，随机计算（SC）除法电路近年来因其在精度权衡下的低复杂度而变得越来越重要。在传统的基于二进制的硬件系统中，设计除法电路已经非常复杂。开发精确高效的 SC 除法电路是一个有待解决的研究课题。之前的研究通过使用多路复用器和 JK 触发器单元提出了不同的 SC 除法电路，这些电路可能需要相关或不相关的输入比特流。本研究的主要核心是探索一种专为 SC 除法电路设计的经济高效的位流发生器。结合这一目标，我们评估了多个位流发生器的性能，并分析了相关性对 SC 除法的影响。我们比较了不同设计的精度和硬件成本。此外，我们还讨论了通过 Van der Corput（VDC）序列的 2 次方（powers-of-2 Van der Corput）设计的低成本、高能效比特流发生器。在测试过的序列发生器中，我们使用 VDC 序列取得了最佳结果。我们的评估结果表明，基于 VDC 的新型设计具有良好的输出效果，与传统位流发生器相比，在相同精度水平下，面积-延迟乘积减少了 15.5%，能耗节省了 18.05%。值得注意的是，我们的研究表明，与最先进的技术相比，采用建议的生成器可提高精度。我们通过一项图像处理案例研究验证了所提出的架构，获得了较高的 PSNR 和结构相似度值。
{"title":"Low-Cost and Highly-Efficient Bit-Stream Generator for Stochastic Computing Division","authors":"Mehran Shoushtari Moghadam;Sercan Aygun;Sina Asadi;M. Hassan Najafi","doi":"10.1109/TNANO.2024.3358395","DOIUrl":"10.1109/TNANO.2024.3358395","url":null,"abstract":"Stochastic computing (SC) division circuits have gained importance in recent years compared to other arithmetic circuits due to their low complexity as a result of an accuracy tradeoff. Designing a division circuit is already complex in conventional binary-based hardware systems. Developing an accurate and efficient SC division circuit is an open research problem. Prior work proposed different SC division circuits by using multiplexers and JK-flip-flop units, which may require correlated or uncorrelated input bit-streams. This study is primarily centered on exploring a cost-effective and highly efficient bit-stream generator specifically designed for SC division circuits. In conjunction with this objective, we assess the performance of multiple bit-stream generators and analyze the impact of correlation on SC division. We compare different designs in terms of accuracy and hardware cost. Moreover, we discuss a low-cost and energy-efficient bit-stream generator via powers-of-2 Van der Corput (VDC) sequences. Among the tested sequence generators, our best results were achieved with VDC sequences. Our evaluation results demonstrate that the novel VDC-based design yields promising outputs, resulting in a 15.5% reduction in the area-delay product and an 18.05% saving in energy consumption for the same accuracy level compared to conventional bit-stream generators. Significantly, our investigation reveals that employing the proposed generator improves the precision compared to the state-of-the-art. We validate the proposed architecture with an image processing case study, achieving high PSNR and structural similarity values.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"195-202"},"PeriodicalIF":2.4,"publicationDate":"2024-01-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139950560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：