Pub Date : 2024-11-08DOI: 10.1109/TNANO.2024.3494856
Zidu Li;Moin Diwan;Phil David Börner;Andreas Bablich;Heidemarie Schmidt;Peter Haring Bolívar;Bhaskar Choubey
An Ag/SiO $_{2}$ /ITO thin-film memristor with a simple deposition technique that exhibits bidirectional threshold and bipolar memristive switching is presented. By applying adequate compliance currents, the switching mechanism of the memristor can be transitioned from threshold switching to bipolar switching. The reverse transition, from bipolar to threshold can be realized by applying a large negative current. This bidirectional switching is stable and reproducible, which has been proven by multiple experimental results. In addition, Verilog-A based modeling approach of this directional switching mechanism is also presented.
{"title":"On Bidirectional Transition Between Threshold and Bipolar Switching in Ag/SiO$_{2}$/ITO Memristors","authors":"Zidu Li;Moin Diwan;Phil David Börner;Andreas Bablich;Heidemarie Schmidt;Peter Haring Bolívar;Bhaskar Choubey","doi":"10.1109/TNANO.2024.3494856","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3494856","url":null,"abstract":"An Ag/SiO\u0000<inline-formula><tex-math>$_{2}$</tex-math></inline-formula>\u0000/ITO thin-film memristor with a simple deposition technique that exhibits bidirectional threshold and bipolar memristive switching is presented. By applying adequate compliance currents, the switching mechanism of the memristor can be transitioned from threshold switching to bipolar switching. The reverse transition, from bipolar to threshold can be realized by applying a large negative current. This bidirectional switching is stable and reproducible, which has been proven by multiple experimental results. In addition, Verilog-A based modeling approach of this directional switching mechanism is also presented.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"771-777"},"PeriodicalIF":2.1,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-05DOI: 10.1109/TNANO.2024.3492021
Reetwik Bhadra;Ramesh Kumar;Amitesh Kumar
This study emphasizes the utilization of split-gate technology in designing a tunable artificial synapse with high energy efficiency. A split-gate dual metal synaptic transistor (SGDMST) is proposed in this work with an Indium-gallium-zinc-oxide (IGZO) channel and a proton-based nanogranular Al 2 O 3 electrolyte working on an electric-double-layer (EDL) technique. The split gate, along with the dual metal used, allows precise gate control with high energy efficacy and also enhances the potentiation and depression synaptic strengths of the device. Furthermore, extensive studies have been conducted on the impact of scaling channel width and employing either single or dual metal gate electrodes on synaptic properties. The findings demonstrate precise simulations of synaptic processes, including paired-pulse facilitation, Short-Term Plasticity (STP), Long-Term Plasticity (LTP), and depression, and comparisons are drawn based on the variables examined. The results provide a concise overview of the split-gate synaptic device and its potential impact on developing neuromorphic computing systems.
{"title":"Dual Metal Split Gate-Based Emulated Synaptic Device With Redacted Plasticity Utilizing Nanogranular Al2O3 Based Ion Conducting Electrolyte","authors":"Reetwik Bhadra;Ramesh Kumar;Amitesh Kumar","doi":"10.1109/TNANO.2024.3492021","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3492021","url":null,"abstract":"This study emphasizes the utilization of split-gate technology in designing a tunable artificial synapse with high energy efficiency. A split-gate dual metal synaptic transistor (SGDMST) is proposed in this work with an Indium-gallium-zinc-oxide (IGZO) channel and a proton-based nanogranular Al\u0000<sub>2</sub>\u0000O\u0000<sub>3</sub>\u0000 electrolyte working on an electric-double-layer (EDL) technique. The split gate, along with the dual metal used, allows precise gate control with high energy efficacy and also enhances the potentiation and depression synaptic strengths of the device. Furthermore, extensive studies have been conducted on the impact of scaling channel width and employing either single or dual metal gate electrodes on synaptic properties. The findings demonstrate precise simulations of synaptic processes, including paired-pulse facilitation, Short-Term Plasticity (STP), Long-Term Plasticity (LTP), and depression, and comparisons are drawn based on the variables examined. The results provide a concise overview of the split-gate synaptic device and its potential impact on developing neuromorphic computing systems.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"765-770"},"PeriodicalIF":2.1,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142757839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-28DOI: 10.1109/TNANO.2024.3487223
Nandit Kaushik;B. Srinivasu
In-Memory-Computing (IMC) through memristive architectures has recently gained traction owing to their capacity to perform logic operations within a crossbar, optimizing both area and speed constraints. This paper introduces two approximate serial IMPLY-based subtractor designs, denoted as Serial IMPLY-based Approximate Subtractor Design-1 (SIASD-1), Serial IMPLY-based Approximate Subtractor Design-2 (SIASD-2), with potential applications in image processing and deep neural networks. The proposed designs are implemented in MAGIC topology for comparison, named as Serial MAGIC-based Approximate Subtractor Design-1 (SMASD-1) and Serial MAGIC-based Approximate Subtractor Design-2 (SMASD-2). Moreover, these proposed subtractor designs are extended to design magnitude comparators. IMPLY-based approximate designs improve the overall latency up to 1.67× with energy savings in the range of 17.4% to 40.3% while occupying the same number of memristors for SIASD-1 and an increase of 3 to 5 memristors for SIASD-2, compared to the best existing exact 8-bit serial IMPLY subtractor. SMASD-1 and SMASD-2 improve the latency up to 1.43×, and energy efficiency are up by 77.6% compared to other MAGIC-based exact designs. Additionally, as comparators, the SIASD-1 and SIASD-2 are up to 4.93× faster with energy reduction up to 79.7% compared to their IMPLY-based equivalents. Similarly, the SMASD-1 and SMASD-2 reduce the latency up to 62% with area savings of 77%, compared to MAGIC-based equivalent designs. Furthermore, the proposed subtractor designs undergo analysis in an image processing application called Motion Detection, while the comparators are evaluated in Max Pooling operations. With Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) serving as assessment metrics, the proposed designs consistently demonstrate acceptable PSNR and SSIM values, affirming their suitability for these applications.
{"title":"High-Speed and Area-Efficient Serial IMPLY-Based Approximate Subtractor and Comparator for Image Processing and Neural Networks","authors":"Nandit Kaushik;B. Srinivasu","doi":"10.1109/TNANO.2024.3487223","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3487223","url":null,"abstract":"In-Memory-Computing (IMC) through memristive architectures has recently gained traction owing to their capacity to perform logic operations within a crossbar, optimizing both area and speed constraints. This paper introduces two approximate serial IMPLY-based subtractor designs, denoted as Serial IMPLY-based Approximate Subtractor Design-1 (SIASD-1), Serial IMPLY-based Approximate Subtractor Design-2 (SIASD-2), with potential applications in image processing and deep neural networks. The proposed designs are implemented in MAGIC topology for comparison, named as Serial MAGIC-based Approximate Subtractor Design-1 (SMASD-1) and Serial MAGIC-based Approximate Subtractor Design-2 (SMASD-2). Moreover, these proposed subtractor designs are extended to design magnitude comparators. IMPLY-based approximate designs improve the overall latency up to 1.67× with energy savings in the range of 17.4% to 40.3% while occupying the same number of memristors for SIASD-1 and an increase of 3 to 5 memristors for SIASD-2, compared to the best existing exact 8-bit serial IMPLY subtractor. SMASD-1 and SMASD-2 improve the latency up to 1.43×, and energy efficiency are up by 77.6% compared to other MAGIC-based exact designs. Additionally, as comparators, the SIASD-1 and SIASD-2 are up to 4.93× faster with energy reduction up to 79.7% compared to their IMPLY-based equivalents. Similarly, the SMASD-1 and SMASD-2 reduce the latency up to 62% with area savings of 77%, compared to MAGIC-based equivalent designs. Furthermore, the proposed subtractor designs undergo analysis in an image processing application called Motion Detection, while the comparators are evaluated in Max Pooling operations. With Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) serving as assessment metrics, the proposed designs consistently demonstrate acceptable PSNR and SSIM values, affirming their suitability for these applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"748-757"},"PeriodicalIF":2.1,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142645568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TNANO.2024.3485758
Leila Shakiba;Mohammad Reza Salehi;Farzin Emami
In this article, the graphene-based metamaterial perfect absorber was investigated in the terahertz region. Due to the geometrical symmetry of the proposed absorber structure, it is insensitive to changes in polarization and its angle, and the absorption value is almost the same over angles from 0 to 90 degrees. According to the configuration of the proposed structure, it is sensitive to changes in the refractive index. Placing graphene on top of the structure improves important sensing parameters, including sensitivity, due to good interaction with the analyte. The proposed structure is being investigated for medical applications including the diagnosis of malaria infection, cancer cells, and hemoglobin identification. The obtained results show the values of sensitivity, figure of merit, and quality coefficient as 2.63(THz/RIU), 175.3(1/RIU), and 523.35, respectively. The accuracy and correctness of the simulation results are checked using the method of equivalent circuit model and transfer matrix method, and there is good agreement between the simulation results and the mentioned methods.
{"title":"Design of a Graphene Based Terahertz Perfect Metamaterial Absorber With Multiple Sensing Performance","authors":"Leila Shakiba;Mohammad Reza Salehi;Farzin Emami","doi":"10.1109/TNANO.2024.3485758","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3485758","url":null,"abstract":"In this article, the graphene-based metamaterial perfect absorber was investigated in the terahertz region. Due to the geometrical symmetry of the proposed absorber structure, it is insensitive to changes in polarization and its angle, and the absorption value is almost the same over angles from 0 to 90 degrees. According to the configuration of the proposed structure, it is sensitive to changes in the refractive index. Placing graphene on top of the structure improves important sensing parameters, including sensitivity, due to good interaction with the analyte. The proposed structure is being investigated for medical applications including the diagnosis of malaria infection, cancer cells, and hemoglobin identification. The obtained results show the values of sensitivity, figure of merit, and quality coefficient as 2.63(THz/RIU), 175.3(1/RIU), and 523.35, respectively. The accuracy and correctness of the simulation results are checked using the method of equivalent circuit model and transfer matrix method, and there is good agreement between the simulation results and the mentioned methods.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"741-747"},"PeriodicalIF":2.1,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142565582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-23DOI: 10.1109/TNANO.2024.3485213
E. Salvador;M.B. Gonzalez;F. Campabadal;R. Rodriguez;E. Miranda
Resistive RAMs or memristors are nowadays considered serious candidates for the implementation of energy efficient and scalable neuromorphic computing systems. However, a major drawback of this technology is the instability of the device current-voltage (I-V) characteristic as is clearly revealed by the so-called cycle-to-cycle (C2C) variability. This lack of complete reproducibility is a consequence of the spontaneous or induced morphological changes of the filamentary conducting structure occurring at atomic level. Variability is an essential issue any compact model for the conduction characteristics of RRAM devices should be able to cope with to be considered realistic. In this work, a thorough investigation of the C2C variability in the I-V loops of HfO 2 -based memristive structures was carried out with the aim of incorporating this information into the equations of the Dynamic Memdiode Model. From the compact modeling viewpoint, C2C correlation effects are achieved using model parameters expressed as mean-reverting stochastic processes driven by Wiener noise (Ornstein-Uhlenbeck process). The direct and indirect links between the random behavior of the model parameters and the observable magnitudes (high and low resistance states, set and reset voltages, etc.) are discussed. The agreement between simulation and experimental results is statistically assessed using the Wasserstein's distance metric.
{"title":"Modeling and Simulation of Correlated Cycle-to- Cycle Variability in the Current-Voltage Hysteresis Loops of RRAM Devices","authors":"E. Salvador;M.B. Gonzalez;F. Campabadal;R. Rodriguez;E. Miranda","doi":"10.1109/TNANO.2024.3485213","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3485213","url":null,"abstract":"Resistive RAMs or memristors are nowadays considered serious candidates for the implementation of energy efficient and scalable neuromorphic computing systems. However, a major drawback of this technology is the instability of the device current-voltage (I-V) characteristic as is clearly revealed by the so-called cycle-to-cycle (C2C) variability. This lack of complete reproducibility is a consequence of the spontaneous or induced morphological changes of the filamentary conducting structure occurring at atomic level. Variability is an essential issue any compact model for the conduction characteristics of RRAM devices should be able to cope with to be considered realistic. In this work, a thorough investigation of the C2C variability in the I-V loops of HfO\u0000<sub>2</sub>\u0000-based memristive structures was carried out with the aim of incorporating this information into the equations of the Dynamic Memdiode Model. From the compact modeling viewpoint, C2C correlation effects are achieved using model parameters expressed as mean-reverting stochastic processes driven by Wiener noise (Ornstein-Uhlenbeck process). The direct and indirect links between the random behavior of the model parameters and the observable magnitudes (high and low resistance states, set and reset voltages, etc.) are discussed. The agreement between simulation and experimental results is statistically assessed using the Wasserstein's distance metric.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"758-764"},"PeriodicalIF":2.1,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10730782","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-16DOI: 10.1109/TNANO.2024.3481392
Gilsang Yoon;Donghyun Go;Jounghun Park;Donghwi Kim;Jongwoo Kim;Ukju An;Jungsik Kim;Jeong-Soo Lee;Byoung Don Kong
Trap profiles in the bandgap-engineered tunneling oxide (BE-TOX) layer of a 3D NAND flash memory were investigated using a transient current trap spectroscopy technique. A new pulse scheme was introduced to generate channel holes and subsequently analyze the hole traps in the BE-TOX layer. In the fresh cell, the hole traps were primarily located at a trap energy level ( ET ) of 1.1 eV, whereas the electron traps exhibited two distinct peaks at ET = 0.75 and 1.25 eV. With increasing program/erase (P/E) cycling operations, the peak ET associated with hole traps shifted toward shallower levels. Conversely, the electron traps remained unchanged, although their intensities increased. The extracted trap generation exhibited the power-law characteristics.
利用瞬态电流陷阱光谱技术研究了三维 NAND 闪存带隙工程隧道氧化物（BE-TOX）层中的陷阱剖面。研究采用了一种新的脉冲方案来产生沟道空穴，然后分析 BE-TOX 层中的空穴陷阱。在新电池中，空穴陷阱主要位于 1.1 eV 的陷阱能级 (ET)，而电子陷阱则在 ET = 0.75 和 1.25 eV 处显示出两个明显的峰值。随着编程/擦除（P/E）循环操作的增加，与空穴阱相关的峰值 ET 向更浅的水平移动。相反，电子陷阱保持不变，但其强度有所增加。提取的陷阱生成呈现出幂律特性。
{"title":"Impact of Electron and Hole Trap Profiles in BE-TOX on Retention Characteristics of 3D NAND Flash Memory","authors":"Gilsang Yoon;Donghyun Go;Jounghun Park;Donghwi Kim;Jongwoo Kim;Ukju An;Jungsik Kim;Jeong-Soo Lee;Byoung Don Kong","doi":"10.1109/TNANO.2024.3481392","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3481392","url":null,"abstract":"Trap profiles in the bandgap-engineered tunneling oxide (BE-TOX) layer of a 3D NAND flash memory were investigated using a transient current trap spectroscopy technique. A new pulse scheme was introduced to generate channel holes and subsequently analyze the hole traps in the BE-TOX layer. In the fresh cell, the hole traps were primarily located at a trap energy level (\u0000<italic>E<sub>T</sub></i>\u0000) of 1.1 eV, whereas the electron traps exhibited two distinct peaks at \u0000<italic>E<sub>T</sub></i>\u0000 = 0.75 and 1.25 eV. With increasing program/erase (P/E) cycling operations, the peak \u0000<italic>E<sub>T</sub></i>\u0000 associated with hole traps shifted toward shallower levels. Conversely, the electron traps remained unchanged, although their intensities increased. The extracted trap generation exhibited the power-law characteristics.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"733-740"},"PeriodicalIF":2.1,"publicationDate":"2024-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142565655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-03DOI: 10.1109/TNANO.2024.3473931
Mohammad Zunaidur Rashid;Shaikh Shahid Ahmed
To study coupled electro-thermal transport processes in nanoscale electronic devices, continuum models are no longer sufficient. In this work, we present an effort to couple a three-dimensional (3-D) Monte Carlo Phonon Transport (MCPT) kernel with a 3-D Monte Carlo Electron Transport (MCET) simulator. The phonon-phonon scattering is modeled in relaxation time approximation (RTA) using Holland's formalism. Diffusive boundary collisions for phonons is modeled using the Beckmann-Kirchhoff (B-K) surface roughness scattering formalism considering the effects of phonon wavelength, incident angles and degree of surface roughness. In the electron-phonon coupled platform, acoustic and intervalley g and f type electron-phonon scattering mechanisms are considered and the resulting local temperature modification has been used to bridge the electron and phonon transport paths. The simulator has been validated by modeling the self-heating effect in a nanoscale FinFET device. Here, phonon transport at the oxide-silicon interface has been treated using the Diffuse Mismatch (DM) model, whereas, the phonons in the oxide have been described using the Debye model and temperature and frequency dependent relaxation time. For a FinFET with a gate length of 18 nm, channel width of 4 nm, and a fin height of 8 nm, simulation results show an ON current degradation of as high as ∼7% due to self-heating. The temperature rise in the channel region is found to be ∼30 K.
要研究纳米级电子器件中的电热耦合传输过程，连续模型已不再足够。在这项工作中，我们努力将三维（3-D）蒙特卡洛声子传输（MCPT）核与三维蒙特卡洛电子传输（MCET）模拟器结合起来。声子-声子散射采用霍兰形式主义的弛豫时间近似（RTA）建模。声子的扩散边界碰撞采用贝克曼-基尔霍夫（B-K）表面粗糙度散射形式主义建模，考虑了声子波长、入射角和表面粗糙度的影响。在电子-声子耦合平台中，考虑了声学和间隙 g 和 f 型电子-声子散射机制，并利用由此产生的局部温度修正来连接电子和声子传输路径。通过对纳米级 FinFET 器件中的自热效应建模，该模拟器得到了验证。在这里，氧化物-硅界面上的声子传输采用扩散错配（DM）模型进行处理，而氧化物中的声子则采用德拜模型以及与温度和频率相关的弛豫时间进行描述。对于栅极长度为 18 nm、沟道宽度为 4 nm、鳍片高度为 8 nm 的 FinFET，模拟结果显示，由于自发热，导通电流衰减高达 ∼ 7%。沟道区域的温升为 30 K。
{"title":"Full 3-D Monte Carlo Simulation of Coupled Electron-Phonon Transport: Self-Heating in a Nanoscale FinFET","authors":"Mohammad Zunaidur Rashid;Shaikh Shahid Ahmed","doi":"10.1109/TNANO.2024.3473931","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3473931","url":null,"abstract":"To study coupled electro-thermal transport processes in nanoscale electronic devices, continuum models are no longer sufficient. In this work, we present an effort to couple a three-dimensional (3-D) Monte Carlo Phonon Transport (MCPT) kernel with a 3-D Monte Carlo Electron Transport (MCET) simulator. The phonon-phonon scattering is modeled in relaxation time approximation (RTA) using Holland's formalism. Diffusive boundary collisions for phonons is modeled using the Beckmann-Kirchhoff (B-K) surface roughness scattering formalism considering the effects of phonon wavelength, incident angles and degree of surface roughness. In the electron-phonon coupled platform, acoustic and intervalley \u0000<italic>g</i>\u0000 and \u0000<italic>f</i>\u0000 type electron-phonon scattering mechanisms are considered and the resulting local temperature modification has been used to bridge the electron and phonon transport paths. The simulator has been validated by modeling the self-heating effect in a nanoscale FinFET device. Here, phonon transport at the oxide-silicon interface has been treated using the Diffuse Mismatch (DM) model, whereas, the phonons in the oxide have been described using the Debye model and temperature and frequency dependent relaxation time. For a FinFET with a gate length of 18 nm, channel width of 4 nm, and a fin height of 8 nm, simulation results show an ON current degradation of as high as ∼7% due to self-heating. The temperature rise in the channel region is found to be ∼30 K.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"696-703"},"PeriodicalIF":2.1,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142565514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-02DOI: 10.1109/TNANO.2024.3472728
Poundoss Chellamuthu;Kirubaveni Savarimuthu;Mohammed Gulam Nabi Alsath;Govindaraj Rajamanickam
A wide range of industrial, environmental, and biomedical applications depend greatly on the development of sensitive and reliable humidity sensors. This work reports an extensive investigation of a nanostructured surfactant such as Sodium Dodecyl Sulfate (SDS) and Cetyltrimethyl Ammonium Bromide (CTAB) activated mixed metal oxide (Zinc Oxide / Nickel Oxide) nanomaterial. The crystal study demonstrates an increase in the ZnO/NiO characteristic peaks (101) and (200), due to surface reactive agents. The increment of CTAB molar ratio has significantly increased the crystallite size, such that the bandgap of ZnO/NiO composite is reduced from 3.37eV to 2.80 eV. Brunauer-Emmitt-Teller (BET) surface area study revealed the production of a mesoporous ZnO with an improvement in the specific surface area from 7.82 to 52.01 m 2 g −1 with a mean diameter reducing from 22.28 to 18.94 nm for the CTAB molar concentration range of 0.0, 0.5, 1.0, 1.5 and 2.0 M namely SC-1, SC-2, SC-3, SC-4, and SC-5 respectively. The internal resistance achieved for the 2M sample is 1 KΩ, which is suitable for better humidity and gas sensing properties. Hence, the proposed ZnO/NiO metal oxide material is more sensitive to a plurality of analytes by providing an increased BET surface area.
{"title":"Experimental Investigations and Characterization of Surfactant Activated Mixed Metal Oxide (MMO) Nanomaterial","authors":"Poundoss Chellamuthu;Kirubaveni Savarimuthu;Mohammed Gulam Nabi Alsath;Govindaraj Rajamanickam","doi":"10.1109/TNANO.2024.3472728","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3472728","url":null,"abstract":"A wide range of industrial, environmental, and biomedical applications depend greatly on the development of sensitive and reliable humidity sensors. This work reports an extensive investigation of a nanostructured surfactant such as Sodium Dodecyl Sulfate (SDS) and Cetyltrimethyl Ammonium Bromide (CTAB) activated mixed metal oxide (Zinc Oxide / Nickel Oxide) nanomaterial. The crystal study demonstrates an increase in the ZnO/NiO characteristic peaks (101) and (200), due to surface reactive agents. The increment of CTAB molar ratio has significantly increased the crystallite size, such that the bandgap of ZnO/NiO composite is reduced from 3.37eV to 2.80 eV. Brunauer-Emmitt-Teller (BET) surface area study revealed the production of a mesoporous ZnO with an improvement in the specific surface area from 7.82 to 52.01 m\u0000<sup>2</sup>\u0000g\u0000<sup>−1</sup>\u0000 with a mean diameter reducing from 22.28 to 18.94 nm for the CTAB molar concentration range of 0.0, 0.5, 1.0, 1.5 and 2.0 M namely SC-1, SC-2, SC-3, SC-4, and SC-5 respectively. The internal resistance achieved for the 2M sample is 1 KΩ, which is suitable for better humidity and gas sensing properties. Hence, the proposed ZnO/NiO metal oxide material is more sensitive to a plurality of analytes by providing an increased BET surface area.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"727-732"},"PeriodicalIF":2.1,"publicationDate":"2024-10-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142565515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-27DOI: 10.1109/TNANO.2024.3469973
Manas R. Samantaray;Agniv Tapadar;Santanu Das;Nikhil Chander;Avishek Adhikary
This work proposes a novel, cost-effective, and simplified method to fabricate(reduced graphene oxide (rGO) nanorods. It is demonstrated that when a composite film made of polyvinylidene fluoride (PVDF) and the fabricated rGO is formed on a silver substrate, a unique structural morphology appears. This structure is unlike the general morphological structures of PVDF and rGO. The fabricated rGO has a nanorod-shapes of 0.54 nm to 1.15 $mu$ m length and diameter in the 51 $-$ 64 nm range. The presence of $alpha$ and $beta$ phase PVDF and rGO in the composite has been confirmed using both X-ray diffractometer and Raman spectroscopy. Impedance characterization of the fabricated device shows constant phase characteristics in the frequency range of 126 kHz to 2 MHz with a constant phase angle at $-63^{circ }$ to $-78^{circ }$ . This indicates that the proposed rGO Nanorod-PVDF composite is suitable for the fabrication of a thin film fractor (fractional order device) with fractional order $eta$ = 0.70 to 0.88 and fractance value 0.08 to 3.08 nF $s^{eta }$ .
{"title":"Low Temperature One-Pot Synthesis of rGO Nanorod-PVDF Composite and Fabrication of a Thin Film Solid-State Fractional Order Device","authors":"Manas R. Samantaray;Agniv Tapadar;Santanu Das;Nikhil Chander;Avishek Adhikary","doi":"10.1109/TNANO.2024.3469973","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3469973","url":null,"abstract":"This work proposes a novel, cost-effective, and simplified method to fabricate(reduced graphene oxide (rGO) nanorods. It is demonstrated that when a composite film made of polyvinylidene fluoride (PVDF) and the fabricated rGO is formed on a silver substrate, a unique structural morphology appears. This structure is unlike the general morphological structures of PVDF and rGO. The fabricated rGO has a nanorod-shapes of 0.54 nm to 1.15 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000m length and diameter in the 51\u0000<inline-formula><tex-math>$-$</tex-math></inline-formula>\u0000 64 nm range. The presence of \u0000<inline-formula><tex-math>$alpha$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$beta$</tex-math></inline-formula>\u0000 phase PVDF and rGO in the composite has been confirmed using both X-ray diffractometer and Raman spectroscopy. Impedance characterization of the fabricated device shows constant phase characteristics in the frequency range of 126 kHz to 2 MHz with a constant phase angle at \u0000<inline-formula><tex-math>$-63^{circ }$</tex-math></inline-formula>\u0000 to \u0000<inline-formula><tex-math>$-78^{circ }$</tex-math></inline-formula>\u0000. This indicates that the proposed rGO Nanorod-PVDF composite is suitable for the fabrication of a thin film fractor (fractional order device) with fractional order \u0000<inline-formula><tex-math>$eta$</tex-math></inline-formula>\u0000 = 0.70 to 0.88 and fractance value 0.08 to 3.08 nF\u0000<inline-formula><tex-math>$s^{eta }$</tex-math></inline-formula>\u0000.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"692-695"},"PeriodicalIF":2.1,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142434596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Batch normalization (BN) is a technique used to enhance training speed and generalization performance by mitigating internal covariate shifts. However, implementing BN in hardware presents challenges due to the need for an additional complex circuit to normalize, scale and shift activations. We proposed a hardware binary neural network (BNN) system capable of BN in hardware, which is consist of an AND-type flash memory array as a synapse and a voltage sense amplifier (VSA) as a neuron. In this system, hardware BN was implemented using a voltage shifter by adjusting the threshold of the binary neuron. To validate the effectiveness of the proposed hardware-based BNN system, we fabricated a charge trap flash with a gate stack of SiO 2 /Si 3 N 4 /SiO 2 . The electrical characteristics were modelled by using BSIM3 model parameters so that the proposed circuit was successfully demonstrated by a SPICE simulation. Moreover, variation effects of the voltage shifter were also analyzed using Monte Carlo simulation. Finally, the performance of the proposed system was proved by incorporating the SPICE results into a high-level simulation of binary LeNet-5 for MNIST pattern recognition, resulting in the improvement of the proposed system in terms of power and area, compared to the previous studies.
{"title":"First Realization of Batch Normalization in Flash-Based Binary Neural Networks Using a Single Voltage Shifter","authors":"Sungmin Hwang;Wangjoo Lee;Jeong Woo Park;Dongwoo Suh","doi":"10.1109/TNANO.2024.3466128","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3466128","url":null,"abstract":"Batch normalization (BN) is a technique used to enhance training speed and generalization performance by mitigating internal covariate shifts. However, implementing BN in hardware presents challenges due to the need for an additional complex circuit to normalize, scale and shift activations. We proposed a hardware binary neural network (BNN) system capable of BN in hardware, which is consist of an AND-type flash memory array as a synapse and a voltage sense amplifier (VSA) as a neuron. In this system, hardware BN was implemented using a voltage shifter by adjusting the threshold of the binary neuron. To validate the effectiveness of the proposed hardware-based BNN system, we fabricated a charge trap flash with a gate stack of SiO\u0000<sub>2</sub>\u0000/Si\u0000<sub>3</sub>\u0000N\u0000<sub>4</sub>\u0000/SiO\u0000<sub>2</sub>\u0000. The electrical characteristics were modelled by using BSIM3 model parameters so that the proposed circuit was successfully demonstrated by a SPICE simulation. Moreover, variation effects of the voltage shifter were also analyzed using Monte Carlo simulation. Finally, the performance of the proposed system was proved by incorporating the SPICE results into a high-level simulation of binary \u0000<italic>LeNet-5</i>\u0000 for MNIST pattern recognition, resulting in the improvement of the proposed system in terms of power and area, compared to the previous studies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"677-683"},"PeriodicalIF":2.1,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142434586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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