With the advancement of optoelectronic technology, a new evaluation of photodetectors’ (PDs’) performance is necessary for next-generation sensing applications. This study uses the e-beam evaporation approach to produce slanted titanium dioxide columnar (TiO2-COL) on the Si substrate, with a constant deposition angle of ∼ 61°. The morphology, structural, and optical properties of the fabricated TiO2-COL samples were examined. Successful growth of the slanted TiO2-COL structure is demonstrated by field emission scanning electron microscopy (FE-SEM). Furthermore, XRD analyses reveal that TiO2-COL has an amorphous nature. Optical characterization reveals that the fabricated sample exhibits high absorption intensity in the UV region, for demonstrating a potential UV photodetector application. The TiO2-COL based PD that was deposited obliquely displayed I-V curves that demonstrated a distinct photovoltaic mode and an extremely low dark current of a few nanoamperes. Moreover, at ∼ 320 nm, the device exhibits a self-powered UV light response with a responsivity value of around ∼ 1.3 mA/W. In addition, this TiO2-COL based photodetector device demonstrates a remarkable detectivity and noise-equivalent-power (NEP) and rise time/fall time of ∼ 4.63 × 1010 Jones, ∼ 6.06 × 10−11 W and ∼ 0.305/0.184 sec, respectively, at −0.1 V. Therefore, this novel idea of a slanted TiO2-COL structure promotes effective light management and offers a reliable route for creating Low-powered UV PDs.
{"title":"Oblique Angle Deposition of Slanted TiO2 Columnar for UV Photodetector Application","authors":"Salam Surjit Singh;Naorem Khelchand Singh;Sapam Bikesh;Biraj Shougaijam","doi":"10.1109/TNANO.2025.3616005","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3616005","url":null,"abstract":"With the advancement of optoelectronic technology, a new evaluation of photodetectors’ (PDs’) performance is necessary for next-generation sensing applications. This study uses the e-beam evaporation approach to produce slanted titanium dioxide columnar (TiO<sub>2</sub>-COL) on the Si substrate, with a constant deposition angle of ∼ 61°. The morphology, structural, and optical properties of the fabricated TiO<sub>2</sub>-COL samples were examined. Successful growth of the slanted TiO<sub>2</sub>-COL structure is demonstrated by field emission scanning electron microscopy (FE-SEM). Furthermore, XRD analyses reveal that TiO<sub>2</sub>-COL has an amorphous nature. Optical characterization reveals that the fabricated sample exhibits high absorption intensity in the UV region, for demonstrating a potential UV photodetector application. The TiO<sub>2</sub>-COL based PD that was deposited obliquely displayed I-V curves that demonstrated a distinct photovoltaic mode and an extremely low dark current of a few nanoamperes. Moreover, at ∼ 320 nm, the device exhibits a self-powered UV light response with a responsivity value of around ∼ 1.3 mA/W. In addition, this TiO<sub>2</sub>-COL based photodetector device demonstrates a remarkable detectivity and noise-equivalent-power (NEP) and rise time/fall time of ∼ 4.63 × 10<sup>10</sup> Jones, ∼ 6.06 × 10<sup>−11</sup> W and ∼ 0.305/0.184 sec, respectively, at −0.1 V. Therefore, this novel idea of a slanted TiO<sub>2</sub>-COL structure promotes effective light management and offers a reliable route for creating Low-powered UV PDs.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"489-494"},"PeriodicalIF":2.1,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145255873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-25DOI: 10.1109/TNANO.2025.3614198
Xiangrong Pu;Haoming Qi;Gang Liu;Zhang Zhang
In industrial IoT and distributed computing environments, edge computing devices empowered by AI have seen increasing deployment in large-scale scenarios, thereby accelerating the demand for time-series data processing. The gated recurrent unit (GRU) outperforms conventional artificial neural networks (ANNs) in tasks such as natural language processing, speech recognition, and machine translation, due to its superior capability in modeling long-range dependencies in sequential data. However, the GRU model is limited by its large parameter count and structural complexity, which presents a bottleneck in hardware circuit implementation. To this end, a memristor-based hybrid gated recurrent unit (HGRU) is proposed, which reduces the parameter count to 67% of the original GRU and shortens the single-step computation latency by 50%, while maintaining complete circuit functionality. Finally, the proposed memristor-based HGRU circuit model is evaluated on the MNIST digit recognition and IMDB sentiment analysis tasks, achieving recognition accuracies of 97% and 86.2%, respectively. Under equivalent parameter settings, it achieves runtime reductions of 37% and 52% compared to the standard GRU, thereby significantly enhancing computational efficiency.
{"title":"Memristor-Based Circuit Demonstration of Hybrid Gated Recurrent Unit for Edge Computing","authors":"Xiangrong Pu;Haoming Qi;Gang Liu;Zhang Zhang","doi":"10.1109/TNANO.2025.3614198","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3614198","url":null,"abstract":"In industrial IoT and distributed computing environments, edge computing devices empowered by AI have seen increasing deployment in large-scale scenarios, thereby accelerating the demand for time-series data processing. The gated recurrent unit (GRU) outperforms conventional artificial neural networks (ANNs) in tasks such as natural language processing, speech recognition, and machine translation, due to its superior capability in modeling long-range dependencies in sequential data. However, the GRU model is limited by its large parameter count and structural complexity, which presents a bottleneck in hardware circuit implementation. To this end, a memristor-based hybrid gated recurrent unit (HGRU) is proposed, which reduces the parameter count to 67% of the original GRU and shortens the single-step computation latency by 50%, while maintaining complete circuit functionality. Finally, the proposed memristor-based HGRU circuit model is evaluated on the MNIST digit recognition and IMDB sentiment analysis tasks, achieving recognition accuracies of 97% and 86.2%, respectively. Under equivalent parameter settings, it achieves runtime reductions of 37% and 52% compared to the standard GRU, thereby significantly enhancing computational efficiency.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"481-488"},"PeriodicalIF":2.1,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-23DOI: 10.1109/TNANO.2025.3613362
Prashant Kumar;Rajeev Kumar Ranjan;Sung-Mo Kang
Electronic neurons, such as integrate-and-fire models and memristor synapses, are key components of energy-efficient spiking neural network (SNN) systems. Current silicon-based models face challenges due to high transistor counts, large footprints, and excessive energy consumption. This brief presents a low-transistor count, energy-efficient neuron design. Our spiking signal-generating circuit consumes approximately 1.2 pJ per spike and uses a single capacitor as its only passive element, while occupying a layout area of 66.93 $mathrm{mu }$m × 36.12 $mathrm{mu }$m and operating on a 1 V power supply. We also highlight the driving capability and pattern recognition application of our proposed neuron model.
{"title":"An Ultra-Low Power 1.2 pJ/Spike Fully CMOS Spiking Neuron and Its Application","authors":"Prashant Kumar;Rajeev Kumar Ranjan;Sung-Mo Kang","doi":"10.1109/TNANO.2025.3613362","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3613362","url":null,"abstract":"Electronic neurons, such as integrate-and-fire models and memristor synapses, are key components of energy-efficient spiking neural network (SNN) systems. Current silicon-based models face challenges due to high transistor counts, large footprints, and excessive energy consumption. This brief presents a low-transistor count, energy-efficient neuron design. Our spiking signal-generating circuit consumes approximately 1.2 pJ per spike and uses a single capacitor as its only passive element, while occupying a layout area of 66.93 <inline-formula><tex-math>$mathrm{mu }$</tex-math></inline-formula>m × 36.12 <inline-formula><tex-math>$mathrm{mu }$</tex-math></inline-formula>m and operating on a 1 V power supply. We also highlight the driving capability and pattern recognition application of our proposed neuron model.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"462-468"},"PeriodicalIF":2.1,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, the effect of ultrathin Al$_{bm {2}}$O$_{bm {3}}$ insertion layer on the endurance characteristics of Hf$_{bm {0.5}}$Zr$_{bm {0.5}}$O$_{bm {2}}$ (HZO) layer is statistically investigated. It was found that the ultrathin Al$_{bm {2}}$O$_{bm {3}}$ insertion layer will not improve or reduce the endurance of HZO devices within the low operation voltage range. However, an abrupt endurance degradation phenomenon is observed when increasing the operation voltage to a specific value and the endurance of HZO/Al$_{bm {2}}$O$_{bm {3}}$ layer is sharply lower than HZO device. This phenomenon is finally explained by the leakage-current-assist polarization switching mechanism after quantitatively extracting the continuous charge density during the polarization switching by pulse measurement. The findings of this work provide a deep understanding of the endurance failure mechanism of Ferroelectric/Dielectric (FE/DE) devices and are helpful for the reliability investigation of the gate stack in Fe-FET.
{"title":"Statistical Investigation of Al$_{2}$O$_{3}$ Insertion Layer on the Endurance of Hf$_{0.5}$Zr$_{0.5}$O$_{2}$ Films: Abrupt Endurance Degradation and Mechanism","authors":"Heng Ye;Xiaomin Lai;Xinzhong Zhu;Jing Liu;Xiaoshan Pan;Yuanlu Xie;Lanlong Ji;Kai Xi;Tiancheng Gong;Yuan Qiu","doi":"10.1109/TNANO.2025.3611601","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3611601","url":null,"abstract":"In this work, the effect of ultrathin Al<inline-formula><tex-math>$_{bm {2}}$</tex-math></inline-formula>O<inline-formula><tex-math>$_{bm {3}}$</tex-math></inline-formula> insertion layer on the endurance characteristics of Hf<inline-formula><tex-math>$_{bm {0.5}}$</tex-math></inline-formula>Zr<inline-formula><tex-math>$_{bm {0.5}}$</tex-math></inline-formula>O<inline-formula><tex-math>$_{bm {2}}$</tex-math></inline-formula> (HZO) layer is statistically investigated. It was found that the ultrathin Al<inline-formula><tex-math>$_{bm {2}}$</tex-math></inline-formula>O<inline-formula><tex-math>$_{bm {3}}$</tex-math></inline-formula> insertion layer will not improve or reduce the endurance of HZO devices within the low operation voltage range. However, an abrupt endurance degradation phenomenon is observed when increasing the operation voltage to a specific value and the endurance of HZO/Al<inline-formula><tex-math>$_{bm {2}}$</tex-math></inline-formula>O<inline-formula><tex-math>$_{bm {3}}$</tex-math></inline-formula> layer is sharply lower than HZO device. This phenomenon is finally explained by the leakage-current-assist polarization switching mechanism after quantitatively extracting the continuous charge density during the polarization switching by pulse measurement. The findings of this work provide a deep understanding of the endurance failure mechanism of Ferroelectric/Dielectric (FE/DE) devices and are helpful for the reliability investigation of the gate stack in Fe-FET.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"500-503"},"PeriodicalIF":2.1,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145352091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents a comprehensive numerical framework for modeling the photoresponse of monolayer graphene-based photodetectors, by solving Poisson’s and current continuity equations self-consistently. The framework accurately captures both electrostatic potential and carrier transport phenomena in graphene-metal junctions and is validated against experimental data. By implementing a PIN junction architecture, a “staircase” potential profile is formed in the device leading to local electric fields on the order of 105 V/cm, significantly enhancing carrier separation and drift current. Our simulation results indicate that the PIN junction yields a 40x increase in responsivity compared to conventional sheet-based graphene devices. This highlights the potential of the PIN junction-based approach for developing advanced, tunable, broadband graphene photodetectors. The developed numerical framework offers a powerful tool for photodetector optimization, enabling systematic exploration of structural parameters and operating conditions.
{"title":"Numerical Modeling and Analysis of Photoresponse in Graphene-Based PIN Junction Devices","authors":"Vinod Sharma;Jinal Kiran Tapar;Oves Badami;Naresh Kumar Emani","doi":"10.1109/TNANO.2025.3610119","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3610119","url":null,"abstract":"This work presents a comprehensive numerical framework for modeling the photoresponse of monolayer graphene-based photodetectors, by solving Poisson’s and current continuity equations self-consistently. The framework accurately captures both electrostatic potential and carrier transport phenomena in graphene-metal junctions and is validated against experimental data. By implementing a PIN junction architecture, a “staircase” potential profile is formed in the device leading to local electric fields on the order of 10<sup>5</sup> V/cm, significantly enhancing carrier separation and drift current. Our simulation results indicate that the PIN junction yields a 40x increase in responsivity compared to conventional sheet-based graphene devices. This highlights the potential of the PIN junction-based approach for developing advanced, tunable, broadband graphene photodetectors. The developed numerical framework offers a powerful tool for photodetector optimization, enabling systematic exploration of structural parameters and operating conditions.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"504-509"},"PeriodicalIF":2.1,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145351920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-05DOI: 10.1109/TNANO.2025.3606832
Julien Lombardi;Fariha Reza;Nasim Farahmand;Rajinder Deol;Nitika Batra;Jonathan E. Spanier;Christine K. McGinn;Ioannis Kymissis;Stephen O’Brien
Nanodielectrics based upon nanoscale Ba(Ti, MV)O3, where M = Nb or Ta, were prepared and electrically characterized for their potential use as a high permittivity dielectric layer. Nanocrystals of Ba(Ti, Nb)O3 (BTNO) and Ba(Ti, Ta)O3 (BTTO) of average size 20 nm (range 10–50 nm) with a non-centrosymmetric (polarizable) crystal structure were synthesized, dispersed in alcohol solvents and blended with three polymers of known but differing dielectric and electromechanical behavior: Polyvinylpyrrolidone (PVP), Polyfurfuryl alcohol (PFA) and Polyvinylidene fluoride–trifluoroethylene (PVDF-TrFE). 0–3 nanoparticle-polymer pressed pellets, films and metal-insulator-metal devices were prepared for electrical characterization. Analysis of the Ba(Ti, MV)O3-PVP and Ba(Ti, MV)O3 -PFA composites showed a high effective permittivity, low loss, low leakage and voltage tolerance, demonstrating the capability for high energy density capacitance. Effective permittivity, of 52 (BTNO-PFA) and 42 (BTTO-PFA) for pellet nanocomposites and 32 (BTNO-PVP) and 20 (BTNO-PVP) film nanocomposites were observed at 1 MHz respectively. Voltage breakdown strengths of 2133 V/mm (BTNO) and 833 V/mm (BTTO) were demonstrated respectively (threshold 0.1 μA). Linear and non-linear dielectric behavior was studied by polarization-electric field (P-E) hysteresis measurements. Nanocomposites of BTNO-PVDF-TrFE were prepared to assess the viability of making ferroelectric nanocomposites over a range of polymer-nanoparticle volume fractions.
{"title":"Linear, Non-Linear, and Ferroelectric Behavior in 0–3 Nanoparticle-Polymer Dielectrics of Ba(Ti, MV)O3 (M = Nb, Ta)","authors":"Julien Lombardi;Fariha Reza;Nasim Farahmand;Rajinder Deol;Nitika Batra;Jonathan E. Spanier;Christine K. McGinn;Ioannis Kymissis;Stephen O’Brien","doi":"10.1109/TNANO.2025.3606832","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3606832","url":null,"abstract":"Nanodielectrics based upon nanoscale Ba(Ti, M<sup>V</sup>)O<sub>3</sub>, where M = Nb or Ta, were prepared and electrically characterized for their potential use as a high permittivity dielectric layer. Nanocrystals of Ba(Ti, Nb)O<sub>3</sub> (BTNO) and Ba(Ti, Ta)O<sub>3</sub> (BTTO) of average size 20 nm (range 10–50 nm) with a non-centrosymmetric (polarizable) crystal structure were synthesized, dispersed in alcohol solvents and blended with three polymers of known but differing dielectric and electromechanical behavior: Polyvinylpyrrolidone (PVP), Polyfurfuryl alcohol (PFA) and Polyvinylidene fluoride–trifluoroethylene (PVDF-TrFE). 0–3 nanoparticle-polymer pressed pellets, films and metal-insulator-metal devices were prepared for electrical characterization. Analysis of the Ba(Ti, M<sup>V</sup>)O<sub>3</sub>-PVP and Ba(Ti, M<sup>V</sup>)O<sub>3</sub> -PFA composites showed a high effective permittivity, low loss, low leakage and voltage tolerance, demonstrating the capability for high energy density capacitance. Effective permittivity, of 52 (BTNO-PFA) and 42 (BTTO-PFA) for pellet nanocomposites and 32 (BTNO-PVP) and 20 (BTNO-PVP) film nanocomposites were observed at 1 MHz respectively. Voltage breakdown strengths of 2133 V/mm (BTNO) and 833 V/mm (BTTO) were demonstrated respectively (threshold 0.1 μA). Linear and non-linear dielectric behavior was studied by polarization-electric field (P-E) hysteresis measurements. Nanocomposites of BTNO-PVDF-TrFE were prepared to assess the viability of making ferroelectric nanocomposites over a range of polymer-nanoparticle volume fractions.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"452-461"},"PeriodicalIF":2.1,"publicationDate":"2025-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145210097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-02DOI: 10.1109/TNANO.2025.3605557
Kyung Min Koo;Jae Seung Woo;Woo Young Choi
We analyze the suppression of gate-diagonal tunneling by an oxide-trapped charge in gate-normal tunneling field effect transistors (TFETs). It is observed that the gate-diagonal tunneling occurring ahead of gate-normal tunneling can be alleviated by trapping electrons in the gate insulator over the channel region. Oxide-trapped charges can be generated by process technologies or hot carrier injections. Because the trapped electrons screen the gate voltage effectively and weaken the gate controllability over the gate-diagonal tunneling region, the achieved subthreshold swing and on-current are 27-% lower and 2.89x higher than those of conventional gate-normal TFETs, respectively.
{"title":"Oxide-Trapped-Charge-Induced Gate-Diagonal Tunneling Suppression of Gate-Normal Tunnel Field-Effect Transistors","authors":"Kyung Min Koo;Jae Seung Woo;Woo Young Choi","doi":"10.1109/TNANO.2025.3605557","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3605557","url":null,"abstract":"We analyze the suppression of gate-diagonal tunneling by an oxide-trapped charge in gate-normal tunneling field effect transistors (TFETs). It is observed that the gate-diagonal tunneling occurring ahead of gate-normal tunneling can be alleviated by trapping electrons in the gate insulator over the channel region. Oxide-trapped charges can be generated by process technologies or hot carrier injections. Because the trapped electrons screen the gate voltage effectively and weaken the gate controllability over the gate-diagonal tunneling region, the achieved subthreshold swing and on-current are 27-% lower and 2.89x higher than those of conventional gate-normal TFETs, respectively.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"445-451"},"PeriodicalIF":2.1,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-25DOI: 10.1109/TNANO.2025.3602073
Roshni Oommen;Adikiran S B;Akash R.;Gautham G;Aswathi R Nair
In this work we propose a biasing scheme to modulate the retention behavior of oxide semiconductor based optoelectronic synapses. The method has been demonstrated using a zinc oxide thin film transistor, which exhibits persistent photoconductivity to UV light. The application of a negative gate bias prevents the recombination of photo-generated carriers, leading to a negligible decay in the post synaptic current and consequently, the retention time could extend beyond $10^{5}$s. The improvement in memory retention is observed in various synaptic functions such as short-term memory, long-term memory, duration-time-dependent plasticity and paired pulse facilitation. A five fold improvement in the % decay of post synaptic current was observed at $V_{gs}$ = −5 V, when compared to $V_{gs}$ = +5 V. Furthermore, we have assessed the impact of these improved retention properties on the performance of an artificial neural network, designed for pattern recognition of MNIST handwritten digits. The accuracy decayed drastically with time from 96% to nearly 40% at $V_{gs}$ = +5 V whereas it drops to only 94% at $V_{gs}$ = −5 V.
{"title":"Gate Tunable Retention in Optoelectronic Synapses Using Oxide Semiconductor Thin Film Transistors","authors":"Roshni Oommen;Adikiran S B;Akash R.;Gautham G;Aswathi R Nair","doi":"10.1109/TNANO.2025.3602073","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3602073","url":null,"abstract":"In this work we propose a biasing scheme to modulate the retention behavior of oxide semiconductor based optoelectronic synapses. The method has been demonstrated using a zinc oxide thin film transistor, which exhibits persistent photoconductivity to UV light. The application of a negative gate bias prevents the recombination of photo-generated carriers, leading to a negligible decay in the post synaptic current and consequently, the retention time could extend beyond <inline-formula><tex-math>$10^{5}$</tex-math></inline-formula>s. The improvement in memory retention is observed in various synaptic functions such as short-term memory, long-term memory, duration-time-dependent plasticity and paired pulse facilitation. A five fold improvement in the % decay of post synaptic current was observed at <inline-formula><tex-math>$V_{gs}$</tex-math></inline-formula> = −5 V, when compared to <inline-formula><tex-math>$V_{gs}$</tex-math></inline-formula> = +5 V. Furthermore, we have assessed the impact of these improved retention properties on the performance of an artificial neural network, designed for pattern recognition of MNIST handwritten digits. The accuracy decayed drastically with time from 96% to nearly 40% at <inline-formula><tex-math>$V_{gs}$</tex-math></inline-formula> = +5 V whereas it drops to only 94% at <inline-formula><tex-math>$V_{gs}$</tex-math></inline-formula> = −5 V.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"434-438"},"PeriodicalIF":2.1,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144998258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-18DOI: 10.1109/TNANO.2025.3599842
Shuying Wang;Pengpeng Ren;Yewei Zhang;Mingzhao Yang;Runsheng Wang;Zhigang Ji
Nanosheet transistors has emerged as a potential structure of semiconductor technology. The introduction of Wrapped-Around Contact (WAC) and Backside Power Delivery Network, particularly the Backside Contact (BSC) in nanosheet transistors, has effectively promotes further scaling. This work contributes to design technology co-optimization (DTCO) for BSC technology by comprehensively exploring the impact of structural innovation, process parameters and dimension parameters. Through electro-thermal coupling simulations, we reveal the significant advantages of Backside Contact with WAC structure in terms of electrothermal properties compared to conventional structures. We also investigate the impact of contact resistivity, contact thermal resistivity, sheet width and number on device and circuit performance. This work provides an inspiration to optimize electro-thermal performance under advanced nodes.
{"title":"Towards Design-Technology Co-Optimization for Nanosheet Transistors With Backside Contact","authors":"Shuying Wang;Pengpeng Ren;Yewei Zhang;Mingzhao Yang;Runsheng Wang;Zhigang Ji","doi":"10.1109/TNANO.2025.3599842","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3599842","url":null,"abstract":"Nanosheet transistors has emerged as a potential structure of semiconductor technology. The introduction of Wrapped-Around Contact (WAC) and Backside Power Delivery Network, particularly the Backside Contact (BSC) in nanosheet transistors, has effectively promotes further scaling. This work contributes to design technology co-optimization (DTCO) for BSC technology by comprehensively exploring the impact of structural innovation, process parameters and dimension parameters. Through electro-thermal coupling simulations, we reveal the significant advantages of Backside Contact with WAC structure in terms of electrothermal properties compared to conventional structures. We also investigate the impact of contact resistivity, contact thermal resistivity, sheet width and number on device and circuit performance. This work provides an inspiration to optimize electro-thermal performance under advanced nodes.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"439-444"},"PeriodicalIF":2.1,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145036786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-07DOI: 10.1109/TNANO.2025.3597001
Jasil T K;Ashish Kumar Yadav;Gyanendra Kumar Maurya;Vivek Garg;Sushil Kumar Pandey
One of the most important factors influencing the performance of Na-ion batteries (NIBs) is the anode’s quality. Currently, NIB anodes have numerous disadvantages, including low capacity, rapid volume change, temperature variable conductivity and poor thermal/chemical stability. In this work, the electronic and transport properties of undoped, doped and defective 1T-NbS2 monolayers were investigated using density functional theory calculations. The maximum quantum capacitance of 1T-NbS2 with S-vacancy (VS-NbS2) changes from 20.49 to 16.92 μF/cm2 across temperature ranges of 200 K to 1000 K, indicating its suitability as anode with temperature-stable capacity. The 1T-NbS2 monolayers exhibit high electrical conductivity with less than 6% fluctuation across a temperature range of 200 K to 1000 K, indicating thermally stable conductance. The 1T-NbS2 layered structure has substantially larger interlayer spacing of 0.615 nm than the size of Na ion (0.095 nm), as well as a relatively tiny variation (0.05 eV for VS-NbS2) in cohesive energies between sodiated and de-sodiated phases, making it a good choice for anodes. For VS-NbS2, the seebeck coefficient ranges from -5 to -40 μV/K, which is often obtained by the most commonly used Na-metal anode, demonstrating its appropriateness as anode. According to our findings, 1T-NbS2 is a great option for thermally stable NIB electrode applications.
{"title":"Enhancement of Functionalized 1T-NbS2 Monolayer Properties for the Superior Anode of Na-Ion Batteries","authors":"Jasil T K;Ashish Kumar Yadav;Gyanendra Kumar Maurya;Vivek Garg;Sushil Kumar Pandey","doi":"10.1109/TNANO.2025.3597001","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3597001","url":null,"abstract":"One of the most important factors influencing the performance of Na-ion batteries (NIBs) is the anode’s quality. Currently, NIB anodes have numerous disadvantages, including low capacity, rapid volume change, temperature variable conductivity and poor thermal/chemical stability. In this work, the electronic and transport properties of undoped, doped and defective 1T-NbS<sub>2</sub> monolayers were investigated using density functional theory calculations. The maximum quantum capacitance of 1T-NbS<sub>2</sub> with S-vacancy (V<sub>S</sub>-NbS<sub>2</sub>) changes from 20.49 to 16.92 μF/cm<sup>2</sup> across temperature ranges of 200 K to 1000 K, indicating its suitability as anode with temperature-stable capacity. The 1T-NbS<sub>2</sub> monolayers exhibit high electrical conductivity with less than 6% fluctuation across a temperature range of 200 K to 1000 K, indicating thermally stable conductance. The 1T-NbS<sub>2</sub> layered structure has substantially larger interlayer spacing of 0.615 nm than the size of Na ion (0.095 nm), as well as a relatively tiny variation (0.05 eV for V<sub>S</sub>-NbS<sub>2</sub>) in cohesive energies between sodiated and de-sodiated phases, making it a good choice for anodes. For V<sub>S</sub>-NbS<sub>2</sub>, the seebeck coefficient ranges from -5 to -40 μV/K, which is often obtained by the most commonly used Na-metal anode, demonstrating its appropriateness as anode. According to our findings, 1T-NbS<sub>2</sub> is a great option for thermally stable NIB electrode applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"421-427"},"PeriodicalIF":2.1,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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