Pub Date : 2024-09-12DOI: 10.1109/TNANO.2024.3459472
Diksha Maurya;Devendra Chack;G. Vickey
Waveguide grating antenna with compact size and high diffraction efficiency remains a significant challenge in beam steering applications for integrated Optical Phased Arrays (OPA). Traditional waveguide grating antennas have large footprints, limiting antenna arrays' density. High diffraction efficiency is essential for effective signal transmission, making it a crucial aspect of antenna design. Optical antennas need higher diffraction efficiency, compact size, and broader field of view to achieve this. The proposed work aims to design a single-etch grating antenna on a silicon-on-insulator (SOI) platform that emits light off-chip. The methodology combines the initial grating antenna designed using Finite-difference time-domain (FDTD) simulations and optimizes it with a genetic algorithm. The proposed design uses a transverse spliced grating, Bragg reflectors, and bottom reflector to achieve an impressive upward diffraction efficiency of nearly 88% operating in C -band centered at 1550 nm. The size of the proposed antenna is 2.8 μm and offers a wide far-field beam width of 38 ° x 136 °. This work enables new advancements in integrated waveguide grating antenna development, with potential applications in free-space optical interconnects and on-chip optical phased arrays.
波导光栅天线具有体积小、衍射效率高的特点，在集成光相控阵（OPA）的波束转向应用中仍是一项重大挑战。传统的波导光栅天线占地面积大，限制了天线阵列的密度。高衍射效率对有效的信号传输至关重要，因此是天线设计的一个关键方面。为此，光学天线需要更高的衍射效率、更小的尺寸和更宽的视场。本研究旨在在硅绝缘体（SOI）平台上设计一种单蚀刻光栅天线，该天线可在芯片外发射光线。该方法结合了利用有限差分时域 (FDTD) 仿真设计的初始光栅天线，并利用遗传算法对其进行优化。拟议的设计使用了横向拼接光栅、布拉格反射器和底部反射器，在以 1550 nm 为中心的 C 波段实现了近 88% 的惊人向上衍射效率。拟议的天线尺寸为 2.8 μm，远场波束宽度为 38 ° x 136 °。这项工作推动了集成波导光栅天线开发的新进展，有望应用于自由空间光互连和片上光学相控阵。
{"title":"Compact and Efficient Transverse Spliced Waveguide Grating Antenna for Integrated Optical Phased Array","authors":"Diksha Maurya;Devendra Chack;G. Vickey","doi":"10.1109/TNANO.2024.3459472","DOIUrl":"10.1109/TNANO.2024.3459472","url":null,"abstract":"Waveguide grating antenna with compact size and high diffraction efficiency remains a significant challenge in beam steering applications for integrated Optical Phased Arrays (OPA). Traditional waveguide grating antennas have large footprints, limiting antenna arrays' density. High diffraction efficiency is essential for effective signal transmission, making it a crucial aspect of antenna design. Optical antennas need higher diffraction efficiency, compact size, and broader field of view to achieve this. The proposed work aims to design a single-etch grating antenna on a silicon-on-insulator (SOI) platform that emits light off-chip. The methodology combines the initial grating antenna designed using Finite-difference time-domain (FDTD) simulations and optimizes it with a genetic algorithm. The proposed design uses a transverse spliced grating, Bragg reflectors, and bottom reflector to achieve an impressive upward diffraction efficiency of nearly 88% operating in C -band centered at 1550 nm. The size of the proposed antenna is 2.8 μm and offers a wide far-field beam width of 38 ° x 136 °. This work enables new advancements in integrated waveguide grating antenna development, with potential applications in free-space optical interconnects and on-chip optical phased arrays.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"665-672"},"PeriodicalIF":2.1,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Graphene-based dry electrodes have shown considerable promise in electrophysiological signal monitoring applications by providing a comfortable, irritant-free alternative to traditional wet electrodes. The proposed electrode was fabricated using a spray-coating technique by depositing reduced graphene oxide (rGO) on a polydimethylsiloxane (PDMS) substrate. The rGO/PDMS dry electrodes exhibit the capability to capture and transmit weak bio-electrical signals such as Electrocardiogram (ECGs) and Electromyogram (EMGs) without significant attenuation or distortion. Experimental results show that when compared to conventional wet Ag/AgCl electrodes, the fabricated rGO/PDMS electrodes measure higher-quality ECG signals with improved SNRs while offering similar contact quality and electrode-skin impedance despite being a dry electrode. The fabricated rGO/PDMS electrodes demonstrated excellent performance and applicability making them suitable for use in wearable long-term health monitoring devices.
{"title":"Reduced Graphene Oxide-Polydimethylsiloxane Based Flexible Dry Electrodes for Electrophysiological Signal Monitoring","authors":"Suraj Baloda;Sashank Krishna Sriram;Sumitra Singh;Navneet Gupta","doi":"10.1109/TNANO.2024.3459931","DOIUrl":"10.1109/TNANO.2024.3459931","url":null,"abstract":"Graphene-based dry electrodes have shown considerable promise in electrophysiological signal monitoring applications by providing a comfortable, irritant-free alternative to traditional wet electrodes. The proposed electrode was fabricated using a spray-coating technique by depositing reduced graphene oxide (rGO) on a polydimethylsiloxane (PDMS) substrate. The rGO/PDMS dry electrodes exhibit the capability to capture and transmit weak bio-electrical signals such as Electrocardiogram (ECGs) and Electromyogram (EMGs) without significant attenuation or distortion. Experimental results show that when compared to conventional wet Ag/AgCl electrodes, the fabricated rGO/PDMS electrodes measure higher-quality ECG signals with improved SNRs while offering similar contact quality and electrode-skin impedance despite being a dry electrode. The fabricated rGO/PDMS electrodes demonstrated excellent performance and applicability making them suitable for use in wearable long-term health monitoring devices.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"644-651"},"PeriodicalIF":2.1,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10679620","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.1109/TNANO.2024.3458427
Muhammad Saqlain;Muhammad Abuzar Baqir;Pankaj Kumar Choudhury
An ultrathin metasurface-based polarization-insensitive single-band terahertz (THz) sensor comprising graphene concentric rings and a thin layer of MXene was investigated for the human body cancer cells detection. The overall metamaterial configuration exhibits single narrow-band nearly-perfect absorption with a high value of quality factor due to a full-width-half-maximum of 0.033 THz at the resonance frequency of 3.793 THz. The results show a high sensitivity of the metamaterial configuration along with a stable operation under different incidence polarizations. The results reveal the designed structure is of potential in biomedical applications.
{"title":"MXene- and Graphene-Assisted THz Metamaterial for Cancer Cells Detection Based on Refractive Index Sensing","authors":"Muhammad Saqlain;Muhammad Abuzar Baqir;Pankaj Kumar Choudhury","doi":"10.1109/TNANO.2024.3458427","DOIUrl":"10.1109/TNANO.2024.3458427","url":null,"abstract":"An ultrathin metasurface-based polarization-insensitive single-band terahertz (THz) sensor comprising graphene concentric rings and a thin layer of MXene was investigated for the human body cancer cells detection. The overall metamaterial configuration exhibits single narrow-band nearly-perfect absorption with a high value of quality factor due to a full-width-half-maximum of 0.033 THz at the resonance frequency of 3.793 THz. The results show a high sensitivity of the metamaterial configuration along with a stable operation under different incidence polarizations. The results reveal the designed structure is of potential in biomedical applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"652-657"},"PeriodicalIF":2.1,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-10DOI: 10.1109/TNANO.2024.3457533
Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han
Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
{"title":"A Review of Ising Machines Implemented in Conventional and Emerging Technologies","authors":"Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han","doi":"10.1109/TNANO.2024.3457533","DOIUrl":"10.1109/TNANO.2024.3457533","url":null,"abstract":"Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"704-717"},"PeriodicalIF":2.1,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/TNANO.2024.3445455
Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori
Recently, machine learning systems have gained prominence in real-time, critical decision-making domains, such as autonomous driving and industrial automation. Their implementations should avoid overconfident predictions through uncertainty estimation. Bayesian Neural Networks (BayNNs) are principled methods for estimating predictive uncertainty. However, their computational costs and power consumption hinder their widespread deployment in edge AI. Utilizing Dropout as an approximation of the posterior distribution, binarizing the parameters of BayNNs, and further implementing them in spintronics-based computation-in-memory (CiM) hardware arrays can be a viable solution. However, designing hardware Dropout modules for convolutional neural network (CNN) topologies is challenging and expensive, as they may require numerous Dropout modules and need to use spatial information to drop certain elements. In this paper, we introduce MC-SpatialDropout, a spatial dropout-based approximate BayNNs with spintronics emerging devices. Our method utilizes the inherent stochasticity of spintronics devices for efficient implementation of the spatial dropout module compared to existing implementations. Furthermore, the number of dropout modules per network layer is reduced by a factor of $9times$ and energy consumption by a factor of $300times$ , while still achieving comparable predictive performance and uncertainty estimates compared to related works.
{"title":"Spatial-SpinDrop: Spatial Dropout-Based Binary Bayesian Neural Network With Spintronics Implementation","authors":"Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori","doi":"10.1109/TNANO.2024.3445455","DOIUrl":"10.1109/TNANO.2024.3445455","url":null,"abstract":"Recently, machine learning systems have gained prominence in real-time, critical decision-making domains, such as autonomous driving and industrial automation. Their implementations should avoid overconfident predictions through uncertainty estimation. Bayesian Neural Networks (BayNNs) are principled methods for estimating predictive uncertainty. However, their computational costs and power consumption hinder their widespread deployment in edge AI. Utilizing Dropout as an approximation of the posterior distribution, binarizing the parameters of BayNNs, and further implementing them in spintronics-based computation-in-memory (CiM) hardware arrays can be a viable solution. However, designing hardware Dropout modules for convolutional neural network (CNN) topologies is challenging and expensive, as they may require numerous Dropout modules and need to use spatial information to drop certain elements. In this paper, we introduce MC-SpatialDropout, a spatial dropout-based approximate BayNNs with spintronics emerging devices. Our method utilizes the inherent stochasticity of spintronics devices for efficient implementation of the spatial dropout module compared to existing implementations. Furthermore, the number of dropout modules per network layer is reduced by a factor of \u0000<inline-formula><tex-math>$9times$</tex-math></inline-formula>\u0000 and energy consumption by a factor of \u0000<inline-formula><tex-math>$300times$</tex-math></inline-formula>\u0000, while still achieving comparable predictive performance and uncertainty estimates compared to related works.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"636-643"},"PeriodicalIF":2.1,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/TNANO.2024.3447020
Jungyoun Kwak;Gihun Choe;Shimeng Yu
A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line (FEOL) p-type Si transistors. The proposed device structure ensures high on current density (Ion > 544 μA/μm) at V GS = 1 V, compensating for lower electron mobility in IWO (than Si). A comprehensive process flow is proposed to prove its integration potential. A custom monolithic 3D (M3D) process-design-kit (PDK) and standard cell library are developed for design-technology co-optimization (DTCO), examining the power, performance, and area (PPA) trade-offs in representative integrated circuits with ∼ 0.8 million of gates. The Verilog-to-GDS synthesis results show a 47% average area reduction in M3D circuits while maintaining a similar energy-delay-product (EDP) compared to the conventional 2D circuits.
{"title":"Design-Technology Co-Optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design","authors":"Jungyoun Kwak;Gihun Choe;Shimeng Yu","doi":"10.1109/TNANO.2024.3447020","DOIUrl":"10.1109/TNANO.2024.3447020","url":null,"abstract":"A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line (FEOL) p-type Si transistors. The proposed device structure ensures high on current density (Ion > 544 μA/μm) at V\u0000<sub>GS</sub>\u0000 = 1 V, compensating for lower electron mobility in IWO (than Si). A comprehensive process flow is proposed to prove its integration potential. A custom monolithic 3D (M3D) process-design-kit (PDK) and standard cell library are developed for design-technology co-optimization (DTCO), examining the power, performance, and area (PPA) trade-offs in representative integrated circuits with ∼ 0.8 million of gates. The Verilog-to-GDS synthesis results show a 47% average area reduction in M3D circuits while maintaining a similar energy-delay-product (EDP) compared to the conventional 2D circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"622-628"},"PeriodicalIF":2.1,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Convolutional neural networks have remarkable performance in artificial intelligence, although at the cost of computationally demanding processes within a single inference. Simultaneously, the underlying chip process is reaching its constraints as Moore's law diminishes. Stochastic computation, as a hardware-friendly and unconventional approach, can alleviate the burden of sophisticated arithmetic at the circuit level. This work presents a novel stochastic computing (SC) multiplier that employs an extension-uniform approach to create bit sequences without relying on logical gates. In addition, we propose a stochastic-binary domain arithmetic method to achieve low-cost hardware implementation and low power dissipation. The 4n-bit widths are partitioned into n 4-bit widths, with the high-precision components executed in the binary domain and the low-precision components executed in the stochastic domain. Additionally, a hardware-compatible circuit for compensating faults is also introduced. The accelerator on cifar10 using stochastic binary hybrid domain spatial coding (SHSC) multiplier achieves better performance than the fixed-point counterpart, with a 33.7% reduction in area and 23% reduction in power.
卷积神经网络在人工智能领域有着卓越的性能，但其代价是单个推理过程的计算量巨大。与此同时，随着摩尔定律的减弱，底层芯片工艺也达到了极限。随机计算作为一种对硬件友好的非常规方法，可以减轻电路级复杂运算的负担。本研究提出了一种新颖的随机计算（SC）乘法器，它采用了一种扩展均匀的方法来创建位序列，而无需依赖逻辑门。此外，我们还提出了一种随机二进制域算术方法，以实现低成本硬件实现和低功耗耗散。4n 位宽度被划分为 n 个 4 位宽度，高精度部分在二进制域中执行，低精度部分在随机域中执行。此外，还引入了用于补偿故障的硬件兼容电路。在 cifar10 上使用随机二进制混合域空间编码（SHSC）乘法器的加速器比对应的定点乘法器性能更好，面积减少了 33.7%，功耗降低了 23%。
{"title":"Stochastic-Binary Hybrid Spatial Coding Multiplier for Convolutional Neural Network Accelerator","authors":"Yakun Zhou;Jiajun Yan;Yizhuo Zhou;Ziyang Shao;Jienan Chen","doi":"10.1109/TNANO.2024.3444278","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3444278","url":null,"abstract":"Convolutional neural networks have remarkable performance in artificial intelligence, although at the cost of computationally demanding processes within a single inference. Simultaneously, the underlying chip process is reaching its constraints as Moore's law diminishes. Stochastic computation, as a hardware-friendly and unconventional approach, can alleviate the burden of sophisticated arithmetic at the circuit level. This work presents a novel stochastic computing (SC) multiplier that employs an extension-uniform approach to create bit sequences without relying on logical gates. In addition, we propose a stochastic-binary domain arithmetic method to achieve low-cost hardware implementation and low power dissipation. The 4n-bit widths are partitioned into n 4-bit widths, with the high-precision components executed in the binary domain and the low-precision components executed in the stochastic domain. Additionally, a hardware-compatible circuit for compensating faults is also introduced. The accelerator on cifar10 using stochastic binary hybrid domain spatial coding (SHSC) multiplier achieves better performance than the fixed-point counterpart, with a 33.7% reduction in area and 23% reduction in power.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"600-605"},"PeriodicalIF":2.1,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142084497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Silicon cold source field-effect transistor (CSFET) offers a compelling solution for low-power logic devices due to its ability to achieve sub-60 mV/dec steep-slope switching with innovative source engineering, while maintaining compatibility with Silicon CMOS technology. Developing a compact model for CSFETs is crucial for advancing our understanding of these novel devices and enabling advanced design and simulation based on CSFETs. To this end, this work introduces a compact model specifically designed for n-type double-gate CSFETs. Employing the Landauer-Büttiker approach alongside machine learning (ML)-based band energy profiles, our model accounts for thermal current via ballistic transport and tunneling current from source-to-drain direct tunneling. Consequently, our model accurately represents the drain current-gate voltage relationship in CSFETs. Furthermore, our proposed model is applicable to both CSFETs and conventional MOSFETs. This enables benchmarking analysis between CSFETs and conventional MOSFETs, shedding light on their comparative performance metrics.
{"title":"Machine Learning-Based Compact Modeling of Silicon Cold Source Field-Effect Transistors","authors":"Haoqing Xu;Weizhuo Gan;Shujin Guo;Shengli Zhang;Zhenhua Wu","doi":"10.1109/TNANO.2024.3442476","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3442476","url":null,"abstract":"The Silicon cold source field-effect transistor (CSFET) offers a compelling solution for low-power logic devices due to its ability to achieve sub-60 mV/dec steep-slope switching with innovative source engineering, while maintaining compatibility with Silicon CMOS technology. Developing a compact model for CSFETs is crucial for advancing our understanding of these novel devices and enabling advanced design and simulation based on CSFETs. To this end, this work introduces a compact model specifically designed for n-type double-gate CSFETs. Employing the Landauer-Büttiker approach alongside machine learning (ML)-based band energy profiles, our model accounts for thermal current via ballistic transport and tunneling current from source-to-drain direct tunneling. Consequently, our model accurately represents the drain current-gate voltage relationship in CSFETs. Furthermore, our proposed model is applicable to both CSFETs and conventional MOSFETs. This enables benchmarking analysis between CSFETs and conventional MOSFETs, shedding light on their comparative performance metrics.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"615-621"},"PeriodicalIF":2.1,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142165016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-05DOI: 10.1109/TNANO.2024.3438542
Md Mazharul Islam;Shamiul Alam;Mohammad Adnan Jahangir;Garrett S. Rose;Suman Datta;Vijaykrishnan Narayanan;Sumeet Kumar Gupta;Ahmedullah Aziz
Energy-efficient sense amplifier (SA) circuits are essential for reliable detection of stored memory states in emerging memory systems. In this work, we introduce three novel sense amplifier topologies based on phase transition materials (PTM) in addition to the previously proposed one, collectively analyzing all four designs tailored for non-volatile memory applications. We utilize the abrupt switching and volatile hysteretic characteristics of PTMs which enables efficient and fast sensing operation in our proposed SA topologies. We provide comprehensive details of their functionality and assess how process variations impact their performance metrics. Our proposed sense amplifier topologies manifest notable performance enhancement. We achieve a ∼67% reduction in sensing delay and a ∼80% decrease in sensing power for current sensing. For voltage sensing, we achieve a ∼75% reduction in sensing delay and a ∼33% decrease in sensing power. Moreover, the proposed SA topologies exhibit improved variation robustness compared to conventional SAs. We also scrutinize the dependence of transistor mirroring window and PTM transition voltages on several device parameters to determine the optimum operating conditions and stance of tunability for each of the proposed SA topologies.
在新兴存储器系统中，高能效感应放大器（SA）电路对于存储存储器状态的可靠检测至关重要。在这项工作中，除了之前提出的基于相变材料（PTM）的新型感应放大器拓扑结构外，我们还介绍了三种新型感应放大器拓扑结构，并针对非易失性存储器应用对所有四种设计进行了综合分析。我们利用 PTM 的突然开关和易挥发滞后特性，在我们提出的 SA 拓扑中实现了高效、快速的感应操作。我们提供了有关其功能的全面细节，并评估了工艺变化对其性能指标的影响。我们提出的感应放大器拓扑结构具有显著的性能提升。在电流感应方面，我们将感应延迟降低了 ∼ 67%，感应功率降低了 ∼ 80%。在电压传感方面，我们实现了传感延迟降低 75% 和传感功率降低 33% 的目标。此外，与传统的传感器相比，所提出的传感器拓扑结构具有更好的变化鲁棒性。我们还仔细研究了晶体管镜像窗口和 PTM 转换电压对多个器件参数的依赖性，以确定每种拟议 SA 拓扑的最佳工作条件和可调性。
{"title":"Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing","authors":"Md Mazharul Islam;Shamiul Alam;Mohammad Adnan Jahangir;Garrett S. Rose;Suman Datta;Vijaykrishnan Narayanan;Sumeet Kumar Gupta;Ahmedullah Aziz","doi":"10.1109/TNANO.2024.3438542","DOIUrl":"10.1109/TNANO.2024.3438542","url":null,"abstract":"Energy-efficient sense amplifier (SA) circuits are essential for reliable detection of stored memory states in emerging memory systems. In this work, we introduce three novel sense amplifier topologies based on phase transition materials (PTM) in addition to the previously proposed one, collectively analyzing all four designs tailored for non-volatile memory applications. We utilize the abrupt switching and volatile hysteretic characteristics of PTMs which enables efficient and fast sensing operation in our proposed SA topologies. We provide comprehensive details of their functionality and assess how process variations impact their performance metrics. Our proposed sense amplifier topologies manifest notable performance enhancement. We achieve a ∼67% reduction in sensing delay and a ∼80% decrease in sensing power for current sensing. For voltage sensing, we achieve a ∼75% reduction in sensing delay and a ∼33% decrease in sensing power. Moreover, the proposed SA topologies exhibit improved variation robustness compared to conventional SAs. We also scrutinize the dependence of transistor mirroring window and PTM transition voltages on several device parameters to determine the optimum operating conditions and stance of tunability for each of the proposed SA topologies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"606-614"},"PeriodicalIF":2.1,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141945961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-02DOI: 10.1109/TNANO.2024.3437669
Aadil Anam;S. Intekhab Amin;Dinesh Prasad
In this noteworthy paper, we present a novel and comprehensive investigation into the optimization of performance parameters for the conventional U-Gate III-V line TFET through TCAD simulation. Our unprecedented threefold optimization strategy encompasses multiple facets, marking a significant contribution to the field. Firstly, in our pursuit of enhancing OFF current performance, we implemented a pioneering approach by employing a highly doped p + -pocket, effectively suppressing parasitic corner tunneling and resulting in a remarkable 258.14-fold improvement in OFF current. Secondly, we embark on another unexplored avenue in conventional U-Gate TFET by implementing the negative capacitance (NC) effect into it. The NC implementation leads to substantial improvements in ON current and subthreshold swing (SS), with an impressive 4.176-fold enhancement in I ON /I OFF and a 2.151-fold reduction in average subthreshold swing (AVSS) (from 33.26 mV/dec to 15.46 mV/dec) compared to the conventional design. In the third and final stage of our optimization strategy, we efficiently combine the benefits of p + -pocket doping and NC implementation. By doing this, we simultaneously enhance the OFF current (improved by 226.91 times), ON current (improved by 1.92 times), I ON /I OFF ratio (enhanced by 435.55 times), and AVSS (improved by an outstanding 2.861 times, from 33.48 mV/dec to 11.7 mV/dec), demonstrating the effectiveness of our holistic approach. This comprehensive study sets a new benchmark for U-Gate III-V line TFET optimization, paving the way for advanced applications in low-power digital circuits.
{"title":"Optimizing InGaAs/GaAsSb Staggered Bandgap U-Gate Line TFET With p+-Pocket Implant and Negative Capacitance for Enhanced Performance","authors":"Aadil Anam;S. Intekhab Amin;Dinesh Prasad","doi":"10.1109/TNANO.2024.3437669","DOIUrl":"10.1109/TNANO.2024.3437669","url":null,"abstract":"In this noteworthy paper, we present a novel and comprehensive investigation into the optimization of performance parameters for the conventional U-Gate III-V line TFET through TCAD simulation. Our unprecedented threefold optimization strategy encompasses multiple facets, marking a significant contribution to the field. Firstly, in our pursuit of enhancing OFF current performance, we implemented a pioneering approach by employing a highly doped p\u0000<sup>+</sup>\u0000-pocket, effectively suppressing parasitic corner tunneling and resulting in a remarkable 258.14-fold improvement in OFF current. Secondly, we embark on another unexplored avenue in conventional U-Gate TFET by implementing the negative capacitance (NC) effect into it. The NC implementation leads to substantial improvements in ON current and subthreshold swing (SS), with an impressive 4.176-fold enhancement in I\u0000<sub>ON</sub>\u0000/I\u0000<sub>OFF</sub>\u0000 and a 2.151-fold reduction in average subthreshold swing (AVSS) (from 33.26 mV/dec to 15.46 mV/dec) compared to the conventional design. In the third and final stage of our optimization strategy, we efficiently combine the benefits of p\u0000<sup>+</sup>\u0000-pocket doping and NC implementation. By doing this, we simultaneously enhance the OFF current (improved by 226.91 times), ON current (improved by 1.92 times), I\u0000<sub>ON</sub>\u0000/I\u0000<sub>OFF</sub>\u0000 ratio (enhanced by 435.55 times), and AVSS (improved by an outstanding 2.861 times, from 33.48 mV/dec to 11.7 mV/dec), demonstrating the effectiveness of our holistic approach. This comprehensive study sets a new benchmark for U-Gate III-V line TFET optimization, paving the way for advanced applications in low-power digital circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"584-590"},"PeriodicalIF":2.1,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141885149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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