Batch normalization (BN) is a technique used to enhance training speed and generalization performance by mitigating internal covariate shifts. However, implementing BN in hardware presents challenges due to the need for an additional complex circuit to normalize, scale and shift activations. We proposed a hardware binary neural network (BNN) system capable of BN in hardware, which is consist of an AND-type flash memory array as a synapse and a voltage sense amplifier (VSA) as a neuron. In this system, hardware BN was implemented using a voltage shifter by adjusting the threshold of the binary neuron. To validate the effectiveness of the proposed hardware-based BNN system, we fabricated a charge trap flash with a gate stack of SiO 2 /Si 3 N 4 /SiO 2 . The electrical characteristics were modelled by using BSIM3 model parameters so that the proposed circuit was successfully demonstrated by a SPICE simulation. Moreover, variation effects of the voltage shifter were also analyzed using Monte Carlo simulation. Finally, the performance of the proposed system was proved by incorporating the SPICE results into a high-level simulation of binary LeNet-5 for MNIST pattern recognition, resulting in the improvement of the proposed system in terms of power and area, compared to the previous studies.
{"title":"First Realization of Batch Normalization in Flash-Based Binary Neural Networks Using a Single Voltage Shifter","authors":"Sungmin Hwang;Wangjoo Lee;Jeong Woo Park;Dongwoo Suh","doi":"10.1109/TNANO.2024.3466128","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3466128","url":null,"abstract":"Batch normalization (BN) is a technique used to enhance training speed and generalization performance by mitigating internal covariate shifts. However, implementing BN in hardware presents challenges due to the need for an additional complex circuit to normalize, scale and shift activations. We proposed a hardware binary neural network (BNN) system capable of BN in hardware, which is consist of an AND-type flash memory array as a synapse and a voltage sense amplifier (VSA) as a neuron. In this system, hardware BN was implemented using a voltage shifter by adjusting the threshold of the binary neuron. To validate the effectiveness of the proposed hardware-based BNN system, we fabricated a charge trap flash with a gate stack of SiO\u0000<sub>2</sub>\u0000/Si\u0000<sub>3</sub>\u0000N\u0000<sub>4</sub>\u0000/SiO\u0000<sub>2</sub>\u0000. The electrical characteristics were modelled by using BSIM3 model parameters so that the proposed circuit was successfully demonstrated by a SPICE simulation. Moreover, variation effects of the voltage shifter were also analyzed using Monte Carlo simulation. Finally, the performance of the proposed system was proved by incorporating the SPICE results into a high-level simulation of binary \u0000<italic>LeNet-5</i>\u0000 for MNIST pattern recognition, resulting in the improvement of the proposed system in terms of power and area, compared to the previous studies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"677-683"},"PeriodicalIF":2.1,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142434586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/TNANO.2024.3462802
Aks Raj;Ravi Kumar Gangwar;Raghvendra Kumar Chaudhary
This letter introduces a conformal multifunctional Terahertz Metamaterial-Resonator (TMR) that achieves ultra-wideband absorption (4.6–9.3 THz) without extra circuit components. Its isotropic design ensures angular and polarization stability on flat and curved surfaces. Utilizing phase-changing Vanadium Oxide (VO 2 ), the TMR reconfigures as an absorber, reflector, or transmissive structure, with simulation results aligning with the derived equivalent circuit model.
{"title":"Pioneering Multi-Functionality through VO2-Infused Polarization Insensitive Conformal Meta-Structures in Terahertz Regime","authors":"Aks Raj;Ravi Kumar Gangwar;Raghvendra Kumar Chaudhary","doi":"10.1109/TNANO.2024.3462802","DOIUrl":"10.1109/TNANO.2024.3462802","url":null,"abstract":"This letter introduces a conformal multifunctional Terahertz Metamaterial-Resonator (TMR) that achieves ultra-wideband absorption (4.6–9.3 THz) without extra circuit components. Its isotropic design ensures angular and polarization stability on flat and curved surfaces. Utilizing phase-changing Vanadium Oxide (VO\u0000<sub>2</sub>\u0000), the TMR reconfigures as an absorber, reflector, or transmissive structure, with simulation results aligning with the derived equivalent circuit model.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"673-676"},"PeriodicalIF":2.1,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142267935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/TNANO.2024.3462605
Joy Chowdhury;Kamalakanta Mahapatra;Angsuman Sarkar;J. K. Das
TFETs are being widely considered for next generation computing and sensing applications. They surpass conventional bulk MOSFETs in terms of subthreshold slope, leakage current and short channel effects. This paper presents a semi-analytical model accounting for both point tunneling and line tunneling schemes in a modified split-channel gate overlap source TFET(SC-GOSTFET) architecture. Considering both the tunneling schemes simultaneously along with the added line component enhances the ON-state current thus making the TFETs a better candidate for nano bio-sensors. The increase in length of the tunneling path is the major advantage of this hybrid model. This also helps to ameliorate the effect of quantum confinement in the band edges during band bending. The proposed biosensor shows reasonable agreement with the simulation data obtained from TCAD and 44.21% and 75.62% higher sensitivity over conventional biosensors. Further, the improved ambipolar characteristics can be exploited to influence the detection of a certain category of biomolecules thus increasing the detection range of this hybrid tunneling-based biosensor .
{"title":"An Analytical Model Accounting for the Pertinence of Hybrid Tunneling in Bio-TFETs","authors":"Joy Chowdhury;Kamalakanta Mahapatra;Angsuman Sarkar;J. K. Das","doi":"10.1109/TNANO.2024.3462605","DOIUrl":"10.1109/TNANO.2024.3462605","url":null,"abstract":"TFETs are being widely considered for next generation computing and sensing applications. They surpass conventional bulk MOSFETs in terms of subthreshold slope, leakage current and short channel effects. This paper presents a semi-analytical model accounting for both point tunneling and line tunneling schemes in a modified split-channel gate overlap source TFET(SC-GOSTFET) architecture. Considering both the tunneling schemes simultaneously along with the added line component enhances the ON-state current thus making the TFETs a better candidate for nano bio-sensors. The increase in length of the tunneling path is the major advantage of this hybrid model. This also helps to ameliorate the effect of quantum confinement in the band edges during band bending. The proposed biosensor shows reasonable agreement with the simulation data obtained from TCAD and 44.21% and 75.62% higher sensitivity over conventional biosensors. Further, the improved ambipolar characteristics can be exploited to influence the detection of a certain category of biomolecules thus increasing the detection range of this hybrid tunneling-based biosensor\u0000<italic>.</i>","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"658-664"},"PeriodicalIF":2.1,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142267936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-16DOI: 10.1109/TNANO.2024.3460869
Yu-Hsun Nien;Yu-Han Huang;Jung-Chuan Chou;Chih-Hsien Lai;Po-Yu Kuo;Po-Hui Yang;Jhih-Wei Zeng;Chia-Wei Wang
This study involves the utilization of electrostatic access techniques and the development of ZTO-SnO 2 /TiO 2 nanofibers (NFs) in different ratios of 1%, 3%, and 5%. The dye-sensitized solar cells (DSSCs) efficiency was enhanced through the utilization of ZTO-SnO 2 nanofiber composites in photoanodes. According to this study, the 3% ZTO-SnO 2 /TiO 2 nanofiber-modified DSSCs conversion efficiency was better than that of other DSSCs at different light intensities. When the light intensity is 100 mW/cm 2 , there is a rise in efficiency by 30.91% compared with pure TiO 2 . The EIS (Electrochemical Impedance Spectroscopy) usage demonstrated that adding ZTO-SnO 2 efficiently lowered the photoanode's electron transfer impedance. The higher scattering potential and powerful electron transfer capability have been demonstrated to have a positive effect on increasing the JSC of DSSCs using quantum efficiency studies.
{"title":"Research on Photovoltaic Measurement and Electrochemical Impedance Spectroscopy Analysis of Dye-Sensitized Solar Cells With Modification of Photoanodes by TiO2 Nanofibers Composited With Zn2SnO4-SnO2 Under Various Illuminances","authors":"Yu-Hsun Nien;Yu-Han Huang;Jung-Chuan Chou;Chih-Hsien Lai;Po-Yu Kuo;Po-Hui Yang;Jhih-Wei Zeng;Chia-Wei Wang","doi":"10.1109/TNANO.2024.3460869","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3460869","url":null,"abstract":"This study involves the utilization of electrostatic access techniques and the development of ZTO-SnO\u0000<sub>2</sub>\u0000/TiO\u0000<sub>2</sub>\u0000 nanofibers (NFs) in different ratios of 1%, 3%, and 5%. The dye-sensitized solar cells (DSSCs) efficiency was enhanced through the utilization of ZTO-SnO\u0000<sub>2</sub>\u0000 nanofiber composites in photoanodes. According to this study, the 3% ZTO-SnO\u0000<sub>2</sub>\u0000/TiO\u0000<sub>2</sub>\u0000 nanofiber-modified DSSCs conversion efficiency was better than that of other DSSCs at different light intensities. When the light intensity is 100 mW/cm\u0000<sup>2</sup>\u0000, there is a rise in efficiency by 30.91% compared with pure TiO\u0000<sub>2</sub>\u0000. The EIS (Electrochemical Impedance Spectroscopy) usage demonstrated that adding ZTO-SnO\u0000<sub>2</sub>\u0000 efficiently lowered the photoanode's electron transfer impedance. The higher scattering potential and powerful electron transfer capability have been demonstrated to have a positive effect on increasing the JSC of DSSCs using quantum efficiency studies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"684-691"},"PeriodicalIF":2.1,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142434539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-12DOI: 10.1109/TNANO.2024.3459472
Diksha Maurya;Devendra Chack;G. Vickey
Waveguide grating antenna with compact size and high diffraction efficiency remains a significant challenge in beam steering applications for integrated Optical Phased Arrays (OPA). Traditional waveguide grating antennas have large footprints, limiting antenna arrays' density. High diffraction efficiency is essential for effective signal transmission, making it a crucial aspect of antenna design. Optical antennas need higher diffraction efficiency, compact size, and broader field of view to achieve this. The proposed work aims to design a single-etch grating antenna on a silicon-on-insulator (SOI) platform that emits light off-chip. The methodology combines the initial grating antenna designed using Finite-difference time-domain (FDTD) simulations and optimizes it with a genetic algorithm. The proposed design uses a transverse spliced grating, Bragg reflectors, and bottom reflector to achieve an impressive upward diffraction efficiency of nearly 88% operating in C -band centered at 1550 nm. The size of the proposed antenna is 2.8 μm and offers a wide far-field beam width of 38 ° x 136 °. This work enables new advancements in integrated waveguide grating antenna development, with potential applications in free-space optical interconnects and on-chip optical phased arrays.
波导光栅天线具有体积小、衍射效率高的特点，在集成光相控阵（OPA）的波束转向应用中仍是一项重大挑战。传统的波导光栅天线占地面积大，限制了天线阵列的密度。高衍射效率对有效的信号传输至关重要，因此是天线设计的一个关键方面。为此，光学天线需要更高的衍射效率、更小的尺寸和更宽的视场。本研究旨在在硅绝缘体（SOI）平台上设计一种单蚀刻光栅天线，该天线可在芯片外发射光线。该方法结合了利用有限差分时域 (FDTD) 仿真设计的初始光栅天线，并利用遗传算法对其进行优化。拟议的设计使用了横向拼接光栅、布拉格反射器和底部反射器，在以 1550 nm 为中心的 C 波段实现了近 88% 的惊人向上衍射效率。拟议的天线尺寸为 2.8 μm，远场波束宽度为 38 ° x 136 °。这项工作推动了集成波导光栅天线开发的新进展，有望应用于自由空间光互连和片上光学相控阵。
{"title":"Compact and Efficient Transverse Spliced Waveguide Grating Antenna for Integrated Optical Phased Array","authors":"Diksha Maurya;Devendra Chack;G. Vickey","doi":"10.1109/TNANO.2024.3459472","DOIUrl":"10.1109/TNANO.2024.3459472","url":null,"abstract":"Waveguide grating antenna with compact size and high diffraction efficiency remains a significant challenge in beam steering applications for integrated Optical Phased Arrays (OPA). Traditional waveguide grating antennas have large footprints, limiting antenna arrays' density. High diffraction efficiency is essential for effective signal transmission, making it a crucial aspect of antenna design. Optical antennas need higher diffraction efficiency, compact size, and broader field of view to achieve this. The proposed work aims to design a single-etch grating antenna on a silicon-on-insulator (SOI) platform that emits light off-chip. The methodology combines the initial grating antenna designed using Finite-difference time-domain (FDTD) simulations and optimizes it with a genetic algorithm. The proposed design uses a transverse spliced grating, Bragg reflectors, and bottom reflector to achieve an impressive upward diffraction efficiency of nearly 88% operating in C -band centered at 1550 nm. The size of the proposed antenna is 2.8 μm and offers a wide far-field beam width of 38 ° x 136 °. This work enables new advancements in integrated waveguide grating antenna development, with potential applications in free-space optical interconnects and on-chip optical phased arrays.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"665-672"},"PeriodicalIF":2.1,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Graphene-based dry electrodes have shown considerable promise in electrophysiological signal monitoring applications by providing a comfortable, irritant-free alternative to traditional wet electrodes. The proposed electrode was fabricated using a spray-coating technique by depositing reduced graphene oxide (rGO) on a polydimethylsiloxane (PDMS) substrate. The rGO/PDMS dry electrodes exhibit the capability to capture and transmit weak bio-electrical signals such as Electrocardiogram (ECGs) and Electromyogram (EMGs) without significant attenuation or distortion. Experimental results show that when compared to conventional wet Ag/AgCl electrodes, the fabricated rGO/PDMS electrodes measure higher-quality ECG signals with improved SNRs while offering similar contact quality and electrode-skin impedance despite being a dry electrode. The fabricated rGO/PDMS electrodes demonstrated excellent performance and applicability making them suitable for use in wearable long-term health monitoring devices.
{"title":"Reduced Graphene Oxide-Polydimethylsiloxane Based Flexible Dry Electrodes for Electrophysiological Signal Monitoring","authors":"Suraj Baloda;Sashank Krishna Sriram;Sumitra Singh;Navneet Gupta","doi":"10.1109/TNANO.2024.3459931","DOIUrl":"10.1109/TNANO.2024.3459931","url":null,"abstract":"Graphene-based dry electrodes have shown considerable promise in electrophysiological signal monitoring applications by providing a comfortable, irritant-free alternative to traditional wet electrodes. The proposed electrode was fabricated using a spray-coating technique by depositing reduced graphene oxide (rGO) on a polydimethylsiloxane (PDMS) substrate. The rGO/PDMS dry electrodes exhibit the capability to capture and transmit weak bio-electrical signals such as Electrocardiogram (ECGs) and Electromyogram (EMGs) without significant attenuation or distortion. Experimental results show that when compared to conventional wet Ag/AgCl electrodes, the fabricated rGO/PDMS electrodes measure higher-quality ECG signals with improved SNRs while offering similar contact quality and electrode-skin impedance despite being a dry electrode. The fabricated rGO/PDMS electrodes demonstrated excellent performance and applicability making them suitable for use in wearable long-term health monitoring devices.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"644-651"},"PeriodicalIF":2.1,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10679620","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-11DOI: 10.1109/TNANO.2024.3458427
Muhammad Saqlain;Muhammad Abuzar Baqir;Pankaj Kumar Choudhury
An ultrathin metasurface-based polarization-insensitive single-band terahertz (THz) sensor comprising graphene concentric rings and a thin layer of MXene was investigated for the human body cancer cells detection. The overall metamaterial configuration exhibits single narrow-band nearly-perfect absorption with a high value of quality factor due to a full-width-half-maximum of 0.033 THz at the resonance frequency of 3.793 THz. The results show a high sensitivity of the metamaterial configuration along with a stable operation under different incidence polarizations. The results reveal the designed structure is of potential in biomedical applications.
{"title":"MXene- and Graphene-Assisted THz Metamaterial for Cancer Cells Detection Based on Refractive Index Sensing","authors":"Muhammad Saqlain;Muhammad Abuzar Baqir;Pankaj Kumar Choudhury","doi":"10.1109/TNANO.2024.3458427","DOIUrl":"10.1109/TNANO.2024.3458427","url":null,"abstract":"An ultrathin metasurface-based polarization-insensitive single-band terahertz (THz) sensor comprising graphene concentric rings and a thin layer of MXene was investigated for the human body cancer cells detection. The overall metamaterial configuration exhibits single narrow-band nearly-perfect absorption with a high value of quality factor due to a full-width-half-maximum of 0.033 THz at the resonance frequency of 3.793 THz. The results show a high sensitivity of the metamaterial configuration along with a stable operation under different incidence polarizations. The results reveal the designed structure is of potential in biomedical applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"652-657"},"PeriodicalIF":2.1,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-10DOI: 10.1109/TNANO.2024.3457533
Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han
Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
{"title":"A Review of Ising Machines Implemented in Conventional and Emerging Technologies","authors":"Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han","doi":"10.1109/TNANO.2024.3457533","DOIUrl":"10.1109/TNANO.2024.3457533","url":null,"abstract":"Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"704-717"},"PeriodicalIF":2.1,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/TNANO.2024.3445455
Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori
Recently, machine learning systems have gained prominence in real-time, critical decision-making domains, such as autonomous driving and industrial automation. Their implementations should avoid overconfident predictions through uncertainty estimation. Bayesian Neural Networks (BayNNs) are principled methods for estimating predictive uncertainty. However, their computational costs and power consumption hinder their widespread deployment in edge AI. Utilizing Dropout as an approximation of the posterior distribution, binarizing the parameters of BayNNs, and further implementing them in spintronics-based computation-in-memory (CiM) hardware arrays can be a viable solution. However, designing hardware Dropout modules for convolutional neural network (CNN) topologies is challenging and expensive, as they may require numerous Dropout modules and need to use spatial information to drop certain elements. In this paper, we introduce MC-SpatialDropout, a spatial dropout-based approximate BayNNs with spintronics emerging devices. Our method utilizes the inherent stochasticity of spintronics devices for efficient implementation of the spatial dropout module compared to existing implementations. Furthermore, the number of dropout modules per network layer is reduced by a factor of $9times$ and energy consumption by a factor of $300times$ , while still achieving comparable predictive performance and uncertainty estimates compared to related works.
{"title":"Spatial-SpinDrop: Spatial Dropout-Based Binary Bayesian Neural Network With Spintronics Implementation","authors":"Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori","doi":"10.1109/TNANO.2024.3445455","DOIUrl":"10.1109/TNANO.2024.3445455","url":null,"abstract":"Recently, machine learning systems have gained prominence in real-time, critical decision-making domains, such as autonomous driving and industrial automation. Their implementations should avoid overconfident predictions through uncertainty estimation. Bayesian Neural Networks (BayNNs) are principled methods for estimating predictive uncertainty. However, their computational costs and power consumption hinder their widespread deployment in edge AI. Utilizing Dropout as an approximation of the posterior distribution, binarizing the parameters of BayNNs, and further implementing them in spintronics-based computation-in-memory (CiM) hardware arrays can be a viable solution. However, designing hardware Dropout modules for convolutional neural network (CNN) topologies is challenging and expensive, as they may require numerous Dropout modules and need to use spatial information to drop certain elements. In this paper, we introduce MC-SpatialDropout, a spatial dropout-based approximate BayNNs with spintronics emerging devices. Our method utilizes the inherent stochasticity of spintronics devices for efficient implementation of the spatial dropout module compared to existing implementations. Furthermore, the number of dropout modules per network layer is reduced by a factor of \u0000<inline-formula><tex-math>$9times$</tex-math></inline-formula>\u0000 and energy consumption by a factor of \u0000<inline-formula><tex-math>$300times$</tex-math></inline-formula>\u0000, while still achieving comparable predictive performance and uncertainty estimates compared to related works.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"636-643"},"PeriodicalIF":2.1,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/TNANO.2024.3447020
Jungyoun Kwak;Gihun Choe;Shimeng Yu
A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line (FEOL) p-type Si transistors. The proposed device structure ensures high on current density (Ion > 544 μA/μm) at V GS = 1 V, compensating for lower electron mobility in IWO (than Si). A comprehensive process flow is proposed to prove its integration potential. A custom monolithic 3D (M3D) process-design-kit (PDK) and standard cell library are developed for design-technology co-optimization (DTCO), examining the power, performance, and area (PPA) trade-offs in representative integrated circuits with ∼ 0.8 million of gates. The Verilog-to-GDS synthesis results show a 47% average area reduction in M3D circuits while maintaining a similar energy-delay-product (EDP) compared to the conventional 2D circuits.
{"title":"Design-Technology Co-Optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design","authors":"Jungyoun Kwak;Gihun Choe;Shimeng Yu","doi":"10.1109/TNANO.2024.3447020","DOIUrl":"10.1109/TNANO.2024.3447020","url":null,"abstract":"A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line (FEOL) p-type Si transistors. The proposed device structure ensures high on current density (Ion > 544 μA/μm) at V\u0000<sub>GS</sub>\u0000 = 1 V, compensating for lower electron mobility in IWO (than Si). A comprehensive process flow is proposed to prove its integration potential. A custom monolithic 3D (M3D) process-design-kit (PDK) and standard cell library are developed for design-technology co-optimization (DTCO), examining the power, performance, and area (PPA) trade-offs in representative integrated circuits with ∼ 0.8 million of gates. The Verilog-to-GDS synthesis results show a 47% average area reduction in M3D circuits while maintaining a similar energy-delay-product (EDP) compared to the conventional 2D circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"622-628"},"PeriodicalIF":2.1,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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