Pub Date : 2025-03-18DOI: 10.1109/TNANO.2025.3553037
Osama Yousuf;Andreu L. Glasmann;Alexander L. Mazzoni;Sina Najmaei;Gina C. Adam
Hardware accelerators based on emerging device technologies are gaining traction for inference workloads, but effective methods for their training remain an open area of research. We propose an efficient hardware-aware methodology for training neural networks with ternary weights that are mappable to emerging memory device arrays. We study device-network interactions across a variety of scenarios using simulated and experimentally measured datasets from ferroelectric field-effect transistor (FeFET) devices with varying characteristics. We quantify the impact of device non-idealities on network training by investigating device-level metrics, network-level metrics, loss landscapes, as well as parameter optimization trajectories. We validate our approach by mapping a hardware-aware solution to an emulated system with parameters calibrated to experimental measurements, highlighting several trade-offs. Hardware-aware training results on FeFET-based multi-layer perceptron networks, long short-term memory networks, and deep convolutional networks demonstrate competitive performance at lower overheads compared to existing schemes, indicating architectural and computational scalability. It is found that devices with low variability, non-linearity, and high dynamic range exhibit training characteristics closest to a software baseline. We provide evidence that device non-idealities inject noise during backpropagation, leading to sharper loss landscapes and higher-dimensional optimization trajectories, which make device networks more difficult to train than software counterparts. We also identify optimal operating voltages for investigated devices by utilizing our hardware-aware training and inference methodologies.
{"title":"Robust Hardware-Aware Neural Networks for FeFET-Based Accelerators","authors":"Osama Yousuf;Andreu L. Glasmann;Alexander L. Mazzoni;Sina Najmaei;Gina C. Adam","doi":"10.1109/TNANO.2025.3553037","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3553037","url":null,"abstract":"Hardware accelerators based on emerging device technologies are gaining traction for inference workloads, but effective methods for their training remain an open area of research. We propose an efficient hardware-aware methodology for training neural networks with ternary weights that are mappable to emerging memory device arrays. We study device-network interactions across a variety of scenarios using simulated and experimentally measured datasets from ferroelectric field-effect transistor (FeFET) devices with varying characteristics. We quantify the impact of device non-idealities on network training by investigating device-level metrics, network-level metrics, loss landscapes, as well as parameter optimization trajectories. We validate our approach by mapping a hardware-aware solution to an emulated system with parameters calibrated to experimental measurements, highlighting several trade-offs. Hardware-aware training results on FeFET-based multi-layer perceptron networks, long short-term memory networks, and deep convolutional networks demonstrate competitive performance at lower overheads compared to existing schemes, indicating architectural and computational scalability. It is found that devices with low variability, non-linearity, and high dynamic range exhibit training characteristics closest to a software baseline. We provide evidence that device non-idealities inject noise during backpropagation, leading to sharper loss landscapes and higher-dimensional optimization trajectories, which make device networks more difficult to train than software counterparts. We also identify optimal operating voltages for investigated devices by utilizing our hardware-aware training and inference methodologies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"189-200"},"PeriodicalIF":2.1,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143808879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-12DOI: 10.1109/TNANO.2025.3569071
Jiang Li;Yijun Cui;Chenghua Wang;Chongyan Gu;Weiqiang Liu
Emerging nano-device resistive random access memories (RRAMs) have become a promising primitive for PUF designs due to their non-volatility, high density, and low power, breaking through the physical limitations. A ring oscillator based physical unclonable function (RO PUF) is one of the most widely studied PUF designs due to its resilience against noise impacts and flexibility of implementation, but its reliability is susceptible to environmental variation and device aging. Present solutions to improve RO PUF reliability either require complicated RO selection algorithms or require discarding a large number of unstable challenge-response pairs (CRPs). This paper presents a highly reliable RRAM-based configurable RO PUF (RCRO-PUF). The proposed RCRO-PUF utilizes the intrinsic variations of RRAMs as the randomness source and applies the resistance variations of RRAMs to the frequency difference of current-starved (CS) ROs. By operating CS inverters in the subthreshold region, the RCRO-PUF achieves low power as well as high reliability. In addition, a reliability enhancement scheme is proposed to eliminate the effects of environmental variations and device aging. Based on Monte Carlo simulations of a 65 nm CMOS process, the proposed RCRO-PUF consumes only 16.18% of the hardware overhead for a regular RO PUF and has only 7.43 $mu W$ per CRP generation. The reliability of the RCRO-PUF is 99.51% over a broad range of temperatures from $-50,^{circ }$C to $150,^{circ }$C and $pm$20% supply voltage variations. It is also 4.7× more resilient to aging than state-of-the-art aging-resilient RO PUF.
{"title":"A Low-Power and Reliable RRAM-Based Configurable RO PUF With Aging Resilience","authors":"Jiang Li;Yijun Cui;Chenghua Wang;Chongyan Gu;Weiqiang Liu","doi":"10.1109/TNANO.2025.3569071","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3569071","url":null,"abstract":"Emerging nano-device resistive random access memories (RRAMs) have become a promising primitive for PUF designs due to their non-volatility, high density, and low power, breaking through the physical limitations. A ring oscillator based physical unclonable function (RO PUF) is one of the most widely studied PUF designs due to its resilience against noise impacts and flexibility of implementation, but its reliability is susceptible to environmental variation and device aging. Present solutions to improve RO PUF reliability either require complicated RO selection algorithms or require discarding a large number of unstable challenge-response pairs (CRPs). This paper presents a highly reliable RRAM-based configurable RO PUF (RCRO-PUF). The proposed RCRO-PUF utilizes the intrinsic variations of RRAMs as the randomness source and applies the resistance variations of RRAMs to the frequency difference of current-starved (CS) ROs. By operating CS inverters in the subthreshold region, the RCRO-PUF achieves low power as well as high reliability. In addition, a reliability enhancement scheme is proposed to eliminate the effects of environmental variations and device aging. Based on Monte Carlo simulations of a 65 nm CMOS process, the proposed RCRO-PUF consumes only 16.18% of the hardware overhead for a regular RO PUF and has only 7.43 <inline-formula><tex-math>$mu W$</tex-math></inline-formula> per CRP generation. The reliability of the RCRO-PUF is 99.51% over a broad range of temperatures from <inline-formula><tex-math>$-50,^{circ }$</tex-math></inline-formula>C to <inline-formula><tex-math>$150,^{circ }$</tex-math></inline-formula>C and <inline-formula><tex-math>$pm$</tex-math></inline-formula>20% supply voltage variations. It is also 4.7× more resilient to aging than state-of-the-art aging-resilient RO PUF.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"293-306"},"PeriodicalIF":2.1,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144125448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-11DOI: 10.1109/TNANO.2025.3549522
T. Cusati;D. Marian;A. Toral-Lopez;E. G. Marin;G. Iannaccone;G. Fiori
We investigate the exploitation of one of the latest advancements in the processing of the two-dimensional materials (2DMs) lateral heterostructures (LH) for electronic applications, which involves the generation of subnanometer one-dimensional (1D) channels embedded in a 2D crystal. Such study is done through a multiscale approach combining Density Functional Theory (DFT) and quantum transport calculations to propose and evaluate various Field-Effect Transistors (FETs) based on LH incorporating one-dimensional MoS$_{2}$ channels within monolayer WSe$_{2}$. We assess the ultimate performance of the transistors by considering different device configurations, lengths and orientations.
{"title":"Transistors With MoS$_{2}$ Subnanometer Channels Embedded in 2D WSe$_{2}$","authors":"T. Cusati;D. Marian;A. Toral-Lopez;E. G. Marin;G. Iannaccone;G. Fiori","doi":"10.1109/TNANO.2025.3549522","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3549522","url":null,"abstract":"We investigate the exploitation of one of the latest advancements in the processing of the two-dimensional materials (2DMs) lateral heterostructures (LH) for electronic applications, which involves the generation of subnanometer one-dimensional (1D) channels embedded in a 2D crystal. Such study is done through a multiscale approach combining Density Functional Theory (DFT) and quantum transport calculations to propose and evaluate various Field-Effect Transistors (FETs) based on LH incorporating one-dimensional MoS<inline-formula><tex-math>$_{2}$</tex-math></inline-formula> channels within monolayer WSe<inline-formula><tex-math>$_{2}$</tex-math></inline-formula>. We assess the ultimate performance of the transistors by considering different device configurations, lengths and orientations.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"152-156"},"PeriodicalIF":2.1,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143706787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-09DOI: 10.1109/TNANO.2025.3568626
Shiva Khani
This paper proposes an ultra-narrow band single-mode metamaterial perfect absorber consisting of periodic square graphene split rings and gold (Au) strips at the top layer, an insulator interlayer of SiO2, and an Au base layer. The absorber designed in this paper incorporates the benefits of conventional graphene plasma and metal plasma and has two applications a perfect absorber and a refractive index sensor (RIS). The finite difference time domain method is used to study the absorption and sensing characteristics of the designed topology. The results show an absorption peak at 3.092 THz with an absorption coefficient of 97.45%, and an absorption bandwidth of 88.11 GHz is achieved. In addition, the generated narrow absorption peak can be flexibly tuned by varying the graphene layer’s chemical potential. Also, high sensitivity and FoM values of 3040 GH/RIU and 34.5 RIU-1 are obtained for the proposed RIS, respectively. The performance of the suggested RIS is analyzed to measure the hemoglobin concentration in human blood. According to the results, the offered design can be a suitable option for future optical bio-sensors for biomedical applications.
{"title":"Hybrid Graphene-Plasmonic-Based Single-Mode Metamaterial Perfect Absorber With an Ultra-Narrow Band for Hemoglobin Concentration Sensing","authors":"Shiva Khani","doi":"10.1109/TNANO.2025.3568626","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3568626","url":null,"abstract":"This paper proposes an ultra-narrow band single-mode metamaterial perfect absorber consisting of periodic square graphene split rings and gold (Au) strips at the top layer, an insulator interlayer of SiO<sub>2</sub>, and an Au base layer. The absorber designed in this paper incorporates the benefits of conventional graphene plasma and metal plasma and has two applications a perfect absorber and a refractive index sensor (RIS). The finite difference time domain method is used to study the absorption and sensing characteristics of the designed topology. The results show an absorption peak at 3.092 THz with an absorption coefficient of 97.45%, and an absorption bandwidth of 88.11 GHz is achieved. In addition, the generated narrow absorption peak can be flexibly tuned by varying the graphene layer’s chemical potential. Also, high sensitivity and FoM values of 3040 GH/RIU and 34.5 RIU<sup>-1</sup> are obtained for the proposed RIS, respectively. The performance of the suggested RIS is analyzed to measure the hemoglobin concentration in human blood. According to the results, the offered design can be a suitable option for future optical bio-sensors for biomedical applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"537-545"},"PeriodicalIF":2.1,"publicationDate":"2025-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145455864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-05DOI: 10.1109/TNANO.2025.3548265
Lennart Weingarten;Kamalika Datta;Rolf Drechsler
Verification plays a major role in ensuring the functional correctness of any design. In recent years with growing complexity of processor designs, verification has assumed utmost importance. Simulation-based techniques cannot ensure completeness in verification, and in this regard formal methods prove crucial. Although formal methods guarantee completeness it is hard to quantify the exact time and space complexities. Recently some works have demonstrated that it is possible to achieve polynomial space and time complexities for various arithmetic circuits as well as for processors. In this paper we propose a Binary Decision Diagram (BDD) based Polynomial Formal Verification (PFV) approach for verifying processors. As a case study, we discuss the PFV for a multi-cycle processor (viz., MicroRV32) with support for combinational and sequential sub-systems. New data structures and code base are utilized to verify all the functional components. Experimental results reveal that the verification can indeed be performed in polynomial time.
{"title":"Polynomial Formal Verification of a RISC-V Processor","authors":"Lennart Weingarten;Kamalika Datta;Rolf Drechsler","doi":"10.1109/TNANO.2025.3548265","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3548265","url":null,"abstract":"Verification plays a major role in ensuring the functional correctness of any design. In recent years with growing complexity of processor designs, verification has assumed utmost importance. Simulation-based techniques cannot ensure completeness in verification, and in this regard formal methods prove crucial. Although formal methods guarantee completeness it is hard to quantify the exact time and space complexities. Recently some works have demonstrated that it is possible to achieve polynomial space and time complexities for various arithmetic circuits as well as for processors. In this paper we propose a <italic>Binary Decision Diagram</i> (BDD) based <italic>Polynomial Formal Verification</i> (PFV) approach for verifying processors. As a case study, we discuss the PFV for a multi-cycle processor (viz., MicroRV32) with support for combinational and sequential sub-systems. New data structures and code base are utilized to verify all the functional components. Experimental results reveal that the verification can indeed be performed in polynomial time.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"140-151"},"PeriodicalIF":2.1,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-03DOI: 10.1109/TNANO.2025.3546872
Min Kyun Sohn;Sang-Hoon Kim;Seong Hyun Lee;Jeong Woo Park;Dongwoo Suh
Recent research on transistors has focused on gate-all-around (GAA) structures, which possess better gate controllability than previous fin field-effect transistor (FinFET) structures. The characteristics of these devices have been optimized through different channel shapes. However, the characteristics of GAA-FETs with channels that have the same cross-sectional area warrant further research. In this study, we simulated n-type GAA-FETs using the Global TCAD Solutions simulation tool to analyze the effective characteristics obtained by setting equal cross-sectional areas. The results show that the total on-current exhibited up to 40.5% enhancement based on shape for the same area. Similarly, under the same conditions, the on/off current ratio exhibited a difference of approximately 1.5 times based on the shape. These findings help determine the optimal shape of the GAA channel and predict the performance when physical limitations restrict the channel shape. Furthermore, they contribute to improving the characteristics of GAA-FETs in mass production.
{"title":"Effects of 3D Channel Shape on the Performance of Nanoscale Gate-All-Around FETs","authors":"Min Kyun Sohn;Sang-Hoon Kim;Seong Hyun Lee;Jeong Woo Park;Dongwoo Suh","doi":"10.1109/TNANO.2025.3546872","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3546872","url":null,"abstract":"Recent research on transistors has focused on gate-all-around (GAA) structures, which possess better gate controllability than previous fin field-effect transistor (FinFET) structures. The characteristics of these devices have been optimized through different channel shapes. However, the characteristics of GAA-FETs with channels that have the same cross-sectional area warrant further research. In this study, we simulated n-type GAA-FETs using the Global TCAD Solutions simulation tool to analyze the effective characteristics obtained by setting equal cross-sectional areas. The results show that the total on-current exhibited up to 40.5% enhancement based on shape for the same area. Similarly, under the same conditions, the on/off current ratio exhibited a difference of approximately 1.5 times based on the shape. These findings help determine the optimal shape of the GAA channel and predict the performance when physical limitations restrict the channel shape. Furthermore, they contribute to improving the characteristics of GAA-FETs in mass production.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"129-133"},"PeriodicalIF":2.1,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Memristive systems have many promising features, making them suitable for both storage and computation. Memristors can perform logical operations and they can be used as the basic structures in digital circuits such as adders and multipliers. In this paper, at first, a new fast and low-cost Full-Adder (FA) is proposed using Single-cycle In-memristor XOR (SIXOR) and Three Memristors Stateful Logic (TMSL) gates that benefits from the advantages of both logics. Then, the proposed FA is used as one of the basic units inside two new array multipliers. The first proposed multiplier is designed in such a way that it has the lowest computational steps (delay) among the existing designs. This design has on average around 70% lower delay compared to the existing designs. The second proposed multiplier, as the low-cost design, requires a very low number of memristors thanks to reusing the existing resources more efficiently, while still having a low delay. This multiplier achieves on average around 36% memristor reduction compared to the state-of-the-art multipliers. Based on the analysis, both proposed array multipliers have notable efficiency advantages compared to the state-of-the-art designs based on different Figures of Merit (FoMs). For example, based on the balanced Figure of Merit (FoM), in which the number of computational steps and the number of required memristors have equal weight, the first and the second proposed multipliers achieve up to 4.6× and 14.9× improvements, respectively, compared to the existing designs in 64-bit multiplication.
{"title":"High-Speed and Low-Cost In-Array Memristive Multipliers Using SIXOR and TMSL Logics","authors":"Roya Rahimi Disfani;Mojtaba Valinataj;Nima TaheriNejad","doi":"10.1109/TNANO.2025.3566272","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3566272","url":null,"abstract":"Memristive systems have many promising features, making them suitable for both storage and computation. Memristors can perform logical operations and they can be used as the basic structures in digital circuits such as adders and multipliers. In this paper, at first, a new fast and low-cost Full-Adder (FA) is proposed using Single-cycle In-memristor XOR (SIXOR) and Three Memristors Stateful Logic (TMSL) gates that benefits from the advantages of both logics. Then, the proposed FA is used as one of the basic units inside two new array multipliers. The first proposed multiplier is designed in such a way that it has the lowest computational steps (delay) among the existing designs. This design has on average around 70% lower delay compared to the existing designs. The second proposed multiplier, as the low-cost design, requires a very low number of memristors thanks to reusing the existing resources more efficiently, while still having a low delay. This multiplier achieves on average around 36% memristor reduction compared to the state-of-the-art multipliers. Based on the analysis, both proposed array multipliers have notable efficiency advantages compared to the state-of-the-art designs based on different Figures of Merit (FoMs). For example, based on the balanced Figure of Merit (FoM), in which the number of computational steps and the number of required memristors have equal weight, the first and the second proposed multipliers achieve up to 4.6× and 14.9× improvements, respectively, compared to the existing designs in 64-bit multiplication.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"25 ","pages":"13-25"},"PeriodicalIF":2.1,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145996542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Silicene, a two-dimensional material with promising potential for future technological applications, has attracted considerable attention over the past decade. Recent research has focused on modifying silicene's electronic and magnetic properties by means of adsorption or substitutional doping. While the magnetic, electronic, and optical properties of doped silicene have been extensively studied, there is a noticeable gap in the literature regarding its mechanical properties. To address this issue, this study explores the mechanical characteristics of bilayer silicene doped with aluminum under various conditions. By employing molecular dynamics simulations, we investigate the influence of aluminum concentration, defects, temperature, and strain rate on the material's mechanical response. The findings reveal a monotonically decreasing strength with Al concentration in both the zigzag and armchair straining directions. Additionally, the material exhibits high sensitivity to defects, with even a small percentage significantly impairing its mechanical properties. Directional dependence is also observed, with the zigzag direction showing greater sensitivity than the armchair. As strain progresses, initial mono-vacancies evolve into more complex defects, hindering predictions of the mechanical response in certain cases. Lastly, strain rate sensitivity is evaluated, yielding values of 0.0485 and 0.0365 for the zigzag and armchair directions, respectively.
{"title":"Influence of Temperature, Strain Rate, and Vacancies on the Mechanical Properties of Aluminum-Doped Bilayer Silicene","authors":"Alexandre Melhorance Barboza;Luis César Rodríguez Aliaga;Daiara Fernandes de Faria;Ivan Napoleão Bastos","doi":"10.1109/TNANO.2025.3546749","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3546749","url":null,"abstract":"Silicene, a two-dimensional material with promising potential for future technological applications, has attracted considerable attention over the past decade. Recent research has focused on modifying silicene's electronic and magnetic properties by means of adsorption or substitutional doping. While the magnetic, electronic, and optical properties of doped silicene have been extensively studied, there is a noticeable gap in the literature regarding its mechanical properties. To address this issue, this study explores the mechanical characteristics of bilayer silicene doped with aluminum under various conditions. By employing molecular dynamics simulations, we investigate the influence of aluminum concentration, defects, temperature, and strain rate on the material's mechanical response. The findings reveal a monotonically decreasing strength with Al concentration in both the zigzag and armchair straining directions. Additionally, the material exhibits high sensitivity to defects, with even a small percentage significantly impairing its mechanical properties. Directional dependence is also observed, with the zigzag direction showing greater sensitivity than the armchair. As strain progresses, initial mono-vacancies evolve into more complex defects, hindering predictions of the mechanical response in certain cases. Lastly, strain rate sensitivity is evaluated, yielding values of 0.0485 and 0.0365 for the zigzag and armchair directions, respectively.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"134-139"},"PeriodicalIF":2.1,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10908092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cellular Nonlinear Networks (CNNs) are a well established computing approach in the domain of analog computing, known for massive parallelism and data processing locality that enable efficient hardware implementations. Combining CNN with non-volatile memristive devices holds the promise to overcome technological hurdles, like scalability issues, and high energy consumption, while also introducing richer dynamics into the field of CNN. Memristive devices based on the valence change mechanism (VCM) show great properties, like bipolar switching, tuneable resistance and non-volatility that are essential for the design of memristive CNN (M-CNN). In this study we design and investigate an uncoupled M-CNN cell implementing the EDGE detection task. This is the first paper investigating the resilience of M-CNN against device-to-device variability. To this end the first experimentally acquired Dynamic Route Map (DRM) of the M-CNN cell is employed. The comparison with simulations results allows for investigating the effect of mechanisms in the VCM device on the performance of the cell. The result of the computation is stored in the VCM device despite the unavoidable variability in the electrical behaviors of different device samples. Furthermore, the theoretically predicted richer dynamics of M-CNNs over traditional CNNs is demonstrated. This work provides crucial insights into design considerations of M-CNNs, especially as here first steps towards the comprehensive analysis on the effect of imperfections and variability of the memristor on M-CNN cell are taken.
{"title":"Dynamic Analysis of the Effect of the Device-to-Device Variability of Real-World Memristors on the Implementation of Uncoupled Memristive Cellular Nonlinear Networks","authors":"Yongmin Wang;Kristoffer Schnieders;Vasileios Ntinas;Alon Ascoli;Felix Cüppers;Susanne Hoffmann-Eifert;Stefan Wiefels;Ronald Tetzlaff;Vikas Rana;Stephan Menzel","doi":"10.1109/TNANO.2025.3545251","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3545251","url":null,"abstract":"Cellular Nonlinear Networks (CNNs) are a well established computing approach in the domain of analog computing, known for massive parallelism and data processing locality that enable efficient hardware implementations. Combining CNN with non-volatile memristive devices holds the promise to overcome technological hurdles, like scalability issues, and high energy consumption, while also introducing richer dynamics into the field of CNN. Memristive devices based on the valence change mechanism (VCM) show great properties, like bipolar switching, tuneable resistance and non-volatility that are essential for the design of memristive CNN (M-CNN). In this study we design and investigate an uncoupled M-CNN cell implementing the EDGE detection task. This is the first paper investigating the resilience of M-CNN against device-to-device variability. To this end the first experimentally acquired Dynamic Route Map (DRM) of the M-CNN cell is employed. The comparison with simulations results allows for investigating the effect of mechanisms in the VCM device on the performance of the cell. The result of the computation is stored in the VCM device despite the unavoidable variability in the electrical behaviors of different device samples. Furthermore, the theoretically predicted richer dynamics of M-CNNs over traditional CNNs is demonstrated. This work provides crucial insights into design considerations of M-CNNs, especially as here first steps towards the comprehensive analysis on the effect of imperfections and variability of the memristor on M-CNN cell are taken.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"121-128"},"PeriodicalIF":2.1,"publicationDate":"2025-02-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10902144","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143621924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper explores the enhanced resistive memory capabilities of titanium (Ti)-doped zinc oxide (ZnO) nanowires (NWs) based devices. Utilizing pulsed laser deposition (PLD), ZnO NWs were fabricated on a ZnO seed film (SF), while Ti films were deposited using an electron beam evaporation technique. Two distinct devices, TZO NWs and ZnO NWs, were created with gold (Au) interdigitated electrodes (IDE). The TZO NWs based device exhibited superior resistive memory performances, showcasing a maximum window of 2.6 V at +10 V and 1.2 V at –10 V, surpassing the ZnO NWs based device. The introduction of Ti doping in ZnO NWs provided additional active sites for charge collection, introducing localized energy levels and enhancing overall device performance. These findings collectively highlight the scalability of the TZO NWs based device for next-generation non-volatile resistive memory (NVRM) applications.
{"title":"Ti-Doped ZnO Nanowires: A Breakthrough in Non-Volatile Resistive Memory Application","authors":"Amitabha Nath;Madhuri Mishra;Subhananda Chakrabarti","doi":"10.1109/TNANO.2025.3544438","DOIUrl":"https://doi.org/10.1109/TNANO.2025.3544438","url":null,"abstract":"This paper explores the enhanced resistive memory capabilities of titanium (Ti)-doped zinc oxide (ZnO) nanowires (NWs) based devices. Utilizing pulsed laser deposition (PLD), ZnO NWs were fabricated on a ZnO seed film (SF), while Ti films were deposited using an electron beam evaporation technique. Two distinct devices, TZO NWs and ZnO NWs, were created with gold (Au) interdigitated electrodes (IDE). The TZO NWs based device exhibited superior resistive memory performances, showcasing a maximum window of 2.6 V at +10 V and 1.2 V at –10 V, surpassing the ZnO NWs based device. The introduction of Ti doping in ZnO NWs provided additional active sites for charge collection, introducing localized energy levels and enhancing overall device performance. These findings collectively highlight the scalability of the TZO NWs based device for next-generation non-volatile resistive memory (NVRM) applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"24 ","pages":"115-120"},"PeriodicalIF":2.1,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143594317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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