Pub Date : 2024-09-10DOI: 10.1109/TNANO.2024.3457533
Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han
Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.
{"title":"A Review of Ising Machines Implemented in Conventional and Emerging Technologies","authors":"Tingting Zhang;Qichao Tao;Bailiang Liu;Andrea Grimaldi;Eleonora Raimondo;Manuel Jiménez;María José Avedillo;Juan Nuñez;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona;Giovanni Finocchio;Jie Han","doi":"10.1109/TNANO.2024.3457533","DOIUrl":"10.1109/TNANO.2024.3457533","url":null,"abstract":"Ising machines have received growing interest as efficient and hardware-friendly solvers for combinatorial optimization problems (COPs). They search for the absolute or approximate ground states of the Ising model with a proper annealing process. In contrast to Ising machines built with superconductive or optical circuits, complementary metal-oxide-semiconductor (CMOS) Ising machines offer inexpensive fabrication, high scalability, and easy integration with mainstream semiconductor chips. As low-energy and CMOS-compatible emerging technologies, spintronics and phase-transition devices offer functionalities that can enhance the scalability and sampling performance of Ising machines. In this article, we survey various approaches in the process flow for solving COPs using CMOS, hybrid CMOS-spintronic, and phase-transition devices. First, the methods for formulating COPs as Ising problems and embedding Ising formulations to the topology of the Ising machine are reviewed. Then, Ising machines are classified by their underlying operational principles and reviewed from a perspective of hardware implementation. CMOS solutions are advantageous with denser connectivity, whereas hybrid CMOS-spintronic and phase-transition device-based solutions show great potential in energy efficiency and high performance. Finally, the challenges and prospects are discussed for the Ising formulation, embedding process, and implementation of Ising machines.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"704-717"},"PeriodicalIF":2.1,"publicationDate":"2024-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/TNANO.2024.3445455
Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori
Recently, machine learning systems have gained prominence in real-time, critical decision-making domains, such as autonomous driving and industrial automation. Their implementations should avoid overconfident predictions through uncertainty estimation. Bayesian Neural Networks (BayNNs) are principled methods for estimating predictive uncertainty. However, their computational costs and power consumption hinder their widespread deployment in edge AI. Utilizing Dropout as an approximation of the posterior distribution, binarizing the parameters of BayNNs, and further implementing them in spintronics-based computation-in-memory (CiM) hardware arrays can be a viable solution. However, designing hardware Dropout modules for convolutional neural network (CNN) topologies is challenging and expensive, as they may require numerous Dropout modules and need to use spatial information to drop certain elements. In this paper, we introduce MC-SpatialDropout, a spatial dropout-based approximate BayNNs with spintronics emerging devices. Our method utilizes the inherent stochasticity of spintronics devices for efficient implementation of the spatial dropout module compared to existing implementations. Furthermore, the number of dropout modules per network layer is reduced by a factor of $9times$ and energy consumption by a factor of $300times$, while still achieving comparable predictive performance and uncertainty estimates compared to related works.
{"title":"Spatial-SpinDrop: Spatial Dropout-Based Binary Bayesian Neural Network With Spintronics Implementation","authors":"Soyed Tuhin Ahmed;Kamal Danouchi;Michael Hefenbrock;Guillaume Prenat;Lorena Anghel;Mehdi B. Tahoori","doi":"10.1109/TNANO.2024.3445455","DOIUrl":"10.1109/TNANO.2024.3445455","url":null,"abstract":"Recently, machine learning systems have gained prominence in real-time, critical decision-making domains, such as autonomous driving and industrial automation. Their implementations should avoid overconfident predictions through uncertainty estimation. Bayesian Neural Networks (BayNNs) are principled methods for estimating predictive uncertainty. However, their computational costs and power consumption hinder their widespread deployment in edge AI. Utilizing Dropout as an approximation of the posterior distribution, binarizing the parameters of BayNNs, and further implementing them in spintronics-based computation-in-memory (CiM) hardware arrays can be a viable solution. However, designing hardware Dropout modules for convolutional neural network (CNN) topologies is challenging and expensive, as they may require numerous Dropout modules and need to use spatial information to drop certain elements. In this paper, we introduce MC-SpatialDropout, a spatial dropout-based approximate BayNNs with spintronics emerging devices. Our method utilizes the inherent stochasticity of spintronics devices for efficient implementation of the spatial dropout module compared to existing implementations. Furthermore, the number of dropout modules per network layer is reduced by a factor of \u0000<inline-formula><tex-math>$9times$</tex-math></inline-formula>\u0000 and energy consumption by a factor of \u0000<inline-formula><tex-math>$300times$</tex-math></inline-formula>\u0000, while still achieving comparable predictive performance and uncertainty estimates compared to related works.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"636-643"},"PeriodicalIF":2.1,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142225591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-21DOI: 10.1109/TNANO.2024.3447020
Jungyoun Kwak;Gihun Choe;Shimeng Yu
A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line (FEOL) p-type Si transistors. The proposed device structure ensures high on current density (Ion > 544 μA/μm) at VGS = 1 V, compensating for lower electron mobility in IWO (than Si). A comprehensive process flow is proposed to prove its integration potential. A custom monolithic 3D (M3D) process-design-kit (PDK) and standard cell library are developed for design-technology co-optimization (DTCO), examining the power, performance, and area (PPA) trade-offs in representative integrated circuits with ∼ 0.8 million of gates. The Verilog-to-GDS synthesis results show a 47% average area reduction in M3D circuits while maintaining a similar energy-delay-product (EDP) compared to the conventional 2D circuits.
{"title":"Design-Technology Co-Optimization for Stacked Nanosheet Oxide Channel Transistors in Monolithic 3D Integrated Circuit Design","authors":"Jungyoun Kwak;Gihun Choe;Shimeng Yu","doi":"10.1109/TNANO.2024.3447020","DOIUrl":"10.1109/TNANO.2024.3447020","url":null,"abstract":"A back-end-of-line (BEOL)-compatible stacked nanosheet tungsten doped indium oxide (IWO) n-type channel transistor is proposed for complementary logic gate operation with front-end-of-line (FEOL) p-type Si transistors. The proposed device structure ensures high on current density (Ion > 544 μA/μm) at V\u0000<sub>GS</sub>\u0000 = 1 V, compensating for lower electron mobility in IWO (than Si). A comprehensive process flow is proposed to prove its integration potential. A custom monolithic 3D (M3D) process-design-kit (PDK) and standard cell library are developed for design-technology co-optimization (DTCO), examining the power, performance, and area (PPA) trade-offs in representative integrated circuits with ∼ 0.8 million of gates. The Verilog-to-GDS synthesis results show a 47% average area reduction in M3D circuits while maintaining a similar energy-delay-product (EDP) compared to the conventional 2D circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"622-628"},"PeriodicalIF":2.1,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Convolutional neural networks have remarkable performance in artificial intelligence, although at the cost of computationally demanding processes within a single inference. Simultaneously, the underlying chip process is reaching its constraints as Moore's law diminishes. Stochastic computation, as a hardware-friendly and unconventional approach, can alleviate the burden of sophisticated arithmetic at the circuit level. This work presents a novel stochastic computing (SC) multiplier that employs an extension-uniform approach to create bit sequences without relying on logical gates. In addition, we propose a stochastic-binary domain arithmetic method to achieve low-cost hardware implementation and low power dissipation. The 4n-bit widths are partitioned into n 4-bit widths, with the high-precision components executed in the binary domain and the low-precision components executed in the stochastic domain. Additionally, a hardware-compatible circuit for compensating faults is also introduced. The accelerator on cifar10 using stochastic binary hybrid domain spatial coding (SHSC) multiplier achieves better performance than the fixed-point counterpart, with a 33.7% reduction in area and 23% reduction in power.
卷积神经网络在人工智能领域有着卓越的性能，但其代价是单个推理过程的计算量巨大。与此同时，随着摩尔定律的减弱，底层芯片工艺也达到了极限。随机计算作为一种对硬件友好的非常规方法，可以减轻电路级复杂运算的负担。本研究提出了一种新颖的随机计算（SC）乘法器，它采用了一种扩展均匀的方法来创建位序列，而无需依赖逻辑门。此外，我们还提出了一种随机二进制域算术方法，以实现低成本硬件实现和低功耗耗散。4n 位宽度被划分为 n 个 4 位宽度，高精度部分在二进制域中执行，低精度部分在随机域中执行。此外，还引入了用于补偿故障的硬件兼容电路。在 cifar10 上使用随机二进制混合域空间编码（SHSC）乘法器的加速器比对应的定点乘法器性能更好，面积减少了 33.7%，功耗降低了 23%。
{"title":"Stochastic-Binary Hybrid Spatial Coding Multiplier for Convolutional Neural Network Accelerator","authors":"Yakun Zhou;Jiajun Yan;Yizhuo Zhou;Ziyang Shao;Jienan Chen","doi":"10.1109/TNANO.2024.3444278","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3444278","url":null,"abstract":"Convolutional neural networks have remarkable performance in artificial intelligence, although at the cost of computationally demanding processes within a single inference. Simultaneously, the underlying chip process is reaching its constraints as Moore's law diminishes. Stochastic computation, as a hardware-friendly and unconventional approach, can alleviate the burden of sophisticated arithmetic at the circuit level. This work presents a novel stochastic computing (SC) multiplier that employs an extension-uniform approach to create bit sequences without relying on logical gates. In addition, we propose a stochastic-binary domain arithmetic method to achieve low-cost hardware implementation and low power dissipation. The 4n-bit widths are partitioned into n 4-bit widths, with the high-precision components executed in the binary domain and the low-precision components executed in the stochastic domain. Additionally, a hardware-compatible circuit for compensating faults is also introduced. The accelerator on cifar10 using stochastic binary hybrid domain spatial coding (SHSC) multiplier achieves better performance than the fixed-point counterpart, with a 33.7% reduction in area and 23% reduction in power.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"600-605"},"PeriodicalIF":2.1,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142084497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Silicon cold source field-effect transistor (CSFET) offers a compelling solution for low-power logic devices due to its ability to achieve sub-60 mV/dec steep-slope switching with innovative source engineering, while maintaining compatibility with Silicon CMOS technology. Developing a compact model for CSFETs is crucial for advancing our understanding of these novel devices and enabling advanced design and simulation based on CSFETs. To this end, this work introduces a compact model specifically designed for n-type double-gate CSFETs. Employing the Landauer-Büttiker approach alongside machine learning (ML)-based band energy profiles, our model accounts for thermal current via ballistic transport and tunneling current from source-to-drain direct tunneling. Consequently, our model accurately represents the drain current-gate voltage relationship in CSFETs. Furthermore, our proposed model is applicable to both CSFETs and conventional MOSFETs. This enables benchmarking analysis between CSFETs and conventional MOSFETs, shedding light on their comparative performance metrics.
{"title":"Machine Learning-Based Compact Modeling of Silicon Cold Source Field-Effect Transistors","authors":"Haoqing Xu;Weizhuo Gan;Shujin Guo;Shengli Zhang;Zhenhua Wu","doi":"10.1109/TNANO.2024.3442476","DOIUrl":"https://doi.org/10.1109/TNANO.2024.3442476","url":null,"abstract":"The Silicon cold source field-effect transistor (CSFET) offers a compelling solution for low-power logic devices due to its ability to achieve sub-60 mV/dec steep-slope switching with innovative source engineering, while maintaining compatibility with Silicon CMOS technology. Developing a compact model for CSFETs is crucial for advancing our understanding of these novel devices and enabling advanced design and simulation based on CSFETs. To this end, this work introduces a compact model specifically designed for n-type double-gate CSFETs. Employing the Landauer-Büttiker approach alongside machine learning (ML)-based band energy profiles, our model accounts for thermal current via ballistic transport and tunneling current from source-to-drain direct tunneling. Consequently, our model accurately represents the drain current-gate voltage relationship in CSFETs. Furthermore, our proposed model is applicable to both CSFETs and conventional MOSFETs. This enables benchmarking analysis between CSFETs and conventional MOSFETs, shedding light on their comparative performance metrics.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"615-621"},"PeriodicalIF":2.1,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142165016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-05DOI: 10.1109/TNANO.2024.3438542
Md Mazharul Islam;Shamiul Alam;Mohammad Adnan Jahangir;Garrett S. Rose;Suman Datta;Vijaykrishnan Narayanan;Sumeet Kumar Gupta;Ahmedullah Aziz
Energy-efficient sense amplifier (SA) circuits are essential for reliable detection of stored memory states in emerging memory systems. In this work, we introduce three novel sense amplifier topologies based on phase transition materials (PTM) in addition to the previously proposed one, collectively analyzing all four designs tailored for non-volatile memory applications. We utilize the abrupt switching and volatile hysteretic characteristics of PTMs which enables efficient and fast sensing operation in our proposed SA topologies. We provide comprehensive details of their functionality and assess how process variations impact their performance metrics. Our proposed sense amplifier topologies manifest notable performance enhancement. We achieve a ∼67% reduction in sensing delay and a ∼80% decrease in sensing power for current sensing. For voltage sensing, we achieve a ∼75% reduction in sensing delay and a ∼33% decrease in sensing power. Moreover, the proposed SA topologies exhibit improved variation robustness compared to conventional SAs. We also scrutinize the dependence of transistor mirroring window and PTM transition voltages on several device parameters to determine the optimum operating conditions and stance of tunability for each of the proposed SA topologies.
在新兴存储器系统中，高能效感应放大器（SA）电路对于存储存储器状态的可靠检测至关重要。在这项工作中，除了之前提出的基于相变材料（PTM）的新型感应放大器拓扑结构外，我们还介绍了三种新型感应放大器拓扑结构，并针对非易失性存储器应用对所有四种设计进行了综合分析。我们利用 PTM 的突然开关和易挥发滞后特性，在我们提出的 SA 拓扑中实现了高效、快速的感应操作。我们提供了有关其功能的全面细节，并评估了工艺变化对其性能指标的影响。我们提出的感应放大器拓扑结构具有显著的性能提升。在电流感应方面，我们将感应延迟降低了 ∼ 67%，感应功率降低了 ∼ 80%。在电压传感方面，我们实现了传感延迟降低 75% 和传感功率降低 33% 的目标。此外，与传统的传感器相比，所提出的传感器拓扑结构具有更好的变化鲁棒性。我们还仔细研究了晶体管镜像窗口和 PTM 转换电压对多个器件参数的依赖性，以确定每种拟议 SA 拓扑的最佳工作条件和可调性。
{"title":"Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing","authors":"Md Mazharul Islam;Shamiul Alam;Mohammad Adnan Jahangir;Garrett S. Rose;Suman Datta;Vijaykrishnan Narayanan;Sumeet Kumar Gupta;Ahmedullah Aziz","doi":"10.1109/TNANO.2024.3438542","DOIUrl":"10.1109/TNANO.2024.3438542","url":null,"abstract":"Energy-efficient sense amplifier (SA) circuits are essential for reliable detection of stored memory states in emerging memory systems. In this work, we introduce three novel sense amplifier topologies based on phase transition materials (PTM) in addition to the previously proposed one, collectively analyzing all four designs tailored for non-volatile memory applications. We utilize the abrupt switching and volatile hysteretic characteristics of PTMs which enables efficient and fast sensing operation in our proposed SA topologies. We provide comprehensive details of their functionality and assess how process variations impact their performance metrics. Our proposed sense amplifier topologies manifest notable performance enhancement. We achieve a ∼67% reduction in sensing delay and a ∼80% decrease in sensing power for current sensing. For voltage sensing, we achieve a ∼75% reduction in sensing delay and a ∼33% decrease in sensing power. Moreover, the proposed SA topologies exhibit improved variation robustness compared to conventional SAs. We also scrutinize the dependence of transistor mirroring window and PTM transition voltages on several device parameters to determine the optimum operating conditions and stance of tunability for each of the proposed SA topologies.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"606-614"},"PeriodicalIF":2.1,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141945961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-02DOI: 10.1109/TNANO.2024.3437669
Aadil Anam;S. Intekhab Amin;Dinesh Prasad
In this noteworthy paper, we present a novel and comprehensive investigation into the optimization of performance parameters for the conventional U-Gate III-V line TFET through TCAD simulation. Our unprecedented threefold optimization strategy encompasses multiple facets, marking a significant contribution to the field. Firstly, in our pursuit of enhancing OFF current performance, we implemented a pioneering approach by employing a highly doped p+-pocket, effectively suppressing parasitic corner tunneling and resulting in a remarkable 258.14-fold improvement in OFF current. Secondly, we embark on another unexplored avenue in conventional U-Gate TFET by implementing the negative capacitance (NC) effect into it. The NC implementation leads to substantial improvements in ON current and subthreshold swing (SS), with an impressive 4.176-fold enhancement in ION/IOFF and a 2.151-fold reduction in average subthreshold swing (AVSS) (from 33.26 mV/dec to 15.46 mV/dec) compared to the conventional design. In the third and final stage of our optimization strategy, we efficiently combine the benefits of p+-pocket doping and NC implementation. By doing this, we simultaneously enhance the OFF current (improved by 226.91 times), ON current (improved by 1.92 times), ION/IOFF ratio (enhanced by 435.55 times), and AVSS (improved by an outstanding 2.861 times, from 33.48 mV/dec to 11.7 mV/dec), demonstrating the effectiveness of our holistic approach. This comprehensive study sets a new benchmark for U-Gate III-V line TFET optimization, paving the way for advanced applications in low-power digital circuits.
{"title":"Optimizing InGaAs/GaAsSb Staggered Bandgap U-Gate Line TFET With p+-Pocket Implant and Negative Capacitance for Enhanced Performance","authors":"Aadil Anam;S. Intekhab Amin;Dinesh Prasad","doi":"10.1109/TNANO.2024.3437669","DOIUrl":"10.1109/TNANO.2024.3437669","url":null,"abstract":"In this noteworthy paper, we present a novel and comprehensive investigation into the optimization of performance parameters for the conventional U-Gate III-V line TFET through TCAD simulation. Our unprecedented threefold optimization strategy encompasses multiple facets, marking a significant contribution to the field. Firstly, in our pursuit of enhancing OFF current performance, we implemented a pioneering approach by employing a highly doped p\u0000<sup>+</sup>\u0000-pocket, effectively suppressing parasitic corner tunneling and resulting in a remarkable 258.14-fold improvement in OFF current. Secondly, we embark on another unexplored avenue in conventional U-Gate TFET by implementing the negative capacitance (NC) effect into it. The NC implementation leads to substantial improvements in ON current and subthreshold swing (SS), with an impressive 4.176-fold enhancement in I\u0000<sub>ON</sub>\u0000/I\u0000<sub>OFF</sub>\u0000 and a 2.151-fold reduction in average subthreshold swing (AVSS) (from 33.26 mV/dec to 15.46 mV/dec) compared to the conventional design. In the third and final stage of our optimization strategy, we efficiently combine the benefits of p\u0000<sup>+</sup>\u0000-pocket doping and NC implementation. By doing this, we simultaneously enhance the OFF current (improved by 226.91 times), ON current (improved by 1.92 times), I\u0000<sub>ON</sub>\u0000/I\u0000<sub>OFF</sub>\u0000 ratio (enhanced by 435.55 times), and AVSS (improved by an outstanding 2.861 times, from 33.48 mV/dec to 11.7 mV/dec), demonstrating the effectiveness of our holistic approach. This comprehensive study sets a new benchmark for U-Gate III-V line TFET optimization, paving the way for advanced applications in low-power digital circuits.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"584-590"},"PeriodicalIF":2.1,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141885149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-31DOI: 10.1109/TNANO.2024.3436014
Avinash Lahgere;Alok Kumar Kamal;Rishu Kumar
In this article, we have reported a tunnel field-effect transistor (TFET) based unified random access memory (T-URAM), integrating nonvolatile memory (NVM) and single transistor (1T) DRAM into a single TFET device. Unlike previously published URAMs, the proposed T-URAM utilizes band-to-band tunneling (BTBT) conduction for programming both NVM and 1T DRAM. This approach offers two main advantages: low supply voltage requirements and disturbance-free NVM operation. Additionally, T-URAM ensures interference-free memory operation through separate gates for NVM and 1T DRAM. Simulations show that T-URAM requires 1.5× to 4.5× less supply voltage compared to existing URAMs. At 358 K, the retention time (RT) of T-URAM in 1T DRAM mode is 500 ms, which is $sim$ 62.5× and $sim$ 7.8× higher than the buried n-well bulk FinFET URAM and ITRS prediction, respectively. For NVM mode, the RT at a gate length of 50 nm matches that of previously reported URAMs. The sense margin of T-URAM in 1T DRAM mode at 358 K is about 1.9 $mu$A/$mu$m, which is roughly 7.6× higher than TFT-based URAM. We also propose a 2x2 crossbar memory array implementation using T-URAM. These findings pave the way for designing low-power, multi-purpose embedded memory for future applications.
{"title":"Band-to-Band Tunneling Based Unified RAM (URAM) for Low Power Embedded Applications","authors":"Avinash Lahgere;Alok Kumar Kamal;Rishu Kumar","doi":"10.1109/TNANO.2024.3436014","DOIUrl":"10.1109/TNANO.2024.3436014","url":null,"abstract":"In this article, we have reported a tunnel field-effect transistor (TFET) based unified random access memory (T-URAM), integrating nonvolatile memory (NVM) and single transistor (1T) DRAM into a single TFET device. Unlike previously published URAMs, the proposed T-URAM utilizes band-to-band tunneling (BTBT) conduction for programming both NVM and 1T DRAM. This approach offers two main advantages: low supply voltage requirements and disturbance-free NVM operation. Additionally, T-URAM ensures interference-free memory operation through separate gates for NVM and 1T DRAM. Simulations show that T-URAM requires 1.5× to 4.5× less supply voltage compared to existing URAMs. At 358 K, the retention time (RT) of T-URAM in 1T DRAM mode is 500 ms, which is \u0000<inline-formula><tex-math>$sim$</tex-math></inline-formula>\u0000 62.5× and \u0000<inline-formula><tex-math>$sim$</tex-math></inline-formula>\u0000 7.8× higher than the buried n-well bulk FinFET URAM and ITRS prediction, respectively. For NVM mode, the RT at a gate length of 50 nm matches that of previously reported URAMs. The sense margin of T-URAM in 1T DRAM mode at 358 K is about 1.9 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000A/\u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000m, which is roughly 7.6× higher than TFT-based URAM. We also propose a 2x2 crossbar memory array implementation using T-URAM. These findings pave the way for designing low-power, multi-purpose embedded memory for future applications.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"629-635"},"PeriodicalIF":2.1,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141869765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Electrochemical biosensors often encounter inaccuracies and unreliability in measurements due to non-ideal effects such as drift and hysteresis. This study presents an innovative back-end calibration circuit specifically designed to mitigate hysteresis and drift effects in potentiometric ruthenium dioxide (RuO2) dopamine biosensors. The proposed calibration circuit combines analog circuitry with a microcontroller, employing gain-configured inverting amplifiers to individually correct hysteresis effects induced by both low and high dopamine concentrations. Furthermore, an inverse drift signal is applied to counteract overall drift effects, significantly improving the precision of dopamine measurements. The biosensor utilizes a radiofrequency sputtering system to deposit RuO2 as a sensing membrane. A sequential drop-casting process is employed to add functional layers. Atomic force microscopy is utilized to characterize the surface morphology of the RuO2 sensing membrane, confirming its uniform pattern and exceptional flatness. Reproducibility and repeatability experiments validate the stability and consistency of the fabricated RuO2 dopamine biosensor, underscoring its potential for practical applications in the diagnosis of neurological disorders.
{"title":"The Back-End Calibration Circuit for Reducing Hysteresis and Drift Effects of the Potentiometric RuO2 Dopamine Biosensor","authors":"Po-Yu Kuo;Ming-Tai Hsu;Jung-Chuan Chou;Chih-Hsien Lai;Yu-Hsun Nien;Po-Hui Yang;Chi-Han Liao;Wei-Shun Chen;Jyun-Ming Huang","doi":"10.1109/TNANO.2024.3435447","DOIUrl":"10.1109/TNANO.2024.3435447","url":null,"abstract":"Electrochemical biosensors often encounter inaccuracies and unreliability in measurements due to non-ideal effects such as drift and hysteresis. This study presents an innovative back-end calibration circuit specifically designed to mitigate hysteresis and drift effects in potentiometric ruthenium dioxide (RuO\u0000<sub>2</sub>\u0000) dopamine biosensors. The proposed calibration circuit combines analog circuitry with a microcontroller, employing gain-configured inverting amplifiers to individually correct hysteresis effects induced by both low and high dopamine concentrations. Furthermore, an inverse drift signal is applied to counteract overall drift effects, significantly improving the precision of dopamine measurements. The biosensor utilizes a radiofrequency sputtering system to deposit RuO\u0000<sub>2</sub>\u0000 as a sensing membrane. A sequential drop-casting process is employed to add functional layers. Atomic force microscopy is utilized to characterize the surface morphology of the RuO\u0000<sub>2</sub>\u0000 sensing membrane, confirming its uniform pattern and exceptional flatness. Reproducibility and repeatability experiments validate the stability and consistency of the fabricated RuO\u0000<sub>2</sub>\u0000 dopamine biosensor, underscoring its potential for practical applications in the diagnosis of neurological disorders.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"578-583"},"PeriodicalIF":2.1,"publicationDate":"2024-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141869766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-18DOI: 10.1109/TNANO.2024.3430221
Ji Kai Wang;Collin VanEssen;Nuoyi Yang;Zhi Cheng Yuan;Prasad S. Gudem;Diego Kienle;Mani Vaidyanathan
The potential to utilize negative-capacitance dynamics in a ferroelectric capacitor as a back-end-of-line (BEOL) element to construct a tuned oscillator operating in the GHz range is proposed and investigated. Using tools established in the field of non-linear dynamics, the operating principles of the circuit are rigorously explored, a criterion for oscillation is developed, and amplitude and frequency control are investigated. Furthermore, this novel architecture is compared with a traditional LC oscillator. Through the comparison, we find that the FE oscillator can provide a substantially larger tuning range (149%, between 1.29 GHz–8.75 GHz, vs. 50% achieved by the traditional LC oscillator) and requires a vastly lower on-chip area $(sim!! 50,{bm{mu}}{{mathbf{m}}^2},text{vs}{rm{.}},sim 40000,{bm{mu}}{{mathbf{m}}^2})$, while achieving a similar figure of merit $mathbf{FO}{{mathbf{M}}_2}$ (reduced by only 6 dB). Such improvements motivate the continued exploration and development of negative-capacitance ferroelectrics as BEOL elements that can significantly improve integrated-circuit performance.
{"title":"Toward a GHz-Frequency BEOL Ferroelectric Negative-Capacitance Oscillator With a Wide Tuning Range","authors":"Ji Kai Wang;Collin VanEssen;Nuoyi Yang;Zhi Cheng Yuan;Prasad S. Gudem;Diego Kienle;Mani Vaidyanathan","doi":"10.1109/TNANO.2024.3430221","DOIUrl":"10.1109/TNANO.2024.3430221","url":null,"abstract":"The potential to utilize negative-capacitance dynamics in a ferroelectric capacitor as a back-end-of-line (BEOL) element to construct a tuned oscillator operating in the GHz range is proposed and investigated. Using tools established in the field of non-linear dynamics, the operating principles of the circuit are rigorously explored, a criterion for oscillation is developed, and amplitude and frequency control are investigated. Furthermore, this novel architecture is compared with a traditional LC oscillator. Through the comparison, we find that the FE oscillator can provide a substantially larger tuning range (149%, between 1.29 GHz–8.75 GHz, vs. 50% achieved by the traditional LC oscillator) and requires a vastly lower on-chip area \u0000<inline-formula><tex-math>$(sim!! 50,{bm{mu}}{{mathbf{m}}^2},text{vs}{rm{.}},sim 40000,{bm{mu}}{{mathbf{m}}^2})$</tex-math></inline-formula>\u0000, while achieving a similar figure of merit \u0000<inline-formula><tex-math>$mathbf{FO}{{mathbf{M}}_2}$</tex-math></inline-formula>\u0000 (reduced by only 6 dB). Such improvements motivate the continued exploration and development of negative-capacitance ferroelectrics as BEOL elements that can significantly improve integrated-circuit performance.","PeriodicalId":449,"journal":{"name":"IEEE Transactions on Nanotechnology","volume":"23 ","pages":"591-599"},"PeriodicalIF":2.1,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141745153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：