Pub Date : 2024-07-26DOI: 10.1109/TSM.2024.3434489
Chae Sun Kim;Hae Rang Roh;Yongseok Lee;Taekyoon Park;Chanmin Lee;Jong Min Lee
The consistent decrease in the open ratio of wafers has spurred a demand for advanced endpoint detection (EPD) techniques to ensure accurate plasma etching in nonlinear optical emission spectroscopy (OES) data characterized by a low signal-to-noise ratio. Additionally, precise detection of endpoint is hindered by variations between plasma chambers arising from diverse issues. To address these issues, this study proposes a nonlinear manifold learning-based EPD model and a chamber condition identification framework. The EPD model demonstrates the capability to extract endpoint-related latent variables from complex nonlinear OES data. Moreover, the model exhibits the ability to generalize to larger datasets through density-based time series clustering. The chamber condition identification framework not only classifies plasma conditions but also automates the determination of the conditions for incoming new wafers. Evaluation of the proposed approach, conducted using actual OES data from multiple chambers, demonstrated that the EPD model outperformed other models which are based on diverse dimensionality reduction approaches. Furthermore, the chamber condition identification process successfully identified condition variations and accurately determined the plasma condition of new data. Moreover, conducting EPD modeling for separate conditions rather than collectively for diverse conditions demonstrated superior detection results, underscoring the importance of the chamber condition identification process.
晶圆开孔率的持续下降刺激了对先进端点检测 (EPD) 技术的需求，以确保非线性光学发射光谱 (OES) 数据中准确的等离子刻蚀，其特点是信噪比低。此外，端点的精确检测还受到等离子体室之间因各种问题而产生的差异的阻碍。为解决这些问题，本研究提出了基于流形学习的非线性 EPD 模型和腔室条件识别框架。EPD 模型展示了从复杂的非线性 OES 数据中提取与终点相关的潜在变量的能力。此外，通过基于密度的时间序列聚类，该模型还展示了对更大数据集进行泛化的能力。腔室条件识别框架不仅能对等离子条件进行分类，还能自动确定进入新晶片的条件。使用来自多个腔室的实际 OES 数据对所提出的方法进行了评估，结果表明 EPD 模型的性能优于其他基于不同降维方法的模型。此外，腔室条件识别过程成功识别了条件变化，并准确确定了新数据的等离子体条件。此外，针对单独条件而不是针对不同条件的集体进行 EPD 建模，可获得更优越的检测结果，这突出表明了腔室条件识别过程的重要性。
{"title":"Plasma Etching Endpoint Detection in the Presence of Chamber Variations Through Nonlinear Manifold Learning and Density-Based Clustering","authors":"Chae Sun Kim;Hae Rang Roh;Yongseok Lee;Taekyoon Park;Chanmin Lee;Jong Min Lee","doi":"10.1109/TSM.2024.3434489","DOIUrl":"10.1109/TSM.2024.3434489","url":null,"abstract":"The consistent decrease in the open ratio of wafers has spurred a demand for advanced endpoint detection (EPD) techniques to ensure accurate plasma etching in nonlinear optical emission spectroscopy (OES) data characterized by a low signal-to-noise ratio. Additionally, precise detection of endpoint is hindered by variations between plasma chambers arising from diverse issues. To address these issues, this study proposes a nonlinear manifold learning-based EPD model and a chamber condition identification framework. The EPD model demonstrates the capability to extract endpoint-related latent variables from complex nonlinear OES data. Moreover, the model exhibits the ability to generalize to larger datasets through density-based time series clustering. The chamber condition identification framework not only classifies plasma conditions but also automates the determination of the conditions for incoming new wafers. Evaluation of the proposed approach, conducted using actual OES data from multiple chambers, demonstrated that the EPD model outperformed other models which are based on diverse dimensionality reduction approaches. Furthermore, the chamber condition identification process successfully identified condition variations and accurately determined the plasma condition of new data. Moreover, conducting EPD modeling for separate conditions rather than collectively for diverse conditions demonstrated superior detection results, underscoring the importance of the chamber condition identification process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"553-566"},"PeriodicalIF":2.3,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141778550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-15DOI: 10.1109/tsm.2024.3428936
Giyoung Yang, Lay Hoon Loh, Emma Greer, Xiaodong Zhang, Shivendra Pandey, Saramma Varghese, Wee Hong Goh, Jianjun Cheng, Eric Hao Guan, Angelo Pinto
{"title":"Boundless Engineering for Yield to Cope With the Complexity of High-Volume Manufacturing","authors":"Giyoung Yang, Lay Hoon Loh, Emma Greer, Xiaodong Zhang, Shivendra Pandey, Saramma Varghese, Wee Hong Goh, Jianjun Cheng, Eric Hao Guan, Angelo Pinto","doi":"10.1109/tsm.2024.3428936","DOIUrl":"https://doi.org/10.1109/tsm.2024.3428936","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"157 1","pages":""},"PeriodicalIF":2.7,"publicationDate":"2024-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141718531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-12DOI: 10.1109/TSM.2024.3427409
Yutong Xie;Benyamin Davaji;Ivan Chakarov;Sandy Wen;Michael Hargrove;David Fried;Peter C. Doerschuk;Amit Lal
Digital twins of the semiconductor fabrication process provide means for optimization of the physical layout and nanofabrication process design, studying compatibility between desired structures and a process flow, and a pathway to analyze the root causes of defects for state-of-the-art CMOS and MEMS devices. In this paper, a metric for the geometric differences between structures visualized by CD-SEM images is defined, and a computer-vision-based algorithm is developed to evaluate the metric. One of the major uses of such metrics is to compare experimental and simulated images. For this application, numerical results are presented when the simulator is SEMulator3D®, a physics-based process modeling software system for semiconductor and MEMS devices. Computer vision tools, such as filters, thresholding, and morphology operations, are used to extract geometric features from CD-SEM images and pattern matching and symmetric difference are used to compute the metric. Examples of using the metrics to quantify the geometric similarity between a simulated nanostructure and an experimental CD-SEM image of the fabricated nanostructure are presented. The data consists of eight classes of nanostructures which are defined, fabricated in the cleanroom with 36 combinations of layout parameters, and imaged with a CD-SEM.
{"title":"Quantitative Comparison of Simulation and Experiment Enabling a Lithography Digital Twin","authors":"Yutong Xie;Benyamin Davaji;Ivan Chakarov;Sandy Wen;Michael Hargrove;David Fried;Peter C. Doerschuk;Amit Lal","doi":"10.1109/TSM.2024.3427409","DOIUrl":"10.1109/TSM.2024.3427409","url":null,"abstract":"Digital twins of the semiconductor fabrication process provide means for optimization of the physical layout and nanofabrication process design, studying compatibility between desired structures and a process flow, and a pathway to analyze the root causes of defects for state-of-the-art CMOS and MEMS devices. In this paper, a metric for the geometric differences between structures visualized by CD-SEM images is defined, and a computer-vision-based algorithm is developed to evaluate the metric. One of the major uses of such metrics is to compare experimental and simulated images. For this application, numerical results are presented when the simulator is SEMulator3D®, a physics-based process modeling software system for semiconductor and MEMS devices. Computer vision tools, such as filters, thresholding, and morphology operations, are used to extract geometric features from CD-SEM images and pattern matching and symmetric difference are used to compute the metric. Examples of using the metrics to quantify the geometric similarity between a simulated nanostructure and an experimental CD-SEM image of the fabricated nanostructure are presented. The data consists of eight classes of nanostructures which are defined, fabricated in the cleanroom with 36 combinations of layout parameters, and imaged with a CD-SEM.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"546-552"},"PeriodicalIF":2.3,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141614074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-04DOI: 10.1109/TSM.2024.3421926
Wheyming Tina Song;Yu-Fan Liao
The occurrence of the “structural-loss” defect during single-crystal silicon growth (SCSG) is a significant issue in semiconductor manufacturing. When structural-loss occurs, it signifies a deviation from the desired quality of single-crystal formation, leading to the need to halt the growth process. Currently, there is a lack of scholarly literature addressing the determination of an optimal stopping time to promptly halt the process upon the occurrence of the defect on-line. Our research makes a substantial contribution by addressing this gap in the SCSG process, specifically focusing on orientations <100> and <111>. The study utilizes advanced AI with YOLO-v7 and innovative approaches. These include precise annotation of crystal misorientation features through a comprehensive definition of structural-loss and novel labeling techniques, identification of optimal hyper-parameters through a robust design, and the implementation of effective stopping rule mechanisms. Significant progress has been achieved in decision-making through the implementation of the stoping time shift to terminate the SCSG process within an average of less than 3 minutes for <100> orientations (with a standard error of 0.3 minutes) and less than 5 minutes for <111> orientations (with a standard error of 0.5 minutes). The promising results indicate that the proposed approaches have the capability to substitute manual inspections, opening up possibilities for new perspectives in this particular field.
{"title":"A Real-Time Automatic Structural-Loss Detection and Stopping Rule of Semiconductor Single-Crystal-Silicon-Growth <100> and <111>","authors":"Wheyming Tina Song;Yu-Fan Liao","doi":"10.1109/TSM.2024.3421926","DOIUrl":"10.1109/TSM.2024.3421926","url":null,"abstract":"The occurrence of the “structural-loss” defect during single-crystal silicon growth (SCSG) is a significant issue in semiconductor manufacturing. When structural-loss occurs, it signifies a deviation from the desired quality of single-crystal formation, leading to the need to halt the growth process. Currently, there is a lack of scholarly literature addressing the determination of an optimal stopping time to promptly halt the process upon the occurrence of the defect on-line. Our research makes a substantial contribution by addressing this gap in the SCSG process, specifically focusing on orientations <100> and <111>. The study utilizes advanced AI with YOLO-v7 and innovative approaches. These include precise annotation of crystal misorientation features through a comprehensive definition of structural-loss and novel labeling techniques, identification of optimal hyper-parameters through a robust design, and the implementation of effective stopping rule mechanisms. Significant progress has been achieved in decision-making through the implementation of the stoping time shift to terminate the SCSG process within an average of less than 3 minutes for <100> orientations (with a standard error of 0.3 minutes) and less than 5 minutes for <111> orientations (with a standard error of 0.5 minutes). The promising results indicate that the proposed approaches have the capability to substitute manual inspections, opening up possibilities for new perspectives in this particular field.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"304-315"},"PeriodicalIF":2.3,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141552962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods.
{"title":"Recognition and Classification of Mixed Defect Pattern Wafer Map Based on Multi-Path DCNN","authors":"Xingna Hou;Mulan Yi;Shouhong Chen;Meiqi Liu;Ziren Zhu","doi":"10.1109/TSM.2024.3418520","DOIUrl":"10.1109/TSM.2024.3418520","url":null,"abstract":"The semiconductor industry is the core industry of the information age. As a key link in the semiconductor industry, wafer fabrication plays a key role in its development. In the testing stage of the wafer, each die of the wafer is detected and marked, and a wafer map with a certain spatial pattern can be formed. The analysis and classification of these spatial patterns can identify the cause of wafer defects, thereby improving production yield. However, as wafer size increases, line widths become smaller, etc., the probability of a mixed defect mode wafer pattern increases. Moreover, the mixed defect mode wafer map is more difficult to identify and classify than the single defect mode wafer map. Therefore, this paper proposes an improved deep convolutional neural network (DCNN) structure model for the recognition and classification of mixed defect pattern wafer maps. From the perspective of increasing the width of the DCNN, the improved network structure can avoid problems such as over-fitting and limited extraction of features due to the continuous deepening of the DCNN. The network is called Multi-Path DCNN (MP-DCNN) structure. The experimental results show that the proposed Multi-Path DCNN structure has better performance and higher classification accuracy than existing methods.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"316-328"},"PeriodicalIF":2.3,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-25DOI: 10.1109/TSM.2024.3418827
Qian Yue;Chen Lan
Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy.
{"title":"DSH to Extend-DSH: Chip-Level Chemical Mechanical Planarization (CMP) Model Upgrade Based on Decoupling Regression Strategy","authors":"Qian Yue;Chen Lan","doi":"10.1109/TSM.2024.3418827","DOIUrl":"10.1109/TSM.2024.3418827","url":null,"abstract":"Chemical mechanical planarization (CMP) is vital for ensuring chip fabrication uniformity at nanometer scales. The emergence of a series of phenomenological CMP process models (Stine et al., 1997; Gbondo-Tugbawa, 2002; Xie, 2007; Vasilev, 2011) suggests that the existing model upgrade approach is largely based on a change in phenomenological model assumptions, demanding deep insights into complex process mechanisms and protracted period for accuracy improvements. To tackle this issue, this paper proposes a decoupling regression strategy for model upgrades. This strategy employs a data-driven approach to enhance the coupling relationships within the model, facilitating continuous improvement of simulation accuracy based on the existing model. It is capable of achieving improvements in model accuracy even in scenarios where modelers lack insight into complex process mechanisms. We validate our method by upgrading the Density Step Height (DSH) model to the Extend-DSH model to address poor erosion predictions at the 28nm node. Comparing model predictions with silicon data reveals that the Extend-DSH model aligns better with the measured data, reducing the root mean square error from 159.31Å to 6.89Å and increasing the coefficient of determination from -0.83561 to 0.6058, showcasing the effectiveness of the proposed chip-level CMP model upgrade method grounded in the decoupling regression strategy.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"329-339"},"PeriodicalIF":2.3,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM.
本文基于对光学发射光谱（OES）信号的所有时间和波长样本的分析，提出了等离子体蚀刻过程中虚拟计量（VM）的新方法。新方法将每个 OES 信号扁平化为单一向量，然后对训练数据集中扁平化 OES 信号向量形成的矩阵进行奇异值分解（SVD）。扁平化和标准化 OES 记录的低秩 SVD 投影可作为基于岭回归、人工神经网络和随机森林的 VM 模型的输入。随后，对从一家大型 300 毫米晶圆制造厂收集的数据集进行了虚拟机研究，结果表明，使用新提出的基于 SVD 的 OES 特征始终优于基准虚拟机模型特征。根据可分析的岭回归虚拟机模型形式对特征重要性进行的其他分析表明，OES 信号部分的独特时频模式对预测相关临界维度具有很高的参考价值，这清楚地证明了将整个 OES 信号用于虚拟机的必要性。
{"title":"Virtual Metrology of Critical Dimensions in Plasma Etch Processes Using Entire Optical Emission Spectrum","authors":"Roberto Dailey;Sam Bertelson;Jinki Kim;Dragan Djurdjanovic","doi":"10.1109/TSM.2024.3416844","DOIUrl":"10.1109/TSM.2024.3416844","url":null,"abstract":"This paper proposes a novel method for Virtual Metrology (VM) in plasma etch processes based on analysis of all time and wavelength samples of Optical Emission Spectroscopy (OES) signals. The new method flattens each OES signal into a single vector, after which Singular Value Decomposition (SVD) is performed on the matrix formed by vectors of flattened OES signals in the training dataset. Low rank SVD projections of flattened and standardized OES recordings served as inputs for Ridge Regression, Artificial Neural Network, and Random Forest based VM models. A VM study is then conducted on a dataset gathered from a major 300 mm wafer fabrication facility, showing that the use of newly proposed SVD-based OES features consistently outperformed benchmark VM model features. Additional analysis of feature importance performed based on the analytically tractable Ridge Regression VM model form demonstrated distinct time-frequency patterns of OES signal portions that were highly informative for prediction of relevant Critical Dimensions, clearly justifying the need to use the entire OES signals for VM.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"363-372"},"PeriodicalIF":2.3,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-19DOI: 10.1109/TSM.2024.3416830
Emily Gallagher;Lars-Åke Ragnarsson;Cedric Rolin
Sustainability and semiconductor manufacturing are linked in ways that may not be visible to experts in either area; this opacity is slowly fading with the surge of corporate commitments toward net-zero carbon emissions by 2050. In 2023, imec released a model (imec.netzero) to quantify the environmental impact of manufacturing integrated circuits (ICs). In this paper, the emissions trends are used to create an understanding of the processes that contribute. Lithography - both 193nm (DUV) and 13.5 nm (EUV) - has a large role to play in changing the overall emissions of IC chip manufacturing. Methods for reducing the emissions associated with lithography include design and process choices that maximize throughput and tool operational choices to reduce consumption. Low-emissions behaviors in manufacturing can be promoted once their potential benefit has been quantified. Engineers are well-accustomed to optimizing for performance; we must now optimize for lower emissions in parallel.
{"title":"Sustainable Semiconductor Manufacturing: The Role of Lithography","authors":"Emily Gallagher;Lars-Åke Ragnarsson;Cedric Rolin","doi":"10.1109/TSM.2024.3416830","DOIUrl":"10.1109/TSM.2024.3416830","url":null,"abstract":"Sustainability and semiconductor manufacturing are linked in ways that may not be visible to experts in either area; this opacity is slowly fading with the surge of corporate commitments toward net-zero carbon emissions by 2050. In 2023, imec released a model (imec.netzero) to quantify the environmental impact of manufacturing integrated circuits (ICs). In this paper, the emissions trends are used to create an understanding of the processes that contribute. Lithography - both 193nm (DUV) and 13.5 nm (EUV) - has a large role to play in changing the overall emissions of IC chip manufacturing. Methods for reducing the emissions associated with lithography include design and process choices that maximize throughput and tool operational choices to reduce consumption. Low-emissions behaviors in manufacturing can be promoted once their potential benefit has been quantified. Engineers are well-accustomed to optimizing for performance; we must now optimize for lower emissions in parallel.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"440-444"},"PeriodicalIF":2.3,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-18DOI: 10.1109/TSM.2024.3416055
Mohammad Mehedi Hasan;Naigong Yu;Imran Khan Mirani
Detecting wafer map anomalies is crucial for preventing yield loss in semiconductor fabrication, although intricate patterns and resource-intensive labeled data prerequisites hinder precise deep-learning segmentation. This paper presents an innovative, unsupervised method for detecting pixel-level anomalies in wafer maps. It utilizes an efficient dual attention module with a knowledge distillation network to learn defect distributions without anomalies. Knowledge transfer is achieved by distilling information from a pre-trained teacher into a student network with similar architecture, except an efficient dual attention module is incorporated atop the teacher network’s feature pyramid hierarchies, which enhances feature representation and segmentation across pyramid hierarchies that selectively emphasize relevant and discard irrelevant features by capturing contextual associations in positional and channel dimensions. Furthermore, it enables student networks to acquire an improved knowledge of hierarchical features to identify anomalies across different scales accurately. The dissimilarity in feature pyramids acts as a discriminatory function, predicting the likelihood of an abnormality, resulting in highly accurate pixel-level anomaly detection. Consequently, our proposed method excelled on the WM-811K and MixedWM38 datasets, achieving AUROC, AUPR, AUPRO, and F1-Scores of (99.65%, 99.35%), (97.31%, 92.13%), (90.76%, 84.66%) respectively, alongside an inference speed of 3.204 FPS, showcasing its high precision and efficiency.
检测晶圆图异常对于防止半导体制造中的良率损失至关重要，但复杂的模式和资源密集型标记数据前提条件阻碍了精确的深度学习分割。本文提出了一种创新的无监督方法，用于检测晶圆图中的像素级异常。它利用高效的双重关注模块和知识提炼网络来学习无异常的缺陷分布。除了在教师网络的特征金字塔层次结构上加入高效的双重注意模块外，知识转移是通过将预先训练好的教师网络中的信息提炼到具有类似结构的学生网络中来实现的，这种结构通过捕捉位置和通道维度中的上下文关联，增强了金字塔层次结构中的特征表示和分割，从而有选择性地强调相关特征，摒弃无关特征。此外，它还能使学生网络获得更好的分层特征知识，从而准确识别不同尺度的异常情况。特征金字塔中的不相似性可作为一种判别功能，预测异常的可能性，从而实现高精度的像素级异常检测。因此，我们提出的方法在 WM-811K 和 MixedWM38 数据集上表现出色，AUROC、AUPR、AUPRO 和 F1 分数分别为（99.65%、99.35%）、（97.31%、92.13%）、（90.76%、84.66%），推理速度为 3.204 FPS，显示了其高精度和高效率。
{"title":"Efficient Dual-Attention-Based Knowledge Distillation Network for Unsupervised Wafer Map Anomaly Detection","authors":"Mohammad Mehedi Hasan;Naigong Yu;Imran Khan Mirani","doi":"10.1109/TSM.2024.3416055","DOIUrl":"10.1109/TSM.2024.3416055","url":null,"abstract":"Detecting wafer map anomalies is crucial for preventing yield loss in semiconductor fabrication, although intricate patterns and resource-intensive labeled data prerequisites hinder precise deep-learning segmentation. This paper presents an innovative, unsupervised method for detecting pixel-level anomalies in wafer maps. It utilizes an efficient dual attention module with a knowledge distillation network to learn defect distributions without anomalies. Knowledge transfer is achieved by distilling information from a pre-trained teacher into a student network with similar architecture, except an efficient dual attention module is incorporated atop the teacher network’s feature pyramid hierarchies, which enhances feature representation and segmentation across pyramid hierarchies that selectively emphasize relevant and discard irrelevant features by capturing contextual associations in positional and channel dimensions. Furthermore, it enables student networks to acquire an improved knowledge of hierarchical features to identify anomalies across different scales accurately. The dissimilarity in feature pyramids acts as a discriminatory function, predicting the likelihood of an abnormality, resulting in highly accurate pixel-level anomaly detection. Consequently, our proposed method excelled on the WM-811K and MixedWM38 datasets, achieving AUROC, AUPR, AUPRO, and F1-Scores of (99.65%, 99.35%), (97.31%, 92.13%), (90.76%, 84.66%) respectively, alongside an inference speed of 3.204 FPS, showcasing its high precision and efficiency.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"293-303"},"PeriodicalIF":2.3,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
During semiconductor manufacturing, the high temperature sulfuric acid peroxide mixture (SPM) and airborne molecule contaminants (AMCs) can result in the formation of defects such as Silicon-carbide (Si-C) on the wafer surface. Furthermore, defects adversely affect device performance, yield, and manufacturing productivity. In this work, a novel approach is proposed by introducing an additional nitrogen (N2) gas purge nozzle inside the single wafer chamber to reduce total volatile organic compounds (t-VOC). Additionally, we provide insights into the mechanism underlying defect formation in SPM which has not been previously explained. In SPM process, defects are formed by AMCs and high temperature. So, various AMCs were investigated in this work. Moreover, the correlation of the number of Si-C defect with temperature and duration of chemical flow was also analyzed. The experimental results demonstrated that defects and t-VOC follow the same concentration trend. Our nitrogen purge method effectively diluted the chamber environment, reducing the adhesion energy between contamination particles and the wafer surface. A suitable N2 purging rate inside the single-wafer chamber facilitated the elimination of around 63% of defects from wafer surface. Hence, this approach can be crucial in minimizing the Si-C defects and improving the chamber environment for high-temperature SPM wet-cleaning process.
{"title":"Elimination of Si-C Defect on Wafer Surface in High-Temperature SPM Process Through Nitrogen Purge in 300-mm Single-Wafer Chamber","authors":"Rajan Kumar Singh;Alfie Lin;Haley Lin;Max Chen;Yvonne Pan;Nancy Cho;Willy Chen;Jamiet Tung;Walt Hu;Wilson Huang","doi":"10.1109/TSM.2024.3416079","DOIUrl":"10.1109/TSM.2024.3416079","url":null,"abstract":"During semiconductor manufacturing, the high temperature sulfuric acid peroxide mixture (SPM) and airborne molecule contaminants (AMCs) can result in the formation of defects such as Silicon-carbide (Si-C) on the wafer surface. Furthermore, defects adversely affect device performance, yield, and manufacturing productivity. In this work, a novel approach is proposed by introducing an additional nitrogen (N2) gas purge nozzle inside the single wafer chamber to reduce total volatile organic compounds (t-VOC). Additionally, we provide insights into the mechanism underlying defect formation in SPM which has not been previously explained. In SPM process, defects are formed by AMCs and high temperature. So, various AMCs were investigated in this work. Moreover, the correlation of the number of Si-C defect with temperature and duration of chemical flow was also analyzed. The experimental results demonstrated that defects and t-VOC follow the same concentration trend. Our nitrogen purge method effectively diluted the chamber environment, reducing the adhesion energy between contamination particles and the wafer surface. A suitable N2 purging rate inside the single-wafer chamber facilitated the elimination of around 63% of defects from wafer surface. Hence, this approach can be crucial in minimizing the Si-C defects and improving the chamber environment for high-temperature SPM wet-cleaning process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"355-362"},"PeriodicalIF":2.3,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141942150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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