Pub Date : 2025-01-14DOI: 10.1109/TSM.2025.3529683
Zilin Wang;Yunfan Shi;Qingchao Zhang;Yikang Zhou;Qian Wang;Zheyao Wang
Cu-Cu thermocompression bonding (TCB) is widely used in 3D integration due to its excellent electrical performance, high bonding strength, and good reliability. However, TCB needs high temperature, high pressure, and complicated chemical-mechanical-planarization (CMP). We have developed a low temperature, CMP-free Cu-Cu bonding method using porous Cu-Sn microbumps. In this paper, we further report the detailed fabrication processes and the formation principles of the porous Cu-Sn bumps, as well as the characterization results of the bonded structures. A pretreatment method is developed using sequential thermal reflow and redox treatment in a gas mixture of oxygen and formic acid to form porous Cu-Sn bumps. The gas content, temperature, and duration of the pretreatment are optimized. An array of $1000times 800$ porous Cu-Sn bumps has been fabricated, and CMP-free Cu-Cu bonding has been achieved using Cu-Sn bumps at 250°C, 10 MPa, and 30 min. The bonding strength, the resistance, and the thermal reliability are evaluated.
{"title":"Fabrication of Porous Cu–Sn Microbumps for Low-Temperature Cu–Cu Bonding","authors":"Zilin Wang;Yunfan Shi;Qingchao Zhang;Yikang Zhou;Qian Wang;Zheyao Wang","doi":"10.1109/TSM.2025.3529683","DOIUrl":"https://doi.org/10.1109/TSM.2025.3529683","url":null,"abstract":"Cu-Cu thermocompression bonding (TCB) is widely used in 3D integration due to its excellent electrical performance, high bonding strength, and good reliability. However, TCB needs high temperature, high pressure, and complicated chemical-mechanical-planarization (CMP). We have developed a low temperature, CMP-free Cu-Cu bonding method using porous Cu-Sn microbumps. In this paper, we further report the detailed fabrication processes and the formation principles of the porous Cu-Sn bumps, as well as the characterization results of the bonded structures. A pretreatment method is developed using sequential thermal reflow and redox treatment in a gas mixture of oxygen and formic acid to form porous Cu-Sn bumps. The gas content, temperature, and duration of the pretreatment are optimized. An array of <inline-formula> <tex-math>$1000times 800$ </tex-math></inline-formula> porous Cu-Sn bumps has been fabricated, and CMP-free Cu-Cu bonding has been achieved using Cu-Sn bumps at 250°C, 10 MPa, and 30 min. The bonding strength, the resistance, and the thermal reliability are evaluated.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"343-351"},"PeriodicalIF":2.3,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-09DOI: 10.1109/TSM.2025.3527514
Seohyun Kim;Shilong Zhang;Youngsoo Shin
In curvilinear optical proximity correction (OPC), each segment is modeled by a cubic Bézier curve, defined by two endpoints and two intermediate points. Iterative correction of these points is not trivial, and a simple heuristic (Chen et al., 2024) has been used but is not effective. A vertex placement error (VPE) is first introduced to replace edge placement error (EPE) in standard Manhattan OPC. Two machine learning models are applied for accurate curve correction. (1) An MLP is used to locate the new endpoints, while VPE from the previous iteration and a few PFT signals representing local light intensity are provided as inputs. (2) A VPE predictor, constructed with GCNs, is designed to output average (or maximum) VPE over a given layout clip. Once trained, it is used to identify intermediate points after new endpoints are fixed by MLP; this is done through gradient descent optimization such that VPE is minimized and curvature constraints are respected as much as possible. Experimental results demonstrate that the proposed curvilinear OPC reduces OPC iterations from 8 to 5 when average VPE is considered as a target or from 14 to 5 when maximum VPE is a target, with a final VPE reduction of about 5 to 6%.
在曲线光学接近校正（OPC）中，每一段由两个端点和两个中间点定义的三次bsamizier曲线建模。这些点的迭代校正不是微不足道的，并且已经使用了简单的启发式（Chen et al., 2024），但并不有效。首次引入顶点放置误差（VPE）来代替标准曼哈顿OPC中的边缘放置误差（EPE）。采用两种机器学习模型进行精确的曲线校正。(1)使用MLP定位新端点，同时提供前一次迭代的VPE和一些表示局部光强的PFT信号作为输入。(2)使用GCNs构建的VPE预测器设计用于在给定布局剪辑上输出平均（或最大）VPE。训练完成后，用于MLP固定新端点后的中间点识别；这是通过梯度下降优化来实现的，这样VPE最小化，曲率约束尽可能得到尊重。实验结果表明，当以平均VPE为目标时，所提出的曲线OPC将OPC迭代从8次减少到5次，当以最大VPE为目标时，将OPC迭代从14次减少到5次，最终的VPE减少约5% ~ 6%。
{"title":"ML-Guided Curvilinear OPC: Fast, Accurate, and Manufacturable Curve Correction","authors":"Seohyun Kim;Shilong Zhang;Youngsoo Shin","doi":"10.1109/TSM.2025.3527514","DOIUrl":"https://doi.org/10.1109/TSM.2025.3527514","url":null,"abstract":"In curvilinear optical proximity correction (OPC), each segment is modeled by a cubic Bézier curve, defined by two endpoints and two intermediate points. Iterative correction of these points is not trivial, and a simple heuristic (Chen et al., 2024) has been used but is not effective. A vertex placement error (VPE) is first introduced to replace edge placement error (EPE) in standard Manhattan OPC. Two machine learning models are applied for accurate curve correction. (1) An MLP is used to locate the new endpoints, while VPE from the previous iteration and a few PFT signals representing local light intensity are provided as inputs. (2) A VPE predictor, constructed with GCNs, is designed to output average (or maximum) VPE over a given layout clip. Once trained, it is used to identify intermediate points after new endpoints are fixed by MLP; this is done through gradient descent optimization such that VPE is minimized and curvature constraints are respected as much as possible. Experimental results demonstrate that the proposed curvilinear OPC reduces OPC iterations from 8 to 5 when average VPE is considered as a target or from 14 to 5 when maximum VPE is a target, with a final VPE reduction of about 5 to 6%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"19-28"},"PeriodicalIF":2.3,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TSM.2025.3527310
Cameron A. Lippert;James R. Landon;Jason Keleher;Alan Rassoolkhani
In this paper, we investigate the potential of a High Efficiency Selective Electrochemical Cell (HESEC) to recover copper from a variety of semiconductor wastewater streams while also achieving EPA discharge compliance. The copper chemical-mechanical planarization (CuCMP), wet etch, and electroplating processes produce significant levels of copper laden wastewaters with complex matrices that make recovery of the copper difficult. Based on our experimental results, the HESEC provides insight into how novel electrochemical cell designs can be used to achieve selective copper removal and recovery from different wastewater streams and open new possibilities for economical point source treatment and implementation of sustainable practices.
{"title":"Integrated Electrochemical Technology for Efficient Metal Recovery in Semiconductor Wastewater","authors":"Cameron A. Lippert;James R. Landon;Jason Keleher;Alan Rassoolkhani","doi":"10.1109/TSM.2025.3527310","DOIUrl":"https://doi.org/10.1109/TSM.2025.3527310","url":null,"abstract":"In this paper, we investigate the potential of a High Efficiency Selective Electrochemical Cell (HESEC) to recover copper from a variety of semiconductor wastewater streams while also achieving EPA discharge compliance. The copper chemical-mechanical planarization (CuCMP), wet etch, and electroplating processes produce significant levels of copper laden wastewaters with complex matrices that make recovery of the copper difficult. Based on our experimental results, the HESEC provides insight into how novel electrochemical cell designs can be used to achieve selective copper removal and recovery from different wastewater streams and open new possibilities for economical point source treatment and implementation of sustainable practices.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"413-419"},"PeriodicalIF":2.3,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-23DOI: 10.1109/TSM.2024.3521368
Chun-Hung Liu;Ze-An Ding
Curvilinear (CL) mask patterns, essential for extreme ultraviolet lithography in advanced semiconductor manufacturing, suffer from degraded fidelity and contrast due to complex pattern environments and severe proximity effects, necessitating CL mask process correction (CL-MPC). However, conventional shape-based CL-MPC methods cannot enhance image contrast because of their inability to adjust dose levels, while dose-based methods require extensive computational time and are incompatible with electron beam writers lacking dose adjustment capabilities. Therefore, this study proposes a two-layer geometry-based CL-MPC method integrating pattern fidelity and image contrast co-optimization with pattern manufacturability enhancement. It employs two overlapping patterns, each of which adjusts the geometry without modifying the dose. A skeleton-based approach creates CL pattern fragments, and dual proportional-integral–derivative controllers improve the pattern fidelity more effectively by classifying the energy slope of target points. For image contrast improvement, a feedback mechanism replaces unsatisfactory parameters with optimized values by minimizing the reciprocal of the energy slope of target points. The pattern manufacturability enhancement further improves mask fabrication by smoothing edge corners and optimizing pattern angles. The proposed method significantly improves pattern fidelity, image contrast, correction runtime efficiency, and manufacturability, making corrected patterns compatible with all electron-beam writers and presenting a promising solution for CL-MPC limitations.
{"title":"Geometry-Based Curvilinear Mask Process Correction for Enhanced Pattern Fidelity, Contrast, and Manufacturability","authors":"Chun-Hung Liu;Ze-An Ding","doi":"10.1109/TSM.2024.3521368","DOIUrl":"https://doi.org/10.1109/TSM.2024.3521368","url":null,"abstract":"Curvilinear (CL) mask patterns, essential for extreme ultraviolet lithography in advanced semiconductor manufacturing, suffer from degraded fidelity and contrast due to complex pattern environments and severe proximity effects, necessitating CL mask process correction (CL-MPC). However, conventional shape-based CL-MPC methods cannot enhance image contrast because of their inability to adjust dose levels, while dose-based methods require extensive computational time and are incompatible with electron beam writers lacking dose adjustment capabilities. Therefore, this study proposes a two-layer geometry-based CL-MPC method integrating pattern fidelity and image contrast co-optimization with pattern manufacturability enhancement. It employs two overlapping patterns, each of which adjusts the geometry without modifying the dose. A skeleton-based approach creates CL pattern fragments, and dual proportional-integral–derivative controllers improve the pattern fidelity more effectively by classifying the energy slope of target points. For image contrast improvement, a feedback mechanism replaces unsatisfactory parameters with optimized values by minimizing the reciprocal of the energy slope of target points. The pattern manufacturability enhancement further improves mask fabrication by smoothing edge corners and optimizing pattern angles. The proposed method significantly improves pattern fidelity, image contrast, correction runtime efficiency, and manufacturability, making corrected patterns compatible with all electron-beam writers and presenting a promising solution for CL-MPC limitations.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"36-47"},"PeriodicalIF":2.3,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The formation of cone defects is a side effect of the shallow trench isolation (STI) etching process, caused by the redeposition of residue from silicon nitride, silicon dioxide, or byproducts from the etching process. This study aims to explain the mechanism responsible for these defects during STI etching. The utilization of this model can enhance the design for manufacturability by streamlining the manufacturing process, reducing susceptibility to defects and process variations, and ultimately improving the reliability and manufacturability of production.
{"title":"The Mechanism of an Etching-Back to Reduce the Density of Cone Defect in STI During the Manufacturing","authors":"Chih-Cherng Liao;Jian-Hsing Lee;Yu-Jui Chang;Kai-Chuan Kan;Ching-Kuei Shih;Ya-Huei Kuo;Pei-Chen Tsai;Chien-Hsien Song;Ke-Horng Chen","doi":"10.1109/TSM.2024.3519780","DOIUrl":"https://doi.org/10.1109/TSM.2024.3519780","url":null,"abstract":"The formation of cone defects is a side effect of the shallow trench isolation (STI) etching process, caused by the redeposition of residue from silicon nitride, silicon dioxide, or byproducts from the etching process. This study aims to explain the mechanism responsible for these defects during STI etching. The utilization of this model can enhance the design for manufacturability by streamlining the manufacturing process, reducing susceptibility to defects and process variations, and ultimately improving the reliability and manufacturability of production.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"134-138"},"PeriodicalIF":2.3,"publicationDate":"2024-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/TSM.2024.3511918
Yaoting Wang;Yongyu Wu;Dawei Gao;Kai Xu
Line Width Roughness (LWR) has emerged as a pivotal challenge that the semiconductor manufacturing industry must confront. This study provides experimental data to elucidate the mechanism by which LWR affects device performance in different processing layers. First, Hard Mask (HM) technology was used to reduce LWR of Active Area (AA) and polysilicon gate by 0.97 nm and 0.62 nm, respectively, resulting in a 21.79% and 55.82% decrease in threshold voltage variability. With the application of HM technology in AA layer processing, the device performance of NMOS and PMOS was also improved by 19.58% and 12.54%, respectively. This improvement can be attributed to the mitigation of carrier scattering induced by LWR. Moreover, HM technology was also conducted in polysilicon gate process which can reduce LWR effectively, thereby enhancing device stability, decreasing the drain-induced barrier lowering factor by approximately 10%, and suppressing gate-induced drain leakage current and overlap capacitance. Consequently, this process contributes to the alleviation of short channel effects. Our research provides experimental groundwork for diminishing LWR, supplies guidelines for understanding the distinct mechanisms of LWR, and offers effective route toward enhancing device performance, and controlling fluctuations.
{"title":"Comprehensive Study of the Impact of LWR on Device Performance in VLSI Technology","authors":"Yaoting Wang;Yongyu Wu;Dawei Gao;Kai Xu","doi":"10.1109/TSM.2024.3511918","DOIUrl":"https://doi.org/10.1109/TSM.2024.3511918","url":null,"abstract":"Line Width Roughness (LWR) has emerged as a pivotal challenge that the semiconductor manufacturing industry must confront. This study provides experimental data to elucidate the mechanism by which LWR affects device performance in different processing layers. First, Hard Mask (HM) technology was used to reduce LWR of Active Area (AA) and polysilicon gate by 0.97 nm and 0.62 nm, respectively, resulting in a 21.79% and 55.82% decrease in threshold voltage variability. With the application of HM technology in AA layer processing, the device performance of NMOS and PMOS was also improved by 19.58% and 12.54%, respectively. This improvement can be attributed to the mitigation of carrier scattering induced by LWR. Moreover, HM technology was also conducted in polysilicon gate process which can reduce LWR effectively, thereby enhancing device stability, decreasing the drain-induced barrier lowering factor by approximately 10%, and suppressing gate-induced drain leakage current and overlap capacitance. Consequently, this process contributes to the alleviation of short channel effects. Our research provides experimental groundwork for diminishing LWR, supplies guidelines for understanding the distinct mechanisms of LWR, and offers effective route toward enhancing device performance, and controlling fluctuations.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"12-18"},"PeriodicalIF":2.3,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-02DOI: 10.1109/TSM.2024.3510358
Haiyong Chen;Yaxiu Zhang;Yan Zhang;Xingwei Yan;Xin Zhang;Kunlin Zou
Efficient and intelligent surface defect detection of photovoltaic modules is crucial for improving the quality of photovoltaic modules and ensuring the reliable operation of large-scale infrastructure. However, the scenario characteristics of data distribution deviation make the construction of defect detection models for open world scenarios such as photovoltaic manufacturing and power plant inspections a challenge. Therefore, we propose the Gather and Distribute Domain shift Suppression Network. It adopts a single domain generalized method that is completely independent of the test samples to address the problem of distribution shift. Using a one-stage network as the baseline network breaks through the limitations of traditional domain generalization methods that typically use two-stage networks. It not only balances detection accuracy and speed but also simplifies the model deployment and application process. The network first employs the DeepSpine module to capture a wider range of contextual information. By concatenating and aligning multi-scale channel features, it effectively suppresses background style shifts. Building upon this, the Gather and Distribute Module performs cross layer interactive learning on multi-scale channel features. The multi-level features and semantic dependencies learned enhance the localization and recognition ability of target defects, thereby achieving the suppression of defect instance shift. Furthermore, we utilizes normalized Wasserstein distance for similarity measurement, reducing measurement errors caused by bounding box position deviations. We conducted a comprehensive evaluation of our network on the Electroluminescence Endogenous Shift Dataset and Photovoltaic Inspection Infrared Dataset. In scenarios with three production lines and four heights on two datasets, the detection accuracy of GDDS reached 91.2%, 82.3%, 79.9%, and 92.8%, 82.7%, 77.2%, and 69.2%, respectively. The experimental results showed that our method can adapt to defect detection in open world scenarios faster and better than other state-of-the-art methods.
{"title":"Defect Detection of Photovoltaic Panels to Suppress Endogenous Shift Phenomenon","authors":"Haiyong Chen;Yaxiu Zhang;Yan Zhang;Xingwei Yan;Xin Zhang;Kunlin Zou","doi":"10.1109/TSM.2024.3510358","DOIUrl":"https://doi.org/10.1109/TSM.2024.3510358","url":null,"abstract":"Efficient and intelligent surface defect detection of photovoltaic modules is crucial for improving the quality of photovoltaic modules and ensuring the reliable operation of large-scale infrastructure. However, the scenario characteristics of data distribution deviation make the construction of defect detection models for open world scenarios such as photovoltaic manufacturing and power plant inspections a challenge. Therefore, we propose the Gather and Distribute Domain shift Suppression Network. It adopts a single domain generalized method that is completely independent of the test samples to address the problem of distribution shift. Using a one-stage network as the baseline network breaks through the limitations of traditional domain generalization methods that typically use two-stage networks. It not only balances detection accuracy and speed but also simplifies the model deployment and application process. The network first employs the DeepSpine module to capture a wider range of contextual information. By concatenating and aligning multi-scale channel features, it effectively suppresses background style shifts. Building upon this, the Gather and Distribute Module performs cross layer interactive learning on multi-scale channel features. The multi-level features and semantic dependencies learned enhance the localization and recognition ability of target defects, thereby achieving the suppression of defect instance shift. Furthermore, we utilizes normalized Wasserstein distance for similarity measurement, reducing measurement errors caused by bounding box position deviations. We conducted a comprehensive evaluation of our network on the Electroluminescence Endogenous Shift Dataset and Photovoltaic Inspection Infrared Dataset. In scenarios with three production lines and four heights on two datasets, the detection accuracy of GDDS reached 91.2%, 82.3%, 79.9%, and 92.8%, 82.7%, 77.2%, and 69.2%, respectively. The experimental results showed that our method can adapt to defect detection in open world scenarios faster and better than other state-of-the-art methods.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"83-95"},"PeriodicalIF":2.3,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-02DOI: 10.1109/TSM.2024.3510232
Tomasz Brozek;Stephen Lam;Christopher Hess;Larg Weiland;Matthew Moe;Xumin Shen;John Chen;Indranil De;Marcin Strojwas;Andrzej Strojwas;John K. Kibarian
Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction, and they are difficult to detect by surface optical scans. In case of a functional failure related to a defect (an open or a short), the localization of the fail site for failure analysis and root cause identification is often difficult, especially for random logic design. In this paper we describe a new -DFM methodology which inserts into the product design special test structures to support New Product Introduction (NPI) and a product yield ramp. The structures are part of PDF Solutions’ proprietary Design-for-Inspection (DFI) system with no penalty to the product layout. They are designed to be electrically tested in a non-contact way using a dedicated and specially optimized e-Beam tool. The layouts of these structures are based on the standard cell design therefore they can be used as filler cells in standard cell-based logic designs. The paper presents the concept of the test structures and their design to cover specific failure modes and enable fail mechanism identification. We describe the design flow to integrate the structures into the product floorplan and the non-contact test methodology to scan product wafers and detect failures. Finally, we demonstrate usage of such DFI structures and provide results collected from scanning product wafers containing embedded DFI filler cells.
{"title":"Product Design Enhancement With Test Structures for Non-Contact Detection of Yield Detractors","authors":"Tomasz Brozek;Stephen Lam;Christopher Hess;Larg Weiland;Matthew Moe;Xumin Shen;John Chen;Indranil De;Marcin Strojwas;Andrzej Strojwas;John K. Kibarian","doi":"10.1109/TSM.2024.3510232","DOIUrl":"https://doi.org/10.1109/TSM.2024.3510232","url":null,"abstract":"Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction, and they are difficult to detect by surface optical scans. In case of a functional failure related to a defect (an open or a short), the localization of the fail site for failure analysis and root cause identification is often difficult, especially for random logic design. In this paper we describe a new -DFM methodology which inserts into the product design special test structures to support New Product Introduction (NPI) and a product yield ramp. The structures are part of PDF Solutions’ proprietary Design-for-Inspection (DFI) system with no penalty to the product layout. They are designed to be electrically tested in a non-contact way using a dedicated and specially optimized e-Beam tool. The layouts of these structures are based on the standard cell design therefore they can be used as filler cells in standard cell-based logic designs. The paper presents the concept of the test structures and their design to cover specific failure modes and enable fail mechanism identification. We describe the design flow to integrate the structures into the product floorplan and the non-contact test methodology to scan product wafers and detect failures. Finally, we demonstrate usage of such DFI structures and provide results collected from scanning product wafers containing embedded DFI filler cells.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"126-133"},"PeriodicalIF":2.3,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-02DOI: 10.1109/TSM.2024.3510376
Hsiu-Hui Hsiao;Kung-Jeng Wang
The semiconductor industry thrives on rapid technological advancements, crucial for superior product performance and cost efficiency. Chip design houses and consumer electronics companies must continuously pursue New Tape Out (NTO) to maintain technological leadership. Timely NTO completion expedites product launches, crucial in the competitive semiconductor market. This paper addresses Chemical Mechanical Polishing (CMP) hotspot, critical in NTO quality and cycle time, affecting wafer surface topology. Hotspot defects can degrade wafer performance, demanding swift detection and resolution. Traditional methods can only identify CMP hotspot after manufacturing, necessitating repeated adjustments to IC design. We propose HotspotFusion, leveraging pattern density data from Graphic Design System (GDS) to predict CMP hotspot early in the design phase. Utilizing a generative AI model, HotspotFusion significantly reduces NTO cycle time by enabling proactive hotspot detection and process optimization, fostering efficiency and competitiveness in semiconductor manufacturing.
{"title":"HotspotFusion: A Generative AI Approach to Predicting CMP Hotspot in Semiconductor Manufacturing","authors":"Hsiu-Hui Hsiao;Kung-Jeng Wang","doi":"10.1109/TSM.2024.3510376","DOIUrl":"https://doi.org/10.1109/TSM.2024.3510376","url":null,"abstract":"The semiconductor industry thrives on rapid technological advancements, crucial for superior product performance and cost efficiency. Chip design houses and consumer electronics companies must continuously pursue New Tape Out (NTO) to maintain technological leadership. Timely NTO completion expedites product launches, crucial in the competitive semiconductor market. This paper addresses Chemical Mechanical Polishing (CMP) hotspot, critical in NTO quality and cycle time, affecting wafer surface topology. Hotspot defects can degrade wafer performance, demanding swift detection and resolution. Traditional methods can only identify CMP hotspot after manufacturing, necessitating repeated adjustments to IC design. We propose HotspotFusion, leveraging pattern density data from Graphic Design System (GDS) to predict CMP hotspot early in the design phase. Utilizing a generative AI model, HotspotFusion significantly reduces NTO cycle time by enabling proactive hotspot detection and process optimization, fostering efficiency and competitiveness in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"73-82"},"PeriodicalIF":2.3,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-26DOI: 10.1109/TSM.2024.3506312
{"title":"2024 Index IEEE Transactions on Semiconductor Manufacturing Vol. 37","authors":"","doi":"10.1109/TSM.2024.3506312","DOIUrl":"https://doi.org/10.1109/TSM.2024.3506312","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"649-667"},"PeriodicalIF":2.3,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10768858","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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