Pub Date : 2024-03-04DOI: 10.1109/TSM.2024.3372521
Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui
In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.
{"title":"Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask","authors":"Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui","doi":"10.1109/TSM.2024.3372521","DOIUrl":"10.1109/TSM.2024.3372521","url":null,"abstract":"In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"160-165"},"PeriodicalIF":2.7,"publicationDate":"2024-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140037422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-03DOI: 10.1109/TSM.2024.3396423
Yongwon Jo;Jinsoo Bae;Hansam Cho;Heejoong Roh;Kyunghye Kim;Munki Jo;Jaeung Tae;Seoung Bum Kim
Semantic segmentation for automated measurement in semiconductor manufacturing, specifically with wafer transmission electron microscopy (TEM) images, poses significant challenges because of the difficulty of acquisition, prevalent noise, and ambiguous object boundaries. However, prior studies focused on broadening the application of semantic segmentation for automated measurement without considering the specific intricacies of TEM images. In this study, we propose a wafer TEM images-specific semantic segmentation and transfer learning (WTEM-SST) framework to address these issues. The proposed WTEM-SST involves a pre-training stage, wafer TEM-specific data augmentation methods, and a boundary-focused loss function. The pre-training stage addresses the difficulty of collecting and annotating wafer TEM images, followed by fine-tuning for process-specific segmentation models. Our data augmentation techniques mitigate challenges related to limited training samples, lots of noise, and unclear boundaries. The boundary-focused loss makes the model more precise in boundary recognition during fine-tuning. We demonstrate that WTEM-SST outperforms conventional segmentation models, with our studies highlighting the effectiveness of the three components in WTEM-SST.
在半导体制造领域，特别是晶圆透射电子显微镜（TEM）图像的自动测量中，语义分割是一项重大挑战，因为采集困难、噪声普遍存在、物体边界模糊不清。然而，之前的研究侧重于扩大语义分割在自动测量中的应用，却没有考虑到 TEM 图像的特殊复杂性。在本研究中，我们提出了晶圆 TEM 图像特定语义分割和迁移学习（WTEM-SST）框架来解决这些问题。拟议的 WTEM-SST 包括预训练阶段、晶圆 TEM 特定数据增强方法和以边界为重点的损失函数。预训练阶段解决了收集和注释晶圆 TEM 图像的困难，随后对特定于流程的分割模型进行微调。我们的数据增强技术可以缓解训练样本有限、噪音大和边界不清晰等难题。在微调过程中，以边界为重点的损失使模型的边界识别更加精确。我们的研究表明，WTEM-SST 优于传统的分割模型，并突出了 WTEM-SST 中三个组件的有效性。
{"title":"Semantic Segmentation for Noisy and Limited Wafer Transmission Electron Microscope Images","authors":"Yongwon Jo;Jinsoo Bae;Hansam Cho;Heejoong Roh;Kyunghye Kim;Munki Jo;Jaeung Tae;Seoung Bum Kim","doi":"10.1109/TSM.2024.3396423","DOIUrl":"10.1109/TSM.2024.3396423","url":null,"abstract":"Semantic segmentation for automated measurement in semiconductor manufacturing, specifically with wafer transmission electron microscopy (TEM) images, poses significant challenges because of the difficulty of acquisition, prevalent noise, and ambiguous object boundaries. However, prior studies focused on broadening the application of semantic segmentation for automated measurement without considering the specific intricacies of TEM images. In this study, we propose a wafer TEM images-specific semantic segmentation and transfer learning (WTEM-SST) framework to address these issues. The proposed WTEM-SST involves a pre-training stage, wafer TEM-specific data augmentation methods, and a boundary-focused loss function. The pre-training stage addresses the difficulty of collecting and annotating wafer TEM images, followed by fine-tuning for process-specific segmentation models. Our data augmentation techniques mitigate challenges related to limited training samples, lots of noise, and unclear boundaries. The boundary-focused loss makes the model more precise in boundary recognition during fine-tuning. We demonstrate that WTEM-SST outperforms conventional segmentation models, with our studies highlighting the effectiveness of the three components in WTEM-SST.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 3","pages":"345-354"},"PeriodicalIF":2.3,"publicationDate":"2024-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140831626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-26DOI: 10.1109/TSM.2024.3370175
Ruian Ji;Rong Chen;Lan Chen
Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process.
{"title":"A Lightweight Chip-Scale Chemical Mechanical Polishing Model Based on Polynomial Network","authors":"Ruian Ji;Rong Chen;Lan Chen","doi":"10.1109/TSM.2024.3370175","DOIUrl":"10.1109/TSM.2024.3370175","url":null,"abstract":"Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"139-145"},"PeriodicalIF":2.7,"publicationDate":"2024-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139977641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-14DOI: 10.1109/TSM.2024.3365827
Surin An;Jeong Eun Choi;Ju Eun Kang;Jiseok Lee;Sang Jeen Hong
Semiconductor industry is experiencing a rising demand for environmentally friendly processes with the emphasis on green policies and worldwide environmental sustainability. Nitrogen trifluoride (NF3), the most common plasma chamber cleaning agent gas, poses a significant concern as a potent greenhouse gas since it has global warming potential (GWP), 740 times and 6 times higher than that CO2 and N2O. This study investigated the exhaust gas using quadrupole mass spectroscopy (QMS) and analyzed the change in cleaning speed and the type of exhaust gas through plasma monitoring using optical mass spectroscopy (OES). The objective is to lower the use of the amount of NF3 gas in chamber cleaning process to partially contribute the environmental sustainability in the point of semiconductor manufacturing. When a small amount of N2 was added to NF3 whose ratio of 7:23, the cleaning efficiency reached to 90% compared to NF3 gas alone. Addition of N2 positively affected electron density and temperature to increase the F-radical in remote plasma system. In conclusion, 18% of NF3 usage amount was reduced during the Sio2 deposition chamber cleaning process.
{"title":"Eco-Friendly Dry-Cleaning and Diagnostics of Silicon Dioxide Deposition Chamber","authors":"Surin An;Jeong Eun Choi;Ju Eun Kang;Jiseok Lee;Sang Jeen Hong","doi":"10.1109/TSM.2024.3365827","DOIUrl":"10.1109/TSM.2024.3365827","url":null,"abstract":"Semiconductor industry is experiencing a rising demand for environmentally friendly processes with the emphasis on green policies and worldwide environmental sustainability. Nitrogen trifluoride (NF3), the most common plasma chamber cleaning agent gas, poses a significant concern as a potent greenhouse gas since it has global warming potential (GWP), 740 times and 6 times higher than that CO2 and N2O. This study investigated the exhaust gas using quadrupole mass spectroscopy (QMS) and analyzed the change in cleaning speed and the type of exhaust gas through plasma monitoring using optical mass spectroscopy (OES). The objective is to lower the use of the amount of NF3 gas in chamber cleaning process to partially contribute the environmental sustainability in the point of semiconductor manufacturing. When a small amount of N2 was added to NF3 whose ratio of 7:23, the cleaning efficiency reached to 90% compared to NF3 gas alone. Addition of N2 positively affected electron density and temperature to increase the F-radical in remote plasma system. In conclusion, 18% of NF3 usage amount was reduced during the Sio2 deposition chamber cleaning process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"207-221"},"PeriodicalIF":2.7,"publicationDate":"2024-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139954668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs.
{"title":"Curvilinear Standard Cell Design for Semiconductor Manufacturing","authors":"Ryoung-Han Kim;Soobin Hwang;Apoorva Oak;Yasser Shirazi;Hsinlan Chang;Kiho Yang;Gioele Mirabelli","doi":"10.1109/TSM.2024.3362900","DOIUrl":"10.1109/TSM.2024.3362900","url":null,"abstract":"Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 2","pages":"152-159"},"PeriodicalIF":2.7,"publicationDate":"2024-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139945816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-05DOI: 10.1109/TSM.2023.3334414
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2023.3334414","DOIUrl":"https://doi.org/10.1109/TSM.2023.3334414","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 1","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10419383","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139694970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-05DOI: 10.1109/TSM.2024.3359520
{"title":"Call for Papers for IEEE Transactions on Materials for Electron Devices","authors":"","doi":"10.1109/TSM.2024.3359520","DOIUrl":"https://doi.org/10.1109/TSM.2024.3359520","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 1","pages":"138-138"},"PeriodicalIF":2.7,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10419869","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139695013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-05DOI: 10.1109/TSM.2024.3356972
{"title":"Joint Call for Papers for IEEE Transactions on Semiconductor Manufacturing and IEEE Transactions on Electron Devices: Special Issue on Semiconductor Design for Manufacturing (DFM)","authors":"","doi":"10.1109/TSM.2024.3356972","DOIUrl":"https://doi.org/10.1109/TSM.2024.3356972","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 1","pages":"137-137"},"PeriodicalIF":2.7,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10419386","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139695042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-27DOI: 10.1109/TSM.2023.3347606
Ajay Kumar Dwivedi;Satyabrata Jit;Shweta Tripathi
This letter reports a SnS2 and ZnO nanocomposite (NC) prepared by dispersion method. The nanocomposite shows promising characteristics for optoelectronic application. SnS2:ZnO NC shows a wide absorption spectrum covering ultraviolet (UV)-visible-near infrared (NIR) regions. Hence, using the proposed nanocomposite a broadband photodetector with a structure comprising Al/ SnS2:ZnO/PEDOT:PSS/ Indium Tin Oxide (ITO) is fabricated. At a bias voltage of 1 V, the measured responsivity values (A/W) of the proposed device are 140.41, 848.63, and 1094.48 at 350 nm (UV), 750 nm (visible) and 900 nm (NIR), respectively.
{"title":"SnS₂ and ZnO Nanocomposite Prepared by Dispersion Method for Photodetector Application","authors":"Ajay Kumar Dwivedi;Satyabrata Jit;Shweta Tripathi","doi":"10.1109/TSM.2023.3347606","DOIUrl":"https://doi.org/10.1109/TSM.2023.3347606","url":null,"abstract":"This letter reports a SnS2 and ZnO nanocomposite (NC) prepared by dispersion method. The nanocomposite shows promising characteristics for optoelectronic application. SnS2:ZnO NC shows a wide absorption spectrum covering ultraviolet (UV)-visible-near infrared (NIR) regions. Hence, using the proposed nanocomposite a broadband photodetector with a structure comprising Al/ SnS2:ZnO/PEDOT:PSS/ Indium Tin Oxide (ITO) is fabricated. At a bias voltage of 1 V, the measured responsivity values (A/W) of the proposed device are 140.41, 848.63, and 1094.48 at 350 nm (UV), 750 nm (visible) and 900 nm (NIR), respectively.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 1","pages":"129-136"},"PeriodicalIF":2.7,"publicationDate":"2023-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139695007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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