Pub Date : 2023-09-20DOI: 10.1109/TSM.2023.3317679
Wen-Chi Chien;Ywh-Leh Chou;Cheng-Hung Wu
This research studies the problems of stochastic dynamic scheduling in production systems with batch processes and process queue time (PQT) constraints. The production systems consist of upstream batch processing machines and downstream single processing machines. Under the PQT constraint, waiting time in the downstream queue is constrained by an upper limit and violating this constraint causes scraps of jobs. The batch process increases the probability of PQT constraint violation because a batch of work-in-processes (WIPs) will move simultaneously into the downstream queue after the service completion of batch processes and suffer from higher waiting time variance. A batch process admission control (BPAC) model is developed using Markov decision processes to minimize the sum of long-run average waiting and scrap costs. The proposed BPAC model explicitly considers uncertain factors in production systems given that uncertainties are major reasons for PQT constraint violation. These uncertain factors include job arrival, processing time, and machine breakdown/repair. To cope with these uncertain factors, the BPAC control decisions change dynamically with the real-time machine health and WIP distribution. The performance of BPAC is validated using discrete event simulation, and the simulation results confirm the significant performance improvement in a wide range of batch production environments.
{"title":"Stochastic Scheduling for Batch Processes With Downstream Queue Time Constraints","authors":"Wen-Chi Chien;Ywh-Leh Chou;Cheng-Hung Wu","doi":"10.1109/TSM.2023.3317679","DOIUrl":"https://doi.org/10.1109/TSM.2023.3317679","url":null,"abstract":"This research studies the problems of stochastic dynamic scheduling in production systems with batch processes and process queue time (PQT) constraints. The production systems consist of upstream batch processing machines and downstream single processing machines. Under the PQT constraint, waiting time in the downstream queue is constrained by an upper limit and violating this constraint causes scraps of jobs. The batch process increases the probability of PQT constraint violation because a batch of work-in-processes (WIPs) will move simultaneously into the downstream queue after the service completion of batch processes and suffer from higher waiting time variance. A batch process admission control (BPAC) model is developed using Markov decision processes to minimize the sum of long-run average waiting and scrap costs. The proposed BPAC model explicitly considers uncertain factors in production systems given that uncertainties are major reasons for PQT constraint violation. These uncertain factors include job arrival, processing time, and machine breakdown/repair. To cope with these uncertain factors, the BPAC control decisions change dynamically with the real-time machine health and WIP distribution. The performance of BPAC is validated using discrete event simulation, and the simulation results confirm the significant performance improvement in a wide range of batch production environments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 4","pages":"599-610"},"PeriodicalIF":2.7,"publicationDate":"2023-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71903203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-12DOI: 10.1109/TSM.2023.3314431
Adar A. Kalir;Sin Kit Lo;Gavan Goldberg;Irena Zingerman-Koladko;Aviv Ohana;Yossi Revah;Tsvi Ben Chimol;Gavriel Honig
In this case study, we introduce two ML techniques, Long Short-Term Memory (LSTM) and an optimized Random Forest (RF), to address challenges related to capacity and cost, by addressing problems of unscheduled downtime and Process Time (PT) variation in the case of a complex chamber processing tool. We show that by using these ML techniques, traditional methods of Predictive Maintenance (PdM) and PT analysis can be enhanced with new insights and lead to significant productivity improvements. We demonstrate that, with these methods, by detecting states and attributes of the tool, trends in the tool’s behavior can be more effectively identified to reduce its unscheduled downtime and improve its run-rate, thereby resulting in significant capacity and cost improvements. This is achieved by reducing the variability of availability; extending the Mean Time Between Failures (MTBF); and removing variability in PT between lots and chambers.
{"title":"Leveraging Machine Learning for Capacity and Cost on a Complex Toolset: A Case Study","authors":"Adar A. Kalir;Sin Kit Lo;Gavan Goldberg;Irena Zingerman-Koladko;Aviv Ohana;Yossi Revah;Tsvi Ben Chimol;Gavriel Honig","doi":"10.1109/TSM.2023.3314431","DOIUrl":"https://doi.org/10.1109/TSM.2023.3314431","url":null,"abstract":"In this case study, we introduce two ML techniques, Long Short-Term Memory (LSTM) and an optimized Random Forest (RF), to address challenges related to capacity and cost, by addressing problems of unscheduled downtime and Process Time (PT) variation in the case of a complex chamber processing tool. We show that by using these ML techniques, traditional methods of Predictive Maintenance (PdM) and PT analysis can be enhanced with new insights and lead to significant productivity improvements. We demonstrate that, with these methods, by detecting states and attributes of the tool, trends in the tool’s behavior can be more effectively identified to reduce its unscheduled downtime and improve its run-rate, thereby resulting in significant capacity and cost improvements. This is achieved by reducing the variability of availability; extending the Mean Time Between Failures (MTBF); and removing variability in PT between lots and chambers.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 4","pages":"611-618"},"PeriodicalIF":2.7,"publicationDate":"2023-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71903204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-04DOI: 10.1109/TSM.2023.3311452
Kristof J. P. Jacobs;Eric Beyne
A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need for a costly backside approach that requires a solid immersion lens. The top silicon substrate is removed using laser lithography and selective etching techniques, enabling the utilization of 405 nm excitation light for the VL-OBIRCH analysis. The validity of the methodology is demonstrated on W2W interconnect test structures with varying interconnect pitch and pad dimensions. The effectiveness of the proposed approach is confirmed through cross-sectional analysis.
{"title":"Defect Localization Approach for Wafer-to-Wafer Hybrid Bonding Interconnects","authors":"Kristof J. P. Jacobs;Eric Beyne","doi":"10.1109/TSM.2023.3311452","DOIUrl":"10.1109/TSM.2023.3311452","url":null,"abstract":"A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need for a costly backside approach that requires a solid immersion lens. The top silicon substrate is removed using laser lithography and selective etching techniques, enabling the utilization of 405 nm excitation light for the VL-OBIRCH analysis. The validity of the methodology is demonstrated on W2W interconnect test structures with varying interconnect pitch and pad dimensions. The effectiveness of the proposed approach is confirmed through cross-sectional analysis.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 4","pages":"673-675"},"PeriodicalIF":2.7,"publicationDate":"2023-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62684571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-04DOI: 10.1109/TSM.2023.3311091
Stacy A. Lynrah;Lim Ying Ying;P. Chinnamuthu
Deposition of the manganese dioxide (MnO2) Thin Film (TF) was carried out by Electron beam (E-beam) evaporation technique. Structural, optical, and electrical characteristics reveal that MnO2 undergoes a phase transformation due to annealing temperature. Photoluminescence (PL) emission reveals the highest intensities at 500°C, indicating the least density of defects present in the sample. Moreover, the XRD analysis is very much in accordance with the optical and electrical results. The I-V characteristics show a significant enhancement at 500°C, with an improved Ilight/Idark ratio. The barrier height increases with the temperature while decreasing at 500°C due to decreased defects. At 500°C, a least ideality factor of value 1.5 is obtained. If the temperature exceeds 500°C, MnO2 breaks into other oxides like Mn2O3 and Mn3O4. Hence annealing at 500°C is an optimum temperature for better structural, optical, and electrical properties of MnO2 TF, showing great promise for future optoelectronics applications.
{"title":"Impact of Annealing Temperature on MnO2 Thin Films: Morphological, Structural, and Electrical Properties","authors":"Stacy A. Lynrah;Lim Ying Ying;P. Chinnamuthu","doi":"10.1109/TSM.2023.3311091","DOIUrl":"10.1109/TSM.2023.3311091","url":null,"abstract":"Deposition of the manganese dioxide (MnO2) Thin Film (TF) was carried out by Electron beam (E-beam) evaporation technique. Structural, optical, and electrical characteristics reveal that MnO2 undergoes a phase transformation due to annealing temperature. Photoluminescence (PL) emission reveals the highest intensities at 500°C, indicating the least density of defects present in the sample. Moreover, the XRD analysis is very much in accordance with the optical and electrical results. The I-V characteristics show a significant enhancement at 500°C, with an improved Ilight/Idark ratio. The barrier height increases with the temperature while decreasing at 500°C due to decreased defects. At 500°C, a least ideality factor of value 1.5 is obtained. If the temperature exceeds 500°C, MnO2 breaks into other oxides like Mn2O3 and Mn3O4. Hence annealing at 500°C is an optimum temperature for better structural, optical, and electrical properties of MnO2 TF, showing great promise for future optoelectronics applications.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 4","pages":"666-672"},"PeriodicalIF":2.7,"publicationDate":"2023-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62684502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-21DOI: 10.1109/TSM.2023.3306751
Gangmin Cho;Taeyoung Kim;Youngsoo Shin
OPC is a very time consuming process for mask synthesis. Quick and accurate OPC using GCN with layout encoder and mask decoder is proposed. (1) GCN performs a series of aggregation with MLP for correction process. A feature of a particular polygon is aggregated with weighted features of neighbor polygons; this is a key motivation of using GCN since one polygon should be corrected while its neighbors are taken into account for more accurate correction. (2) GCN inputs are provided by a layout encoder, which extracts a feature from each layout polygon. GCN outputs, features corresponding to corrected polygons, are processed by a mask decoder to yield the final mask pattern. (3) The encoder and decoder originate from respective autoencoders. High fidelity of decoder is a key for OPC quality. This is achieved by collective training of the two autoencoders with a single loss function while the encoder and decoder are connected. Experiments demonstrate that the proposed OPC achieves 47% smaller EPE than OPC using a simple MLP model.
{"title":"Fast Optical Proximity Correction Using Graph Convolutional Network With Autoencoders","authors":"Gangmin Cho;Taeyoung Kim;Youngsoo Shin","doi":"10.1109/TSM.2023.3306751","DOIUrl":"10.1109/TSM.2023.3306751","url":null,"abstract":"OPC is a very time consuming process for mask synthesis. Quick and accurate OPC using GCN with layout encoder and mask decoder is proposed. (1) GCN performs a series of aggregation with MLP for correction process. A feature of a particular polygon is aggregated with weighted features of neighbor polygons; this is a key motivation of using GCN since one polygon should be corrected while its neighbors are taken into account for more accurate correction. (2) GCN inputs are provided by a layout encoder, which extracts a feature from each layout polygon. GCN outputs, features corresponding to corrected polygons, are processed by a mask decoder to yield the final mask pattern. (3) The encoder and decoder originate from respective autoencoders. High fidelity of decoder is a key for OPC quality. This is achieved by collective training of the two autoencoders with a single loss function while the encoder and decoder are connected. Experiments demonstrate that the proposed OPC achieves 47% smaller EPE than OPC using a simple MLP model.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 4","pages":"629-635"},"PeriodicalIF":2.7,"publicationDate":"2023-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62684936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-14DOI: 10.1109/TSM.2023.3304722
Haiyan Wang;Tianhong Pan;Guochu Chen
The carry-over effect is a common phenomenon in the semiconductor manufacturing process, giving the process a dynamic nature. Dynamic models are more accurate but with a consequent increase in uncertainty. Therefore, it is very important to eliminate the uncertainty and disturbance at the same time. To this end, a run-to-run (RtR) control scheme based on discrete active disturbance rejection control (DADRC) is proposed in this work. The process recipe is calculated using the state error feedback law, relying on the extended state observer (ESO) to effectively suppress the total disturbance synthesized by model uncertainty and external disturbance. Considering that tool aging often leads to drift disturbances in semiconductor manufacturing processes, a model-assisted ESO with two extended states is designed to estimate process states and total disturbance. Then an optimal observer gain is derived to minimize the estimation error. Finally, the numerical and industrial cases provide compelling evidence of the effectiveness of the proposed control scheme in suppressing tool-aging drift disturbance and a remarkable degree of tolerance towards uncertainties in the system model’s order and parameters.
{"title":"Discrete Active Disturbance Rejection Control for Semiconductor Manufacturing Processes With Dynamic Models","authors":"Haiyan Wang;Tianhong Pan;Guochu Chen","doi":"10.1109/TSM.2023.3304722","DOIUrl":"10.1109/TSM.2023.3304722","url":null,"abstract":"The carry-over effect is a common phenomenon in the semiconductor manufacturing process, giving the process a dynamic nature. Dynamic models are more accurate but with a consequent increase in uncertainty. Therefore, it is very important to eliminate the uncertainty and disturbance at the same time. To this end, a run-to-run (RtR) control scheme based on discrete active disturbance rejection control (DADRC) is proposed in this work. The process recipe is calculated using the state error feedback law, relying on the extended state observer (ESO) to effectively suppress the total disturbance synthesized by model uncertainty and external disturbance. Considering that tool aging often leads to drift disturbances in semiconductor manufacturing processes, a model-assisted ESO with two extended states is designed to estimate process states and total disturbance. Then an optimal observer gain is derived to minimize the estimation error. Finally, the numerical and industrial cases provide compelling evidence of the effectiveness of the proposed control scheme in suppressing tool-aging drift disturbance and a remarkable degree of tolerance towards uncertainties in the system model’s order and parameters.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 4","pages":"636-644"},"PeriodicalIF":2.7,"publicationDate":"2023-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62684924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-11DOI: 10.1109/TSM.2023.3304517
Patrick Deenen;Wim Nuijten;Alp Akcay
This paper studies the problem of scheduling machines in the photolithography area of a semiconductor manufacturing facility. The scheduling problem is characterized as an unrelated parallel machine scheduling problem with machine eligibilities, sequence- and machine-dependent setup times, auxiliary resources and transfer times for the auxiliary resources. Each job requires two auxiliary resources: a reticle and a pod. Reticles are handled in pods and a pod contains multiple reticles. Both reticles and pods are used on multiple machines and a transfer time is required if transferred from one machine to another. A novel constraint programming (CP) approach is proposed and is benchmarked against a mixed-integer programming (MIP) method. The results of the study, consisting of a real-world case study at a global semiconductor manufacturer, demonstrate that the CP approach significantly outperforms the MIP method and produces high-quality solutions for multiple real-world instances, although optimality cannot be guaranteed.
{"title":"Scheduling a Real-World Photolithography Area With Constraint Programming","authors":"Patrick Deenen;Wim Nuijten;Alp Akcay","doi":"10.1109/TSM.2023.3304517","DOIUrl":"10.1109/TSM.2023.3304517","url":null,"abstract":"This paper studies the problem of scheduling machines in the photolithography area of a semiconductor manufacturing facility. The scheduling problem is characterized as an unrelated parallel machine scheduling problem with machine eligibilities, sequence- and machine-dependent setup times, auxiliary resources and transfer times for the auxiliary resources. Each job requires two auxiliary resources: a reticle and a pod. Reticles are handled in pods and a pod contains multiple reticles. Both reticles and pods are used on multiple machines and a transfer time is required if transferred from one machine to another. A novel constraint programming (CP) approach is proposed and is benchmarked against a mixed-integer programming (MIP) method. The results of the study, consisting of a real-world case study at a global semiconductor manufacturer, demonstrate that the CP approach significantly outperforms the MIP method and produces high-quality solutions for multiple real-world instances, although optimality cannot be guaranteed.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 4","pages":"590-598"},"PeriodicalIF":2.7,"publicationDate":"2023-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62684882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-04DOI: 10.1109/TSM.2023.3277155
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on \"Wide and Ultrawide Band Gap Semiconductor Devices for RF and Power Applications\"","authors":"","doi":"10.1109/TSM.2023.3277155","DOIUrl":"https://doi.org/10.1109/TSM.2023.3277155","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 3","pages":"494-495"},"PeriodicalIF":2.7,"publicationDate":"2023-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/66/10209215/10209284.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3510005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-04DOI: 10.1109/TSM.2023.3277157
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2023.3277157","DOIUrl":"https://doi.org/10.1109/TSM.2023.3277157","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 3","pages":"C3-C3"},"PeriodicalIF":2.7,"publicationDate":"2023-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/66/10209215/10209218.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3494689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-04DOI: 10.1109/TSM.2023.3301288
{"title":"Call for Papers: 8th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference 2024","authors":"","doi":"10.1109/TSM.2023.3301288","DOIUrl":"https://doi.org/10.1109/TSM.2023.3301288","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"36 3","pages":"496-496"},"PeriodicalIF":2.7,"publicationDate":"2023-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/66/10209215/10209216.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"3488464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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