Pub Date : 2025-02-25DOI: 10.1109/TSM.2025.3534595
{"title":"Call for Papers for Journal of Lightwave Technology: Special Issue on OFS-29","authors":"","doi":"10.1109/TSM.2025.3534595","DOIUrl":"https://doi.org/10.1109/TSM.2025.3534595","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"110-110"},"PeriodicalIF":2.3,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10903546","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-25DOI: 10.1109/TSM.2025.3534593
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Materials for Electron Devices: \"Exploration of the Exciting World of Multifunctional Oxide-Based Electronic Devices: From Material to System-Level Applications\"","authors":"","doi":"10.1109/TSM.2025.3534593","DOIUrl":"https://doi.org/10.1109/TSM.2025.3534593","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"108-109"},"PeriodicalIF":2.3,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10903522","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-25DOI: 10.1109/TSM.2025.3534606
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2025.3534606","DOIUrl":"https://doi.org/10.1109/TSM.2025.3534606","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"C3-C3"},"PeriodicalIF":2.3,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10903151","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A wafer warpage prediction model for trench field-plate MOSFETs on large diameter wafers is proposed. Trench field-plate MOSFETs have deeper trenches and thicker oxides compared to conventional power MOSFETs, and the stress imbalance between the front and back of the wafer must be controlled to suppress wafer warpage in the mass-production process. Therefore, predicting wafer warpage throughout the process is a key technology from the viewpoint of process integration, and its importance is increasing with the use of large-diameter wafers. In this study, as a main process module in trench field-plate power MOSFET process, the processes of trench formation, oxidation, polysilicon deposition, and annealing were examined. The wafer warpage and Raman shift were analyzed by comparing the experiment results with simulations in a 300 mm diameter process. Based on the measured wafer warpage, anisotropic deformation of the poly silicon after annealing was suggested, and a new model considering this anisotropic deformation was developed to predict the through-process for 300 mm wafers.
{"title":"A Warpage Prediction Model for Trench Field-Plate Power MOSFET in 300mm-Diameter Process","authors":"Hiroaki Kato;Bozhou Cai;Jiuyang Yuan;Shin-Ichi Nishizawa;Wataru Saito","doi":"10.1109/TSM.2025.3543133","DOIUrl":"https://doi.org/10.1109/TSM.2025.3543133","url":null,"abstract":"A wafer warpage prediction model for trench field-plate MOSFETs on large diameter wafers is proposed. Trench field-plate MOSFETs have deeper trenches and thicker oxides compared to conventional power MOSFETs, and the stress imbalance between the front and back of the wafer must be controlled to suppress wafer warpage in the mass-production process. Therefore, predicting wafer warpage throughout the process is a key technology from the viewpoint of process integration, and its importance is increasing with the use of large-diameter wafers. In this study, as a main process module in trench field-plate power MOSFET process, the processes of trench formation, oxidation, polysilicon deposition, and annealing were examined. The wafer warpage and Raman shift were analyzed by comparing the experiment results with simulations in a 300 mm diameter process. Based on the measured wafer warpage, anisotropic deformation of the poly silicon after annealing was suggested, and a new model considering this anisotropic deformation was developed to predict the through-process for 300 mm wafers.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"263-269"},"PeriodicalIF":2.3,"publicationDate":"2025-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-18DOI: 10.1109/TSM.2025.3543453
Noah Graff;Dragan Djurdjanovic
This paper presents a metaheuristic optimization-based approach for selecting a pre-determined number of measurement markers from the set of available markers that optimizes the performance of the recently introduced robust ${mathrm { L}}^{infty }$ norm overlay control algorithm, which robustly minimizes the worst overlay error across a given pattern layer. This optimization is then used in a Design of Experiments (DOE) setting to build a tractable regression model of a customizable objective function encompassing cost effects of quality losses and throughput benefits resulting from the down-selection of markers selected for robust overlay control. Using this model, one can rapidly determine the optimal proportion of markers for any set of cost parameters, and the optimal subset forming this proportion of available markers can be down-selected to maximize performance of the resulting robust overlay controller. Overlay data and models from a semiconductor manufacturing fab were used to evaluate the newly proposed inspection and control strategy. Results clearly indicate that the novel strategic down-selection of measurement markers coupled with robust overlay control could lead to vastly improved throughputs without decreasing quality relative to what can be achieved using traditional Run-to-Run (R2R) control. Feasibility of the novel DOE-based optimization was demonstrated for two scenarios of cost-effect parameters.
{"title":"Throughput and Quality Optimized Down-Selection of Overlay Measurement Markers for Robust Control of the Maximum Overlay Error in a Pattern Layer in Photolithography Processes","authors":"Noah Graff;Dragan Djurdjanovic","doi":"10.1109/TSM.2025.3543453","DOIUrl":"https://doi.org/10.1109/TSM.2025.3543453","url":null,"abstract":"This paper presents a metaheuristic optimization-based approach for selecting a pre-determined number of measurement markers from the set of available markers that optimizes the performance of the recently introduced robust <inline-formula> <tex-math>${mathrm { L}}^{infty }$ </tex-math></inline-formula> norm overlay control algorithm, which robustly minimizes the worst overlay error across a given pattern layer. This optimization is then used in a Design of Experiments (DOE) setting to build a tractable regression model of a customizable objective function encompassing cost effects of quality losses and throughput benefits resulting from the down-selection of markers selected for robust overlay control. Using this model, one can rapidly determine the optimal proportion of markers for any set of cost parameters, and the optimal subset forming this proportion of available markers can be down-selected to maximize performance of the resulting robust overlay controller. Overlay data and models from a semiconductor manufacturing fab were used to evaluate the newly proposed inspection and control strategy. Results clearly indicate that the novel strategic down-selection of measurement markers coupled with robust overlay control could lead to vastly improved throughputs without decreasing quality relative to what can be achieved using traditional Run-to-Run (R2R) control. Feasibility of the novel DOE-based optimization was demonstrated for two scenarios of cost-effect parameters.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"251-262"},"PeriodicalIF":2.3,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-13DOI: 10.1109/TSM.2025.3535145
Jeff J. Ye;Raviteja Pagadala;Fei Lu
Defect and line width roughness (LWR) are two main yield detractors in advanced plasma etch process in high-volume memory manufacturing. In this paper, we present the results of defect reduction and LWR improvement by using a post pre-coat treatment (PPT) method in waferless chamber clean (WCC) recipe. Adding a PPT step at the end of WCC recipe reduces defect, inline critical dimension (CD) variation and LWR. Atomic force microscopy (AFM) results show pre-coat silicon oxide and/or PPT improves surface roughness by 30%. X-ray photoelectron spectroscopy (XPS) has been utilized to characterize the surfaces treated with and without PPT, indicating PPT can remove residue chloride and solidify SiO2 film from its loose form. With the implementation of WCC with PPT, we have achieved yield improvement, which is attributed to defect reduction, tighter inline CD and LWR improvement.
{"title":"Defect Reduction and Line Width Roughness Improvement by Using a Post Precoat Treatment in Waferless Chamber Conditioning","authors":"Jeff J. Ye;Raviteja Pagadala;Fei Lu","doi":"10.1109/TSM.2025.3535145","DOIUrl":"https://doi.org/10.1109/TSM.2025.3535145","url":null,"abstract":"Defect and line width roughness (LWR) are two main yield detractors in advanced plasma etch process in high-volume memory manufacturing. In this paper, we present the results of defect reduction and LWR improvement by using a post pre-coat treatment (PPT) method in waferless chamber clean (WCC) recipe. Adding a PPT step at the end of WCC recipe reduces defect, inline critical dimension (CD) variation and LWR. Atomic force microscopy (AFM) results show pre-coat silicon oxide and/or PPT improves surface roughness by 30%. X-ray photoelectron spectroscopy (XPS) has been utilized to characterize the surfaces treated with and without PPT, indicating PPT can remove residue chloride and solidify SiO2 film from its loose form. With the implementation of WCC with PPT, we have achieved yield improvement, which is attributed to defect reduction, tighter inline CD and LWR improvement.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"399-403"},"PeriodicalIF":2.3,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/TSM.2025.3539223
Bangxu Liu;Dewen Zhao;Xinchun Lu;Yuhong Liu
The quality of semiconductor fabrication processes is typically degraded by variations in the manufacturing environment, which can be suppressed by run-to-run (R2R) control schemes. The performance of controlling systems to the produce process which is always highly complex and nonlinear physical model thus is strongly associated with the controlling strategy. However, previous works focusing on less complex semiconductor fabrication processes or linear controlling strategy are both hard to extend the application scenario. A novel structure for a R2R control system based on a distributed form of deep reinforcement learning (DRL), namely, distributional soft actor-critic (DSAC) DRL with twin-value distribution learning, is proposed for multizone pressure control in the chemical mechanical planarization (CMP) process, which is one of the most crucial manufacturing processes for the fabrication of ultra-large integrated circuits (ICs). In addition, several optimization algorithms for DRL, such as twin value distribution learning, are applied, further improving DSAC DRL to enhance the control performance. Compared with other reinforcement learning (RL)-based controllers, the proposed RL control policy achieves better control performance when tested using a multizone CMP virtual metrology (VM) model based on long short-term memory (LSTM) and one-dimensional convolutional neural network (1DCNN) architectures. This deep neural network (DNN) VM model, which is applied for the first time here to test the proposed DRL-based R2R controller for semiconductor manufacturing, is designed to preserve the complexity and nonlinearity of the CMP process by using data recorded from a practical manufacturing process at an IC fabrication facility in Tianjin, China. The novel model-free controlling schemes combined with the new VM model can be used in different R2R application scenarios. Meanwhile the results achieved using the proposed DRL control strategy strongly support its potential application in modern industrial semiconductor manufacturing and offer practical guidance for the further development of CMP procedures.
{"title":"Process Control in Semiconductor Manufacturing Based on Deep Distributional Soft Actor-Critic Reinforcement Learning","authors":"Bangxu Liu;Dewen Zhao;Xinchun Lu;Yuhong Liu","doi":"10.1109/TSM.2025.3539223","DOIUrl":"https://doi.org/10.1109/TSM.2025.3539223","url":null,"abstract":"The quality of semiconductor fabrication processes is typically degraded by variations in the manufacturing environment, which can be suppressed by run-to-run (R2R) control schemes. The performance of controlling systems to the produce process which is always highly complex and nonlinear physical model thus is strongly associated with the controlling strategy. However, previous works focusing on less complex semiconductor fabrication processes or linear controlling strategy are both hard to extend the application scenario. A novel structure for a R2R control system based on a distributed form of deep reinforcement learning (DRL), namely, distributional soft actor-critic (DSAC) DRL with twin-value distribution learning, is proposed for multizone pressure control in the chemical mechanical planarization (CMP) process, which is one of the most crucial manufacturing processes for the fabrication of ultra-large integrated circuits (ICs). In addition, several optimization algorithms for DRL, such as twin value distribution learning, are applied, further improving DSAC DRL to enhance the control performance. Compared with other reinforcement learning (RL)-based controllers, the proposed RL control policy achieves better control performance when tested using a multizone CMP virtual metrology (VM) model based on long short-term memory (LSTM) and one-dimensional convolutional neural network (1DCNN) architectures. This deep neural network (DNN) VM model, which is applied for the first time here to test the proposed DRL-based R2R controller for semiconductor manufacturing, is designed to preserve the complexity and nonlinearity of the CMP process by using data recorded from a practical manufacturing process at an IC fabrication facility in Tianjin, China. The novel model-free controlling schemes combined with the new VM model can be used in different R2R application scenarios. Meanwhile the results achieved using the proposed DRL control strategy strongly support its potential application in modern industrial semiconductor manufacturing and offer practical guidance for the further development of CMP procedures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"210-231"},"PeriodicalIF":2.3,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/TSM.2025.3540267
Angelo Rossoni;Tomasz Brozek;Sharad Saxena;Rajesh Khamankar;Luigi Colalongo;Zsolt M. Kovacs-Vajna
Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modulated by device design and local/ global environment. In this paper we investigate the impact of stress, developed during FinFET device fabrication, on electrical characteristics of transistors manufactured in 7nm silicon FinFET technology. Two sources of stress modulation are studied: (i) active region isolation (Diffusion Break) (ii) Metal Gate extension outside of the fins of the transistor. A 3D TCAD process model of a FinFET device was created and calibrated using electrical characteristics measured on foundry fabricated silicon wafers. The model was then applied to simulate mechanical stress in transistors with various design attributes for Diffusion Breaks (Single vs. Double Diffusion Break) and Gate Cuts, following by modeling of electrical characteristics. Very good agreement between simulations and measured silicon data has been obtained for PMOS and NMOS FinFET transistors. This work demonstrates that the layout sensitivity in discussed design cases can be explained by modulation of the mechanical stress and that the model can be used to predict successfully the stress distributions and their impact on electrical characteristics of FinFET devices. It can be applied to assist designers and technologists with Design-Technology Co-optimization, design rule and PDK development, and process optimization for best performance and reduced variability.
{"title":"Stress-Related Local Layout Effects in FinFET Technology and Device Design Sensitivity","authors":"Angelo Rossoni;Tomasz Brozek;Sharad Saxena;Rajesh Khamankar;Luigi Colalongo;Zsolt M. Kovacs-Vajna","doi":"10.1109/TSM.2025.3540267","DOIUrl":"https://doi.org/10.1109/TSM.2025.3540267","url":null,"abstract":"Transistor characteristics in advanced technology nodes are strongly impacted by devices design and process integration choices. Variation in the layout and pattern configuration in close proximity to the device often causes undesirable sensitivities known as Local Layout Effects (LLEs). One of the sensitivities is related to carrier mobility dependence on mechanical stress, modulated by device design and local/ global environment. In this paper we investigate the impact of stress, developed during FinFET device fabrication, on electrical characteristics of transistors manufactured in 7nm silicon FinFET technology. Two sources of stress modulation are studied: (i) active region isolation (Diffusion Break) (ii) Metal Gate extension outside of the fins of the transistor. A 3D TCAD process model of a FinFET device was created and calibrated using electrical characteristics measured on foundry fabricated silicon wafers. The model was then applied to simulate mechanical stress in transistors with various design attributes for Diffusion Breaks (Single vs. Double Diffusion Break) and Gate Cuts, following by modeling of electrical characteristics. Very good agreement between simulations and measured silicon data has been obtained for PMOS and NMOS FinFET transistors. This work demonstrates that the layout sensitivity in discussed design cases can be explained by modulation of the mechanical stress and that the model can be used to predict successfully the stress distributions and their impact on electrical characteristics of FinFET devices. It can be applied to assist designers and technologists with Design-Technology Co-optimization, design rule and PDK development, and process optimization for best performance and reduced variability.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"117-125"},"PeriodicalIF":2.3,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-10DOI: 10.1109/TSM.2025.3539456
Kangjian Cheng;Jingyan Huang;Wen Siang Lew
We report the demonstration of the crystallization of amorphous arsenic and boron-doped silicon films on dielectric substrates at reduced thermal budgets. The conventional methods to form polycrystalline silicon generally require growth temperatures of at least $600~^{circ }$ C, or high-temperature post-annealing to transform the silicon structure from amorphous into polycrystalline. Here, we show the formation of high-quality polycrystalline silicon at temperatures between $500~^{circ }$ C and $550~^{circ }$ C, which helps to reduce the thermal budget strain on heterojunction bipolar transistor devices. This advancement is attained by selecting buffer layer materials and fine-tuning film thickness. A notable increase in the film conductivity was observed, with improvements of 66% and 1719% for arsenic and boron-doped silicon films, respectively, compared to structured-mixed silicon films. The crystalline nature of the films is confirmed through top-view scanning electron microscopy coupled with ImageJ software analysis, offering a rapid, inline approach for crystal percentage quantification. Additionally, cross-sectional transmission electron microscopy analyses verify the complete film crystallization.
{"title":"Enhanced Silicon Crystallization on Dielectric Materials at Reduced Temperature","authors":"Kangjian Cheng;Jingyan Huang;Wen Siang Lew","doi":"10.1109/TSM.2025.3539456","DOIUrl":"https://doi.org/10.1109/TSM.2025.3539456","url":null,"abstract":"We report the demonstration of the crystallization of amorphous arsenic and boron-doped silicon films on dielectric substrates at reduced thermal budgets. The conventional methods to form polycrystalline silicon generally require growth temperatures of at least <inline-formula> <tex-math>$600~^{circ }$ </tex-math></inline-formula>C, or high-temperature post-annealing to transform the silicon structure from amorphous into polycrystalline. Here, we show the formation of high-quality polycrystalline silicon at temperatures between <inline-formula> <tex-math>$500~^{circ }$ </tex-math></inline-formula>C and <inline-formula> <tex-math>$550~^{circ }$ </tex-math></inline-formula>C, which helps to reduce the thermal budget strain on heterojunction bipolar transistor devices. This advancement is attained by selecting buffer layer materials and fine-tuning film thickness. A notable increase in the film conductivity was observed, with improvements of 66% and 1719% for arsenic and boron-doped silicon films, respectively, compared to structured-mixed silicon films. The crystalline nature of the films is confirmed through top-view scanning electron microscopy coupled with ImageJ software analysis, offering a rapid, inline approach for crystal percentage quantification. Additionally, cross-sectional transmission electron microscopy analyses verify the complete film crystallization.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"203-209"},"PeriodicalIF":2.3,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-06DOI: 10.1109/TSM.2025.3539300
Chengzhen Yu;Sheng Liu;Wensheng Chen;Xu Ma
Simulation of thick-mask effects is an important task in computational lithography within extreme ultraviolet (EUV) waveband. This paper proposes a fast and accurate learning-based thick-mask model dubbed multi-channel block attention network (MCBA-Net) to solve this problem for EUV lithography. The proposed MCBA-Net introduces geometric feature attention module and structural feature attention module to improve the computation accuracy of thick-mask diffraction near field. During the training process, the proposed attention modules can effectively learn the impact of the three-dimensional mask diffraction behavior. In addition, the multi-channel network architecture is used to simultaneously synthesize the thick-mask diffraction matrices under different polarization states, and the coupling between different diffraction matrices is addressed. Numerical experiments show that the proposed model improves the computational efficiency by more than 20-fold over the rigorous simulator, and reduces the prediction error by 25%~50% compared with the state-of-the-art deep learning models. In addition, the generalization ability of the proposed method is proved using a complex testing pattern.
{"title":"Fast and Accurate EUVL Thick-Mask Model Based on Multi-Channel Attention Network","authors":"Chengzhen Yu;Sheng Liu;Wensheng Chen;Xu Ma","doi":"10.1109/TSM.2025.3539300","DOIUrl":"https://doi.org/10.1109/TSM.2025.3539300","url":null,"abstract":"Simulation of thick-mask effects is an important task in computational lithography within extreme ultraviolet (EUV) waveband. This paper proposes a fast and accurate learning-based thick-mask model dubbed multi-channel block attention network (MCBA-Net) to solve this problem for EUV lithography. The proposed MCBA-Net introduces geometric feature attention module and structural feature attention module to improve the computation accuracy of thick-mask diffraction near field. During the training process, the proposed attention modules can effectively learn the impact of the three-dimensional mask diffraction behavior. In addition, the multi-channel network architecture is used to simultaneously synthesize the thick-mask diffraction matrices under different polarization states, and the coupling between different diffraction matrices is addressed. Numerical experiments show that the proposed model improves the computational efficiency by more than 20-fold over the rigorous simulator, and reduces the prediction error by 25%~50% compared with the state-of-the-art deep learning models. In addition, the generalization ability of the proposed method is proved using a complex testing pattern.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"194-202"},"PeriodicalIF":2.3,"publicationDate":"2025-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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