Pub Date : 2025-08-21DOI: 10.1109/TSM.2025.3575487
{"title":"Call for Papers for a Special Issue of IEEE Transactions on Electron Devices: Reliability of Advanced Nodes","authors":"","doi":"10.1109/TSM.2025.3575487","DOIUrl":"https://doi.org/10.1109/TSM.2025.3575487","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"736-737"},"PeriodicalIF":2.3,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11132379","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/TSM.2025.3594906
Xinqiao Dong;Subhadeep Mukherjee;Yi Yang;Vivek Duvvuru;Jing Nie
In semiconductor fabrication facilities, non-production test wafers constitute a substantial amount of the non-equipment-related consumable expense. With the escalating demand and increased costs associated with bare silicon test wafers, as well as the limited viability of external reclamation, the imperative to extend the lifecycle of recycled wafers and establish an in-house reclamation process has become pronounced for major chip manufacturers. External reclaim usually comes with a higher cost per wafer and a limited recycle lifespan. In contrast, in-house reclaim offers a cost that is significantly lower, at only a fraction of the external reclaim cost per wafer, and provides a much longer recycling lifespan, making it a more cost-effective solution. Historically, semiconductor fabs lacked the capability to recondition test wafers that had reached the end of their usable lifespan. Test wafers failing global specifications were downgraded and outsourced to external vendors for reclamation. This paper presents an innovative approach combining amorphous silica fine slurry, semi-hard pad configurations, and optimized scrub cleaning to achieve a 93% cost reduction and triple the recycling lifespan compared to external reclaim. The recently developed in-house wafer reclamation process at Micron has significant yield improvements, meets the global reclaim specifications. Furthermore, a novel combination of new CMP (Chemical Mechanical Polishing) slurries and process optimization in both CMP and Wet processes have been devised and effectively applied to the reclamation process, achieving an impressive reclaim yield for high-volume operations. These advances have instilled confidence in in-house recycling and reclamation processes within semiconductor fabrication. While specific figures remain confidential, the results of this paper underscore the viability of in-house silicon wafer reclamation and elucidate a cost-effective, high-yield methodology. These insights are intended for dissemination as an innovative method to achieve hundreds of millions of dollars annualized network savings and significant wastage reduction.
{"title":"In-House Test Wafer Reclaim for Fab Cost and Wastage Reduction","authors":"Xinqiao Dong;Subhadeep Mukherjee;Yi Yang;Vivek Duvvuru;Jing Nie","doi":"10.1109/TSM.2025.3594906","DOIUrl":"https://doi.org/10.1109/TSM.2025.3594906","url":null,"abstract":"In semiconductor fabrication facilities, non-production test wafers constitute a substantial amount of the non-equipment-related consumable expense. With the escalating demand and increased costs associated with bare silicon test wafers, as well as the limited viability of external reclamation, the imperative to extend the lifecycle of recycled wafers and establish an in-house reclamation process has become pronounced for major chip manufacturers. External reclaim usually comes with a higher cost per wafer and a limited recycle lifespan. In contrast, in-house reclaim offers a cost that is significantly lower, at only a fraction of the external reclaim cost per wafer, and provides a much longer recycling lifespan, making it a more cost-effective solution. Historically, semiconductor fabs lacked the capability to recondition test wafers that had reached the end of their usable lifespan. Test wafers failing global specifications were downgraded and outsourced to external vendors for reclamation. This paper presents an innovative approach combining amorphous silica fine slurry, semi-hard pad configurations, and optimized scrub cleaning to achieve a 93% cost reduction and triple the recycling lifespan compared to external reclaim. The recently developed in-house wafer reclamation process at Micron has significant yield improvements, meets the global reclaim specifications. Furthermore, a novel combination of new CMP (Chemical Mechanical Polishing) slurries and process optimization in both CMP and Wet processes have been devised and effectively applied to the reclamation process, achieving an impressive reclaim yield for high-volume operations. These advances have instilled confidence in in-house recycling and reclamation processes within semiconductor fabrication. While specific figures remain confidential, the results of this paper underscore the viability of in-house silicon wafer reclamation and elucidate a cost-effective, high-yield methodology. These insights are intended for dissemination as an innovative method to achieve hundreds of millions of dollars annualized network savings and significant wastage reduction.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"391-398"},"PeriodicalIF":2.3,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-31DOI: 10.1109/TSM.2025.3594651
Jaeho Lee;Jinhyeok Park;Sangpyo Hong;Illhoe Hwang;Seol Hwang;Young Jae Jang;Donghwi Shin;Jaeung Lee
The Autonomous Robot Orchestration Solution (AROS) is transforming the management of robot fleets by identifying the state and environment of each robot and enabling them to collaborate toward common goals. This paper introduces AROS and its application in controlling massive fleets of Overhead Hoist Transport (OHT) vehicles in semiconductor fabrication facilities. AROS leverages key technologies, including reinforcement learning algorithms, discrete event simulation, and real-time data collection through Digital Twin (DT). The DT replicates the real system in a virtual environment with real-time communication to optimize decision-making for OHTs. A key innovation of AROS is the introduction of active Q routing, a dynamic routing method that adapts to changing traffic conditions by predicting and adjusting travel times through discrete event simulation. Active Q routing enhances operational efficiency by mitigating congestion and reducing delays, even in highly dynamic environments. We demonstrate the effectiveness of AROS and active Q routing on OHT system performance, showcasing reductions in average delivery times and increases in delivery capacity. These findings are validated through real-world use cases in a large-scale semiconductor fab.
{"title":"Autonomous Robot Orchestration Solution for OHT With Active Q Routing and Digital Twin FA: Factory Automation","authors":"Jaeho Lee;Jinhyeok Park;Sangpyo Hong;Illhoe Hwang;Seol Hwang;Young Jae Jang;Donghwi Shin;Jaeung Lee","doi":"10.1109/TSM.2025.3594651","DOIUrl":"https://doi.org/10.1109/TSM.2025.3594651","url":null,"abstract":"The Autonomous Robot Orchestration Solution (AROS) is transforming the management of robot fleets by identifying the state and environment of each robot and enabling them to collaborate toward common goals. This paper introduces AROS and its application in controlling massive fleets of Overhead Hoist Transport (OHT) vehicles in semiconductor fabrication facilities. AROS leverages key technologies, including reinforcement learning algorithms, discrete event simulation, and real-time data collection through Digital Twin (DT). The DT replicates the real system in a virtual environment with real-time communication to optimize decision-making for OHTs. A key innovation of AROS is the introduction of active Q routing, a dynamic routing method that adapts to changing traffic conditions by predicting and adjusting travel times through discrete event simulation. Active Q routing enhances operational efficiency by mitigating congestion and reducing delays, even in highly dynamic environments. We demonstrate the effectiveness of AROS and active Q routing on OHT system performance, showcasing reductions in average delivery times and increases in delivery capacity. These findings are validated through real-world use cases in a large-scale semiconductor fab.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"404-412"},"PeriodicalIF":2.3,"publicationDate":"2025-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-15DOI: 10.1109/TSM.2025.3588602
Lianhao Qi;Jingyuan Mao;Xiaoyang Chang;Xiaoyang Lin;Xinhe Wang
We propose a method that enables real-time endpoint detection during plasma etching of small openings (the absolute area of the opening is at or below 5%) on a wafer. Traditional endpoint detection techniques rely on observing changes in specific wavelengths, which perform well for wafers with larger openings. However, as integrated circuit manufacturing processes continue to develop towards miniaturization, real-time endpoint detection in small opening areas remains a significant challenge. This method utilizes strategies such as hybrid noise reduction, dimensionality reduction, and interpolation to achieve real-time monitoring of etching status. First of all, a spectrometer is used to monitor chamber status in real time and provide spectral data. The wavelet threshold combined with median filtering was used to denoise the data, the SNR of the spectral signal processed by the mixed strategy increases by 37.87% compared to that of the noisy signal. What’s more, 86.96% dimensionality reduction can be achieved through the spectral data dimensionality reduction rule. Finally, an offline model was constructed using a three-time spline interpolation for the selected feature wavelengths. Compared with other strategies, the sensitivity of endpoint detection in small opening areas of the model constructed by the above algorithm is increased by 13.2%.
{"title":"Improving Endpoint Detection Sensitivity in Plasma Etching With Small Openings","authors":"Lianhao Qi;Jingyuan Mao;Xiaoyang Chang;Xiaoyang Lin;Xinhe Wang","doi":"10.1109/TSM.2025.3588602","DOIUrl":"https://doi.org/10.1109/TSM.2025.3588602","url":null,"abstract":"We propose a method that enables real-time endpoint detection during plasma etching of small openings (the absolute area of the opening is at or below 5%) on a wafer. Traditional endpoint detection techniques rely on observing changes in specific wavelengths, which perform well for wafers with larger openings. However, as integrated circuit manufacturing processes continue to develop towards miniaturization, real-time endpoint detection in small opening areas remains a significant challenge. This method utilizes strategies such as hybrid noise reduction, dimensionality reduction, and interpolation to achieve real-time monitoring of etching status. First of all, a spectrometer is used to monitor chamber status in real time and provide spectral data. The wavelet threshold combined with median filtering was used to denoise the data, the SNR of the spectral signal processed by the mixed strategy increases by 37.87% compared to that of the noisy signal. What’s more, 86.96% dimensionality reduction can be achieved through the spectral data dimensionality reduction rule. Finally, an offline model was constructed using a three-time spline interpolation for the selected feature wavelengths. Compared with other strategies, the sensitivity of endpoint detection in small opening areas of the model constructed by the above algorithm is increased by 13.2%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"717-727"},"PeriodicalIF":2.3,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-15DOI: 10.1109/TSM.2025.3589216
Yuxiang Xu;Yihui Xu;Zhichao Zhang;Jianqiang Han
While deeply etching silicon to form various microstructures with bosses or crossing splitting grooves with a V-shaped or trapezoidal cross section, the etching solution will undercut convex corners. The major problem associated with compensation structure design is the large spatial requirement around the convex corners. This paper proposes a compensation pattern to compensate the undercutting of adjacent convex corners of crossing splitting grooves. Four square masks are set at the convex corners of each chip. The twelve convex corners of four square masks are connected by six <110> oriented clamped-clamped beams. In the first stage of etching, the etching solution undercuts <110> oriented clamped-clamped beams from both sides instead of from both ends. The lateral undercutting rate of the narrow clamped-clamped beams is only 9.6% of the etching rate of the (100) plane in 80°C 25% TMAH solution. This greatly reducing the size of compensation pattern between four adjacent convex corners. Square masks are used to protect the convex corners of each chip from being etched during maskless etching the silicon wedges under clamped-clamped beams. This convex corner compensation pattern reduces the width of splitting grooves and improves the yield.
{"title":"Innovative Design of a Compensation Structure for Anisotropic Etching of Adjacent Convex Corners","authors":"Yuxiang Xu;Yihui Xu;Zhichao Zhang;Jianqiang Han","doi":"10.1109/TSM.2025.3589216","DOIUrl":"https://doi.org/10.1109/TSM.2025.3589216","url":null,"abstract":"While deeply etching silicon to form various microstructures with bosses or crossing splitting grooves with a V-shaped or trapezoidal cross section, the etching solution will undercut convex corners. The major problem associated with compensation structure design is the large spatial requirement around the convex corners. This paper proposes a compensation pattern to compensate the undercutting of adjacent convex corners of crossing splitting grooves. Four square masks are set at the convex corners of each chip. The twelve convex corners of four square masks are connected by six <110> oriented clamped-clamped beams. In the first stage of etching, the etching solution undercuts <110> oriented clamped-clamped beams from both sides instead of from both ends. The lateral undercutting rate of the narrow clamped-clamped beams is only 9.6% of the etching rate of the (100) plane in 80°C 25% TMAH solution. This greatly reducing the size of compensation pattern between four adjacent convex corners. Square masks are used to protect the convex corners of each chip from being etched during maskless etching the silicon wedges under clamped-clamped beams. This convex corner compensation pattern reduces the width of splitting grooves and improves the yield.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"687-692"},"PeriodicalIF":2.3,"publicationDate":"2025-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-10DOI: 10.1109/TSM.2025.3587715
Lee Sai Link;Mohamed Fauzi Packeer Mohamed;Tan Chan Lik
This study investigates the impact of BF${}_{2} {+}$ F co-implantation at various energies on the electrical and structural characteristics of Polysilicon resistors in MOS devices. The introduction of Fluorine effectively reduces the Polysilicon sheet resistance by 10.13% while also optimizing the Temperature Coefficient of Resistance (TCR) at higher energy implantation. A grain-boundary passivation model is used to explain the reduction in sheet resistance caused by the addition of Fluorine. This is supported by evidence of grain size enhancement and surface roughness reduction, attributed to an increased concentration of Si-F bonds as observed through FTIR analysis. Furthermore, the incorporation of Fluorine results in a decrease in Gate capacitance and an increase in Gate breakdown voltage. A novel mechanism is proposed to explain the impact of Fluorine on Gate capacitance by the formation of a low-k SiOF layer. Additionally, higher Fluorine implantation energy improves the reliability of Polysilicon resistors by mitigating sheet resistance drift under constant 40 V electrical and thermal stress at various temperatures.
{"title":"Optimizing Polysilicon Resistor Fabrication via BF2 + F Co-Implantation: A Manufacturing-Compatible Approach for Low Resistance and High Reliability in MOS Devices","authors":"Lee Sai Link;Mohamed Fauzi Packeer Mohamed;Tan Chan Lik","doi":"10.1109/TSM.2025.3587715","DOIUrl":"https://doi.org/10.1109/TSM.2025.3587715","url":null,"abstract":"This study investigates the impact of BF<inline-formula> <tex-math>${}_{2} {+}$ </tex-math></inline-formula> F co-implantation at various energies on the electrical and structural characteristics of Polysilicon resistors in MOS devices. The introduction of Fluorine effectively reduces the Polysilicon sheet resistance by 10.13% while also optimizing the Temperature Coefficient of Resistance (TCR) at higher energy implantation. A grain-boundary passivation model is used to explain the reduction in sheet resistance caused by the addition of Fluorine. This is supported by evidence of grain size enhancement and surface roughness reduction, attributed to an increased concentration of Si-F bonds as observed through FTIR analysis. Furthermore, the incorporation of Fluorine results in a decrease in Gate capacitance and an increase in Gate breakdown voltage. A novel mechanism is proposed to explain the impact of Fluorine on Gate capacitance by the formation of a low-k SiOF layer. Additionally, higher Fluorine implantation energy improves the reliability of Polysilicon resistors by mitigating sheet resistance drift under constant 40 V electrical and thermal stress at various temperatures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"709-716"},"PeriodicalIF":2.3,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the low accuracy and high false alarm rate of conventional semisupervised lithography hotspot detection models, we propose a semisupervised hotspot detection model based on dual-branch auxiliary classification comprising a classification stream, a dual-branch auxiliary classification stream, and a clustering stream. The classification stream assigns labels to input samples. The auxiliary classification stream consisting of two branches validates the classification results. Moreover, the clustering stream estimates the confidence of the sample labels. Due to the imbalance of the dataset, the model integrates a random data augmentation method to increase the hotspot samples and thus enhance model performance. Additionally, false positive rate (FPR) is used to assess model performance across all benchmarks in the ICCAD 2012 dataset. The experimental results demonstrate that our model achieves higher accuracy and a lower FPR while requiring less overall detection and simulation time across different proportions of labeled samples compared with the state-of-the-art model.
{"title":"Semisupervised Lithography Hotspot Detection Model Based on Dual-Branch Auxiliary Classification","authors":"Hui Xu;Wenxin Huang;Xinzhong Xiao;Ye Yuan;Ruijun Ma;Fuxin Tang;Pan Qi;Huaguo Liang","doi":"10.1109/TSM.2025.3586456","DOIUrl":"https://doi.org/10.1109/TSM.2025.3586456","url":null,"abstract":"Due to the low accuracy and high false alarm rate of conventional semisupervised lithography hotspot detection models, we propose a semisupervised hotspot detection model based on dual-branch auxiliary classification comprising a classification stream, a dual-branch auxiliary classification stream, and a clustering stream. The classification stream assigns labels to input samples. The auxiliary classification stream consisting of two branches validates the classification results. Moreover, the clustering stream estimates the confidence of the sample labels. Due to the imbalance of the dataset, the model integrates a random data augmentation method to increase the hotspot samples and thus enhance model performance. Additionally, false positive rate (FPR) is used to assess model performance across all benchmarks in the ICCAD 2012 dataset. The experimental results demonstrate that our model achieves higher accuracy and a lower FPR while requiring less overall detection and simulation time across different proportions of labeled samples compared with the state-of-the-art model.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"522-532"},"PeriodicalIF":2.3,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-03DOI: 10.1109/TSM.2025.3585570
Shuang Mei;Zhaolei Diao;Xingyue Liu;Guojun Wen
The advancement of integrated circuit fabrication processes has resulted in a concomitant increase in the complexity and frequency of surface defects on semiconductor wafers. This underscores the necessity for precise, real-time quality monitoring and control to enhance yield, cost-efficiency, and performance. Traditional automatic optical inspection (AOI) methods based on die-to-golden sample, die-to-die, or general deep learning-based semantic segmentation models often fail to meet these requirements due to insufficient detection accuracy, high false alarm rates, or inadequate throughput. To address these challenges, this paper proposes BDSD-Net, an efficient real-time detector that achieves state-of-the-art (SoTA) performance in wafer surface defect detection. Initially, a novel lightweight MVHNet backbone is developed, which seamlessly integrates the synergistic strengths of convolutional neural networks (CNNs) and Transformers within a ResNet-inspired architecture. Subsequently, an adaptive hybrid encoder is engineered to reduce the interference caused by intricate background patterns, thereby enhancing the accuracy of defect segmentation. This encoder includes an adaptive intra-scale feature interaction (ADFI) module that extracts more detailed high-level semantic information, and an adaptive multi-scale feature fusion (AMFF) module that effectively merges defect features across various scales. Moving away from high-complexity encoder structures, an efficient multi-scale residual fusion (EMRF) module is developed to narrow down the hypothesis space, thereby accelerating convergence. Finally, a knowledge distillation training strategy is also implemented to equip the lightweight model with the learning capabilities of more complex network models, thus enhancing its mean average precision (mAP) and frames per second (FPS) in inspection tasks. Extensive experimental results demonstrate the effectiveness of our method with data volume robustness, which achieves 88.2% and 88.9% mAP@0.5 on the semiconductor wafer and chip datasets. Moreover, compared to SoTA methods, our framework shows superior performance, achieving a compact model size of only 27 MB and a detection speed of 108.4 FPS. The demo code of this work is publicly available at https://github.com/Adiao2001/BDSD-Net/.
{"title":"BDSD-Net: An Efficient and High-Precision Anomaly Detector for Real-Time Semiconductor Wafer Vision Inspection","authors":"Shuang Mei;Zhaolei Diao;Xingyue Liu;Guojun Wen","doi":"10.1109/TSM.2025.3585570","DOIUrl":"https://doi.org/10.1109/TSM.2025.3585570","url":null,"abstract":"The advancement of integrated circuit fabrication processes has resulted in a concomitant increase in the complexity and frequency of surface defects on semiconductor wafers. This underscores the necessity for precise, real-time quality monitoring and control to enhance yield, cost-efficiency, and performance. Traditional automatic optical inspection (AOI) methods based on die-to-golden sample, die-to-die, or general deep learning-based semantic segmentation models often fail to meet these requirements due to insufficient detection accuracy, high false alarm rates, or inadequate throughput. To address these challenges, this paper proposes BDSD-Net, an efficient real-time detector that achieves state-of-the-art (SoTA) performance in wafer surface defect detection. Initially, a novel lightweight MVHNet backbone is developed, which seamlessly integrates the synergistic strengths of convolutional neural networks (CNNs) and Transformers within a ResNet-inspired architecture. Subsequently, an adaptive hybrid encoder is engineered to reduce the interference caused by intricate background patterns, thereby enhancing the accuracy of defect segmentation. This encoder includes an adaptive intra-scale feature interaction (ADFI) module that extracts more detailed high-level semantic information, and an adaptive multi-scale feature fusion (AMFF) module that effectively merges defect features across various scales. Moving away from high-complexity encoder structures, an efficient multi-scale residual fusion (EMRF) module is developed to narrow down the hypothesis space, thereby accelerating convergence. Finally, a knowledge distillation training strategy is also implemented to equip the lightweight model with the learning capabilities of more complex network models, thus enhancing its mean average precision (mAP) and frames per second (FPS) in inspection tasks. Extensive experimental results demonstrate the effectiveness of our method with data volume robustness, which achieves 88.2% and 88.9% mAP@0.5 on the semiconductor wafer and chip datasets. Moreover, compared to SoTA methods, our framework shows superior performance, achieving a compact model size of only 27 MB and a detection speed of 108.4 FPS. The demo code of this work is publicly available at <uri>https://github.com/Adiao2001/BDSD-Net/</uri>.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"675-686"},"PeriodicalIF":2.3,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-02DOI: 10.1109/TSM.2025.3584390
Max Constantin Klotzsche;Shubhada Sunil Shetti;Benjamin Lilienthal-Uhlig;Conrad Guhl
Three methods for improving planarization in a ceria free, two step STI CMP process were investigated using patterned test wafers representing 2X nm technology. It was found that within die non-uniformity (WIDNU) after bulk CMP can be improved with (1) higher oxide overburden, (2) reduced bulk polish pressure and (3) intermittent polishing by up to 15, 30 and 41% respectively. Intermittent polishing consists of alternating polish and water rinse intervals with continuous conditioning. By combining these methods up to 33% lower WIDNU is achieved post-SON, while oxide dishing for large open areas on the scale of 0.1 and 1 mm is reduced by up to 43% and 46% respectively. All three methods only require minor process changes and may help silica slurry to replace common ceria slurry in certain applications where price, particle contamination, sustainability and supply risk are the deciding factors.
{"title":"Reduced Topography After Stop on Nitride (SON) STI CMP Through Improved Post-Bulk Planarity for Diverse Layouts in Advanced Nodes","authors":"Max Constantin Klotzsche;Shubhada Sunil Shetti;Benjamin Lilienthal-Uhlig;Conrad Guhl","doi":"10.1109/TSM.2025.3584390","DOIUrl":"https://doi.org/10.1109/TSM.2025.3584390","url":null,"abstract":"Three methods for improving planarization in a ceria free, two step STI CMP process were investigated using patterned test wafers representing 2X nm technology. It was found that within die non-uniformity (WIDNU) after bulk CMP can be improved with (1) higher oxide overburden, (2) reduced bulk polish pressure and (3) intermittent polishing by up to 15, 30 and 41% respectively. Intermittent polishing consists of alternating polish and water rinse intervals with continuous conditioning. By combining these methods up to 33% lower WIDNU is achieved post-SON, while oxide dishing for large open areas on the scale of 0.1 and 1 mm is reduced by up to 43% and 46% respectively. All three methods only require minor process changes and may help silica slurry to replace common ceria slurry in certain applications where price, particle contamination, sustainability and supply risk are the deciding factors.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"659-666"},"PeriodicalIF":2.3,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11063224","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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