Pub Date : 2024-03-07DOI: 10.1109/TSM.2024.3378554
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2024.3378554","DOIUrl":"https://doi.org/10.1109/TSM.2024.3378554","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of the highly developed era of 5G, AI, and IoT, the latest generation of ICs is designed with smaller-sized FETs, lower time delays, and reduced power consumption. To address the challenges posed by these advancements, materials with a lower k value than silicon dioxide (low-k, <4.0) are being developed to reduce resistance-capacitance (RC) time delays and power consumption. While low-k materials are still emerging, various material companies continue to introduce innovative low-k products, such as SiLK, Fox, Coral, and Aurora from different companies. Simultaneously, considering proprietary business interests, the processes and materials associated with these products have not been clearly presented. In this report, we employ a novel set of equipment to validate an innovative formulation for synthesizing a low-k silicon dioxide layer. Thickness measurements confirm a higher deposition rate of silicon dioxide layers, with excellent uniformity observed on 8” wafer. Furthermore, the dielectric constant (k) decreases to 2.35, indicating the production of a great low-k material. Additionally, in the formulation of reactants, we avoid the use of silane and organic silane, contributing to improved safety in the facility and effective control of reactant costs. The results highlight an advantageous option for fabricating interconnect layers in ICs.
随着 5G、人工智能和物联网等高度发达时代的到来，最新一代集成电路的设计需要更小尺寸的 FET、更低的时间延迟和更低的功耗。为了应对这些进步带来的挑战，人们正在开发 k 值低于二氧化硅（低 k 值，<4.0）的材料，以减少电阻电容 (RC) 时间延迟和功耗。虽然低 k 值材料仍在不断涌现，但各材料公司仍在不断推出创新的低 k 值产品，如不同公司推出的 SiLK、Fox、Coral 和 Aurora。同时，考虑到专有商业利益，与这些产品相关的工艺和材料还没有得到清晰的介绍。在本报告中，我们采用了一套新型设备来验证合成低 K 值二氧化硅层的创新配方。厚度测量结果表明，二氧化硅层的沉积率更高，在 8" 晶圆上观察到了极佳的均匀性。此外，介电常数（k）降至 2.35，表明生产出了极佳的低 k 材料。此外，在反应物配方中，我们避免了硅烷和有机硅烷的使用，从而提高了设备的安全性，并有效控制了反应物成本。这些结果凸显了制造集成电路互连层的有利选择。
{"title":"Pioneering Fast and Safe Low-k Silicon Dioxide Synthesis for Modern Integrated Circuits","authors":"Yu-Ting Chow;Shou-Yen Chao;Pei-Cheng Jiang;Chung-Tzu Chang;Mei-Yuan Zheng;Mu-Chun Wang;Cheng-Hsun-Tony Chang;Chii-Ruey Lin;Chia-Fu Chen;Kuo-Wei Liu","doi":"10.1109/TSM.2024.3374067","DOIUrl":"10.1109/TSM.2024.3374067","url":null,"abstract":"With the advent of the highly developed era of 5G, AI, and IoT, the latest generation of ICs is designed with smaller-sized FETs, lower time delays, and reduced power consumption. To address the challenges posed by these advancements, materials with a lower k value than silicon dioxide (low-k, <4.0) are being developed to reduce resistance-capacitance (RC) time delays and power consumption. While low-k materials are still emerging, various material companies continue to introduce innovative low-k products, such as SiLK, Fox, Coral, and Aurora from different companies. Simultaneously, considering proprietary business interests, the processes and materials associated with these products have not been clearly presented. In this report, we employ a novel set of equipment to validate an innovative formulation for synthesizing a low-k silicon dioxide layer. Thickness measurements confirm a higher deposition rate of silicon dioxide layers, with excellent uniformity observed on 8” wafer. Furthermore, the dielectric constant (k) decreases to 2.35, indicating the production of a great low-k material. Additionally, in the formulation of reactants, we avoid the use of silane and organic silane, contributing to improved safety in the facility and effective control of reactant costs. The results highlight an advantageous option for fabricating interconnect layers in ICs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140073978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-06DOI: 10.1109/TSM.2024.3373690
Yiwen Liao;Raphaël Latty;Bin Yang
Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is typically performed by experienced human experts. However, with the fast development in semiconductor industry, test cases can contain hundreds of variables. The resulting high-dimensionality poses enormous challenges to experts. Thereby, some recent prior works have introduced data-driven variable selection algorithms to tackle these problems and achieved notable success. Nevertheless, for these methods, experts are not involved in training and inference phases, which may lead to bias and inaccuracy due to the lack of prior knowledge. Hence, this letter for the first time aims to design a novel conditional variable selection approach while keeping experts in the loop. In this way, we expect that our algorithm can be more efficiently and effectively trained to identify the most critical variables under certain expert knowledge. Extensive experiments on both synthetic and real-world datasets from industry have been conducted and shown the effectiveness of our method.
{"title":"Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation","authors":"Yiwen Liao;Raphaël Latty;Bin Yang","doi":"10.1109/TSM.2024.3373690","DOIUrl":"10.1109/TSM.2024.3373690","url":null,"abstract":"Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is typically performed by experienced human experts. However, with the fast development in semiconductor industry, test cases can contain hundreds of variables. The resulting high-dimensionality poses enormous challenges to experts. Thereby, some recent prior works have introduced data-driven variable selection algorithms to tackle these problems and achieved notable success. Nevertheless, for these methods, experts are not involved in training and inference phases, which may lead to bias and inaccuracy due to the lack of prior knowledge. Hence, this letter for the first time aims to design a novel conditional variable selection approach while keeping experts in the loop. In this way, we expect that our algorithm can be more efficiently and effectively trained to identify the most critical variables under certain expert knowledge. Extensive experiments on both synthetic and real-world datasets from industry have been conducted and shown the effectiveness of our method.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140057229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-04DOI: 10.1109/TSM.2024.3372521
Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui
In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.
{"title":"Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask","authors":"Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui","doi":"10.1109/TSM.2024.3372521","DOIUrl":"10.1109/TSM.2024.3372521","url":null,"abstract":"In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140037422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-26DOI: 10.1109/TSM.2024.3370175
Ruian Ji;Rong Chen;Lan Chen
Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process.
{"title":"A Lightweight Chip-Scale Chemical Mechanical Polishing Model Based on Polynomial Network","authors":"Ruian Ji;Rong Chen;Lan Chen","doi":"10.1109/TSM.2024.3370175","DOIUrl":"10.1109/TSM.2024.3370175","url":null,"abstract":"Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139977641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-14DOI: 10.1109/TSM.2024.3365827
Surin An;Jeong Eun Choi;Ju Eun Kang;Jiseok Lee;Sang Jeen Hong
Semiconductor industry is experiencing a rising demand for environmentally friendly processes with the emphasis on green policies and worldwide environmental sustainability. Nitrogen trifluoride (NF3), the most common plasma chamber cleaning agent gas, poses a significant concern as a potent greenhouse gas since it has global warming potential (GWP), 740 times and 6 times higher than that CO2 and N2O. This study investigated the exhaust gas using quadrupole mass spectroscopy (QMS) and analyzed the change in cleaning speed and the type of exhaust gas through plasma monitoring using optical mass spectroscopy (OES). The objective is to lower the use of the amount of NF3 gas in chamber cleaning process to partially contribute the environmental sustainability in the point of semiconductor manufacturing. When a small amount of N2 was added to NF3 whose ratio of 7:23, the cleaning efficiency reached to 90% compared to NF3 gas alone. Addition of N2 positively affected electron density and temperature to increase the F-radical in remote plasma system. In conclusion, 18% of NF3 usage amount was reduced during the Sio2 deposition chamber cleaning process.
{"title":"Eco-Friendly Dry-Cleaning and Diagnostics of Silicon Dioxide Deposition Chamber","authors":"Surin An;Jeong Eun Choi;Ju Eun Kang;Jiseok Lee;Sang Jeen Hong","doi":"10.1109/TSM.2024.3365827","DOIUrl":"10.1109/TSM.2024.3365827","url":null,"abstract":"Semiconductor industry is experiencing a rising demand for environmentally friendly processes with the emphasis on green policies and worldwide environmental sustainability. Nitrogen trifluoride (NF3), the most common plasma chamber cleaning agent gas, poses a significant concern as a potent greenhouse gas since it has global warming potential (GWP), 740 times and 6 times higher than that CO2 and N2O. This study investigated the exhaust gas using quadrupole mass spectroscopy (QMS) and analyzed the change in cleaning speed and the type of exhaust gas through plasma monitoring using optical mass spectroscopy (OES). The objective is to lower the use of the amount of NF3 gas in chamber cleaning process to partially contribute the environmental sustainability in the point of semiconductor manufacturing. When a small amount of N2 was added to NF3 whose ratio of 7:23, the cleaning efficiency reached to 90% compared to NF3 gas alone. Addition of N2 positively affected electron density and temperature to increase the F-radical in remote plasma system. In conclusion, 18% of NF3 usage amount was reduced during the Sio2 deposition chamber cleaning process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139954668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs.
{"title":"Curvilinear Standard Cell Design for Semiconductor Manufacturing","authors":"Ryoung-Han Kim;Soobin Hwang;Apoorva Oak;Yasser Shirazi;Hsinlan Chang;Kiho Yang;Gioele Mirabelli","doi":"10.1109/TSM.2024.3362900","DOIUrl":"10.1109/TSM.2024.3362900","url":null,"abstract":"Curvilinear design was applied to standard cell layout to improve electrical characteristics and reduce manufacturing costs. Its implementation was intelligently co-optimized with 1-D Manhattan shapes and photolithography process to preserve the standard cell area equivalent to that of 1-D Manhattan-only designs. B-spline curve representation was employed to realize the curvilinear design. Curvilinear pathfinding was carried out through the Voronoi diagram to find the optimum routing path, and the A* routing algorithm to determine the shortest path. In the curvilinear-designed standard cells, the majority of standard cells exhibited reduced total metal length, decreased number of vias, and eliminated the need for an extra metal layer when compared to 1-D Manhattan-only standard cell designs. Manufacturability of curvilinear designs was evaluated, and potential solutions are proposed in the context of design rule, design rules check (DRC) and optical proximity correction (OPC). DRC and OPC were carried out within the currently employed electronic design automation (EDA) tools to verify the curvilinear designs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139945816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-05DOI: 10.1109/TSM.2023.3334414
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2023.3334414","DOIUrl":"https://doi.org/10.1109/TSM.2023.3334414","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10419383","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139694970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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