Pub Date : 2024-11-22DOI: 10.1109/TSM.2024.3504213
{"title":"TechRxiv: Share Your Preprint Research With the World!","authors":"","doi":"10.1109/TSM.2024.3504213","DOIUrl":"https://doi.org/10.1109/TSM.2024.3504213","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"648-648"},"PeriodicalIF":2.3,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10766042","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/TSM.2024.3492173
Pin-Yen Liao;Tee Lin;Omid Ali Zargar;Jhang-Kun Li;Yang-Cheng Shih;Shih-Cheng Hu;Graham Leggett
recent developments in semiconductor manufacturing have seen feature sizes reduce to as small as 3 nm. It is predicted that 2 nm, or even 1 nanometer will be achieved soon. Improving the level of cleanliness of the wafer mask during manufacturing can lead to improved product yield and quality. The quality of lithography technology and the reticle is one of the most important items in the wafer manufacturing process. The cleanliness of this process directly affects the wafer quality and yield. Because the wafer manufacturing process involves the stacking of multiple reticles through lithography technology, semiconductor factories mostly use a reticle stocker room to store the photomasks. However, the reticle is susceptible to defects caused by moisture, particles, and molecular contaminants in the air. Therefore, the reticle stocker room environment requires high cleanliness and humidity control. In this study, the flow stream lines, velocity and humidity fields associated with a flow isolation device (FID) installed in a reticle stocker room were analyzed with the assistance of computational fluid dynamics (CFD) software developed by ANSYS Fluent. Different velocity (V=1 m/s, 1.5 m/s, 2 m/s) of the flow isolation device were examined. The results show that under the same velocity (V=1 m/s), the wider the outlet width of the flow isolation device (W ${=}0$ .2 m), the higher the isolation efficiency ($eta {=}83.9$ %). The results also show that the faster the velocity of the flow isolation device (V =2 m/s), the better the isolation efficiency ($eta {=}88.2$ %) under the same outlet width (W ${=}0$ .1 m). The use of the flow isolation device can effectively reduce the supply of clean dry air (CDA) by up to 40%, greatly reducing energy consumption during semiconductor manufacturing. According to the results of this study, when using both a hollow fiber adsorption dryer and a flow isolation device with a width of 0.1 m and an outlet wind speed of 2 m/s, it can save 118,514 kWh per year, and its energy saving rate is 92.03%.
{"title":"Prevention of Moisture Invasion by Flow Isolation Device (FID) for Mask Automatic Storage System (Stocker Room) in a Semiconductor Fabrication Plant (Fab)","authors":"Pin-Yen Liao;Tee Lin;Omid Ali Zargar;Jhang-Kun Li;Yang-Cheng Shih;Shih-Cheng Hu;Graham Leggett","doi":"10.1109/TSM.2024.3492173","DOIUrl":"https://doi.org/10.1109/TSM.2024.3492173","url":null,"abstract":"recent developments in semiconductor manufacturing have seen feature sizes reduce to as small as 3 nm. It is predicted that 2 nm, or even 1 nanometer will be achieved soon. Improving the level of cleanliness of the wafer mask during manufacturing can lead to improved product yield and quality. The quality of lithography technology and the reticle is one of the most important items in the wafer manufacturing process. The cleanliness of this process directly affects the wafer quality and yield. Because the wafer manufacturing process involves the stacking of multiple reticles through lithography technology, semiconductor factories mostly use a reticle stocker room to store the photomasks. However, the reticle is susceptible to defects caused by moisture, particles, and molecular contaminants in the air. Therefore, the reticle stocker room environment requires high cleanliness and humidity control. In this study, the flow stream lines, velocity and humidity fields associated with a flow isolation device (FID) installed in a reticle stocker room were analyzed with the assistance of computational fluid dynamics (CFD) software developed by ANSYS Fluent. Different velocity (V=1 m/s, 1.5 m/s, 2 m/s) of the flow isolation device were examined. The results show that under the same velocity (V=1 m/s), the wider the outlet width of the flow isolation device (W <inline-formula> <tex-math>${=}0$ </tex-math></inline-formula>.2 m), the higher the isolation efficiency (<inline-formula> <tex-math>$eta {=}83.9$ </tex-math></inline-formula>%). The results also show that the faster the velocity of the flow isolation device (V =2 m/s), the better the isolation efficiency (<inline-formula> <tex-math>$eta {=}88.2$ </tex-math></inline-formula>%) under the same outlet width (W <inline-formula> <tex-math>${=}0$ </tex-math></inline-formula>.1 m). The use of the flow isolation device can effectively reduce the supply of clean dry air (CDA) by up to 40%, greatly reducing energy consumption during semiconductor manufacturing. According to the results of this study, when using both a hollow fiber adsorption dryer and a flow isolation device with a width of 0.1 m and an outlet wind speed of 2 m/s, it can save 118,514 kWh per year, and its energy saving rate is 92.03%.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"57-64"},"PeriodicalIF":2.3,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-05DOI: 10.1109/TSM.2024.3483781
Zhao Hong;Chew Ze Yong;Kosasih Lucky;Goh Jun Rong;Wang Joheng
The semiconductor industry faces increasing pressure to improve energy efficiency while maintaining competitiveness and sustainability. Apart from more conventional energy efficiency measures look at equipment modernization and process and design optimization, this paper explores the potential of data-driven approaches to address these challenges and optimize energy consumption across both the facility and manufacturing space of a semiconductor manufacture plant. By harnessing advanced analytics, machine learning algorithms, and IoT technologies, semiconductor manufacturers can gain real-time insights into energy usage patterns, and identify areas of opportunities that leads to the implementation of targeted interventions to optimize performance. The paper first looks into the challenges and measures of enabling and enhancing data visibility which is the foundation of the data-driven approach, then it examines case studies, best practices and various systematic approaches, demonstrating the transformative impact of data-driven energy efficiency measures which leads to operational efficiency, cost reduction, and environmental sustainability. Ultimately, this paper aims to provide a fresh angle into the energy efficiency study for peers in semiconductor industries to leverage in their journey towards a more sustainable and energy efficient future.
{"title":"A Data-Driven Approach for Improving Energy Efficiency in a Semiconductor Manufacturing Plant","authors":"Zhao Hong;Chew Ze Yong;Kosasih Lucky;Goh Jun Rong;Wang Joheng","doi":"10.1109/TSM.2024.3483781","DOIUrl":"https://doi.org/10.1109/TSM.2024.3483781","url":null,"abstract":"The semiconductor industry faces increasing pressure to improve energy efficiency while maintaining competitiveness and sustainability. Apart from more conventional energy efficiency measures look at equipment modernization and process and design optimization, this paper explores the potential of data-driven approaches to address these challenges and optimize energy consumption across both the facility and manufacturing space of a semiconductor manufacture plant. By harnessing advanced analytics, machine learning algorithms, and IoT technologies, semiconductor manufacturers can gain real-time insights into energy usage patterns, and identify areas of opportunities that leads to the implementation of targeted interventions to optimize performance. The paper first looks into the challenges and measures of enabling and enhancing data visibility which is the foundation of the data-driven approach, then it examines case studies, best practices and various systematic approaches, demonstrating the transformative impact of data-driven energy efficiency measures which leads to operational efficiency, cost reduction, and environmental sustainability. Ultimately, this paper aims to provide a fresh angle into the energy efficiency study for peers in semiconductor industries to leverage in their journey towards a more sustainable and energy efficient future.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"475-480"},"PeriodicalIF":2.3,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10742890","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Typical defects on unpatterned wafers include particles, residues, scratches, and cracks. Various dark-field scattering methods have been applied to detect unpatterned wafer surface defects. However, these methods have only one optical detection channel, making handling multiple types of wafer defects difficult. In response, the theory of multimodal defect inspection is improved, and a multimodal spot-scanning imaging system is developed. The laser beam is focused on the wafer surface, generating micron-level high-intensity focused spot illumination. Scattered light from the wafer surface is collected by the dark-field objective, and the intensity is measured by the photodiode. Reflected light from the wafer surface is collected by the bright-field objective. After polarization splitting, it is measured by two four-quadrant detectors to analyze the topography, film, and reflected signal. The turntable and linear guide drive the optical head and wafer, allowing the focused spot to scan along the wafer in a spiral trajectory, enabling fast and accurate detection. The defect inspection system has been verified through experiments. The minimum detectable PSL particle size is less than 200 nm, the minimum detectable scratch width is less than $1~mu $ m, and the minimum detectable stain width is less than $20~mu $ m.
{"title":"Characterization of Multimodal Spot Scanning Imaging System for Wafer Defect Inspection","authors":"Zuoda Zhou;Haiyan Luo;Wei Xiong;Dingjun Qu;Ruizhe Ding;Zhiwei Li;Wei Jin;Yu Ru;Shihao Jia;Jin Hong","doi":"10.1109/TSM.2024.3481291","DOIUrl":"https://doi.org/10.1109/TSM.2024.3481291","url":null,"abstract":"Typical defects on unpatterned wafers include particles, residues, scratches, and cracks. Various dark-field scattering methods have been applied to detect unpatterned wafer surface defects. However, these methods have only one optical detection channel, making handling multiple types of wafer defects difficult. In response, the theory of multimodal defect inspection is improved, and a multimodal spot-scanning imaging system is developed. The laser beam is focused on the wafer surface, generating micron-level high-intensity focused spot illumination. Scattered light from the wafer surface is collected by the dark-field objective, and the intensity is measured by the photodiode. Reflected light from the wafer surface is collected by the bright-field objective. After polarization splitting, it is measured by two four-quadrant detectors to analyze the topography, film, and reflected signal. The turntable and linear guide drive the optical head and wafer, allowing the focused spot to scan along the wafer in a spiral trajectory, enabling fast and accurate detection. The defect inspection system has been verified through experiments. The minimum detectable PSL particle size is less than 200 nm, the minimum detectable scratch width is less than <inline-formula> <tex-math>$1~mu $ </tex-math></inline-formula>m, and the minimum detectable stain width is less than <inline-formula> <tex-math>$20~mu $ </tex-math></inline-formula>m.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"4-11"},"PeriodicalIF":2.3,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143489096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tin chloride pentahydrate (SnCl ${_{{4}}} cdot 5$ H2O) is used as the dopant precursor to form the n-type $alpha $ -Ga2O3 in this study. The X-ray diffraction (XRD) and high-resolution transmission electron microscope (HR-TEM) confirm that the single-crystalline $alpha $ -Ga2O3:SnCl ${_{{4}}} cdot 5$ H2O epi-layer was grown on the r-plane sapphire substrate using mist chemical vapor deposition (mist-CVD). When the Sn doping atomic concentrations are the same, the electron concentration of $alpha $ -Ga2O3:SnCl ${_{{4}}} cdot 5$ H2O is higher than that of $alpha $ -Ga2O3:SnCl ${_{{2}}} cdot 2$ H2O. The lower thermal decomposition temperature and lower residues of $alpha $ -Ga2O3:SnCl ${_{{4}}} cdot 5$ H2O are confirmed in thermogravimetric (TGA) analysis. Sn $3d_{5/2}$ binding energy spectra observed by X-ray photoelectron spectroscopy (XPS) show that SnCl ${_{{4}}} cdot 5$ H2O provides more $Sn^{4+}$ than SnCl ${_{{2}}} cdot 2$ H2O. The specific contact resistivity of $alpha $ -Ga2O3:SnCl ${_{{4}}} cdot 5$ H2O reaches $1.62times 10{^{-}5 }~Omega $ -cm2 with $10^{20}$ cm $^{-}3 $ Sn doping concentration. Moreover, the power figure-of-merit (PFoM) of $alpha $ -Ga2O3:SnCl ${_{{4}}} cdot 5$ H2O-based lateral Schottky barrier diode (SBD) is 0.356 GW/cm2 which is comparable to $beta $ -Ga2O3-based SBD.
{"title":"Improving Doping Efficiency of Mist-CVD Epitaxy for Tin-Doped α-Ga₂O₃ Using Tin Chloride Pentahydrate","authors":"Han-Yin Liu;Yun-Yun Cheng;Wei-Han Chen;Ko-Fan Hu;Nei-En Chiu","doi":"10.1109/TSM.2024.3475730","DOIUrl":"https://doi.org/10.1109/TSM.2024.3475730","url":null,"abstract":"Tin chloride pentahydrate (SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O) is used as the dopant precursor to form the n-type \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3 in this study. The X-ray diffraction (XRD) and high-resolution transmission electron microscope (HR-TEM) confirm that the single-crystalline \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O epi-layer was grown on the r-plane sapphire substrate using mist chemical vapor deposition (mist-CVD). When the Sn doping atomic concentrations are the same, the electron concentration of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O is higher than that of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{2}}} cdot 2$ </tex-math></inline-formula>\u0000 H2O. The lower thermal decomposition temperature and lower residues of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O are confirmed in thermogravimetric (TGA) analysis. Sn \u0000<inline-formula> <tex-math>$3d_{5/2}$ </tex-math></inline-formula>\u0000 binding energy spectra observed by X-ray photoelectron spectroscopy (XPS) show that SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O provides more \u0000<inline-formula> <tex-math>$Sn^{4+}$ </tex-math></inline-formula>\u0000 than SnCl\u0000<inline-formula> <tex-math>${_{{2}}} cdot 2$ </tex-math></inline-formula>\u0000 H2O. The specific contact resistivity of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O reaches \u0000<inline-formula> <tex-math>$1.62times 10{^{-}5 }~Omega $ </tex-math></inline-formula>\u0000-cm2 with \u0000<inline-formula> <tex-math>$10^{20}$ </tex-math></inline-formula>\u0000 cm\u0000<inline-formula> <tex-math>$^{-}3 $ </tex-math></inline-formula>\u0000 Sn doping concentration. Moreover, the power figure-of-merit (PFoM) of \u0000<inline-formula> <tex-math>$alpha $ </tex-math></inline-formula>\u0000-Ga2O3:SnCl\u0000<inline-formula> <tex-math>${_{{4}}} cdot 5$ </tex-math></inline-formula>\u0000 H2O-based lateral Schottky barrier diode (SBD) is 0.356 GW/cm2 which is comparable to \u0000<inline-formula> <tex-math>$beta $ </tex-math></inline-formula>\u0000-Ga2O3-based SBD.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"629-633"},"PeriodicalIF":2.3,"publicationDate":"2024-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The front opening unified pod (FOUP) is a carrier that transports multiple wafers as it moves between numerous processing facilities. It is inevitably exposed to air humidity coming from the equipment front end module (EFEM), which leads to the formation of harmful residual particles on the wafer surfaces due to the reaction of moisture with airborne molecular contamination (AMC). This can cause serious defects, and thus there is a need to understand the complex flow structure inside the EFEM and FOUP. Magnetic resonance velocimetry (MRV) is hereby employed to qualitatively and quantitatively measure the 3D flow when conventional load port purge (LPP) is utilized to protect the wafers. The front LPP forms a barrier between the FOUP and EFEM, blocking the EFEM flow from entering the FOUP. Additionally, at the rear of the FOUP, flow from the rear and front LPP collide and then travels between the wafers toward the FOUP entrance, thereby protecting the wafers. Using computational fluid dynamic (CFD) simulations, various combinations of flow rates from different purge ports were simulated, leading to an optimal flow condition. These findings suggest that independent control of the flow rates can be a practical way to protect the wafers from defects.
{"title":"Quantitative 3-D Flow Visualization of Conventional Purge Flow Within a Front Opening Unified Pod (FOUP)","authors":"Sung-Gwang Lee;Juhan Bae;Hoomi Choi;Jaein Jeong;Youngjeong Kim;Wontae Hwang","doi":"10.1109/TSM.2024.3473868","DOIUrl":"https://doi.org/10.1109/TSM.2024.3473868","url":null,"abstract":"The front opening unified pod (FOUP) is a carrier that transports multiple wafers as it moves between numerous processing facilities. It is inevitably exposed to air humidity coming from the equipment front end module (EFEM), which leads to the formation of harmful residual particles on the wafer surfaces due to the reaction of moisture with airborne molecular contamination (AMC). This can cause serious defects, and thus there is a need to understand the complex flow structure inside the EFEM and FOUP. Magnetic resonance velocimetry (MRV) is hereby employed to qualitatively and quantitatively measure the 3D flow when conventional load port purge (LPP) is utilized to protect the wafers. The front LPP forms a barrier between the FOUP and EFEM, blocking the EFEM flow from entering the FOUP. Additionally, at the rear of the FOUP, flow from the rear and front LPP collide and then travels between the wafers toward the FOUP entrance, thereby protecting the wafers. Using computational fluid dynamic (CFD) simulations, various combinations of flow rates from different purge ports were simulated, leading to an optimal flow condition. These findings suggest that independent control of the flow rates can be a practical way to protect the wafers from defects.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"620-628"},"PeriodicalIF":2.3,"publicationDate":"2024-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TSM.2024.3472611
Yuanfu Yang;Min Sun
In semiconductor manufacturing, defect detection is pivotal for enhancing productivity and yield. This paper introduces a novel weakly supervised method, the Implicit Cross Domain Diffusion Model (ICDDM), designed to tackle defect pattern segmentation challenges in the absence of detailed pixel-wise annotations. ICDDM employs a generative model to estimate the joint distribution of images depicting defect patterns and background circuits, formulating this estimation as a Markov Chain and optimizing it through denoising score matching. Building on this, we propose the Cross Domain Latent Diffusion Model (CDLDM), inspired by the Latent Diffusion Model, which simplifies the diffusion process into a lower-dimensional latent space to boost detection efficiency. Further enhancing our model, we introduce the Knowledge Distillation Cross Domain Diffusion Model (KDCDDM), which utilizes CDLDM as a teacher model and a Generative Adversarial Network (GAN) as a student model. This approach significantly accelerates the diffusion process by reducing the number of necessary denoising iterations while maintaining robust model performance. This suite of techniques offers a comprehensive solution for efficient and effective defect detection in semiconductor production environments.
{"title":"Knowledge Distillation Cross Domain Diffusion Model: A Generative AI Approach for Defect Pattern Segmentation","authors":"Yuanfu Yang;Min Sun","doi":"10.1109/TSM.2024.3472611","DOIUrl":"https://doi.org/10.1109/TSM.2024.3472611","url":null,"abstract":"In semiconductor manufacturing, defect detection is pivotal for enhancing productivity and yield. This paper introduces a novel weakly supervised method, the Implicit Cross Domain Diffusion Model (ICDDM), designed to tackle defect pattern segmentation challenges in the absence of detailed pixel-wise annotations. ICDDM employs a generative model to estimate the joint distribution of images depicting defect patterns and background circuits, formulating this estimation as a Markov Chain and optimizing it through denoising score matching. Building on this, we propose the Cross Domain Latent Diffusion Model (CDLDM), inspired by the Latent Diffusion Model, which simplifies the diffusion process into a lower-dimensional latent space to boost detection efficiency. Further enhancing our model, we introduce the Knowledge Distillation Cross Domain Diffusion Model (KDCDDM), which utilizes CDLDM as a teacher model and a Generative Adversarial Network (GAN) as a student model. This approach significantly accelerates the diffusion process by reducing the number of necessary denoising iterations while maintaining robust model performance. This suite of techniques offers a comprehensive solution for efficient and effective defect detection in semiconductor production environments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"634-642"},"PeriodicalIF":2.3,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-01DOI: 10.1109/TSM.2024.3471635
Jingxian Wei;Chenyu Xu;Sihai Zhang
As the technology node in semiconductor manufacturing continuously shrinks, the etch-induced etch bias introduced during the etching process cannot be ignored and necessitates correction. The prevailing approach to addressing this issue is model-based etch bias correction. This method involves simulating the etching process by training an etch model that predicts the bias between the After Development Inspection (ADI) contour and the After Etch Inspection (AEI) contour. However, the reliability of the etch data for model training is compromised due to pattern shrinkage during Scanning Electron Microscope (SEM) imaging, which impairs the model’s prediction accuracy. To mitigate these issues, the contour averaging method is frequently employed, although it lacks thorough theoretical explanation and experimental verification. In this study, we validate the effectiveness of contour averaging theoretically and empirically. A relationship is derived between the prediction error of the etch model and the number of averaged contours, showing that contour averaging minimizes measurement errors of etch data. We also demonstrate the improved prediction accuracy of etch model using contour averaging, with both real and generated etch data.
{"title":"Why Contour Averaging Works for SEM Metrology: Analysis and Validation","authors":"Jingxian Wei;Chenyu Xu;Sihai Zhang","doi":"10.1109/TSM.2024.3471635","DOIUrl":"https://doi.org/10.1109/TSM.2024.3471635","url":null,"abstract":"As the technology node in semiconductor manufacturing continuously shrinks, the etch-induced etch bias introduced during the etching process cannot be ignored and necessitates correction. The prevailing approach to addressing this issue is model-based etch bias correction. This method involves simulating the etching process by training an etch model that predicts the bias between the After Development Inspection (ADI) contour and the After Etch Inspection (AEI) contour. However, the reliability of the etch data for model training is compromised due to pattern shrinkage during Scanning Electron Microscope (SEM) imaging, which impairs the model’s prediction accuracy. To mitigate these issues, the contour averaging method is frequently employed, although it lacks thorough theoretical explanation and experimental verification. In this study, we validate the effectiveness of contour averaging theoretically and empirically. A relationship is derived between the prediction error of the etch model and the number of averaged contours, showing that contour averaging minimizes measurement errors of etch data. We also demonstrate the improved prediction accuracy of etch model using contour averaging, with both real and generated etch data.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"535-541"},"PeriodicalIF":2.3,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：