Pub Date : 2025-06-27DOI: 10.1109/TSM.2025.3583925
Soumen Kar;Nicholas W. Gangi;Katrina A. Morgan;Lewis G. Carpenter;Nicholas M. Fahrenkopf;Yukta Timalsina;Christopher V. Baiocco;David Harame
This work evaluates thick silicon nitride (SiN) film properties using various inline and offline advanced metrology data analysis. The thick SiN films for photonic applications are typically prepared by plasma-enhanced chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD) techniques. Our present study combines high-volume inline and high-accuracy offline metrology to best characterize our thick SiN films. The developed SiN film compositional analysis has been carried out using inline X-ray photoelectron spectroscopy (XPS) to get fast feedback on the composition and contamination of the film surface. Finally, we present a refractive index (n) comparison for annealed and unannealed PECVD/LPCVD wafers.
{"title":"Evaluation of Thick Silicon Nitride Film Properties at 300 mm Scale for High-Q Photonic Devices","authors":"Soumen Kar;Nicholas W. Gangi;Katrina A. Morgan;Lewis G. Carpenter;Nicholas M. Fahrenkopf;Yukta Timalsina;Christopher V. Baiocco;David Harame","doi":"10.1109/TSM.2025.3583925","DOIUrl":"https://doi.org/10.1109/TSM.2025.3583925","url":null,"abstract":"This work evaluates thick silicon nitride (SiN) film properties using various inline and offline advanced metrology data analysis. The thick SiN films for photonic applications are typically prepared by plasma-enhanced chemical vapor deposition (PECVD) and low-pressure chemical vapor deposition (LPCVD) techniques. Our present study combines high-volume inline and high-accuracy offline metrology to best characterize our thick SiN films. The developed SiN film compositional analysis has been carried out using inline X-ray photoelectron spectroscopy (XPS) to get fast feedback on the composition and contamination of the film surface. Finally, we present a refractive index (n) comparison for annealed and unannealed PECVD/LPCVD wafers.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"420-427"},"PeriodicalIF":2.3,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-23DOI: 10.1109/TSM.2025.3582194
Christina L. Lau;Shuhan Ding;Yutong Xie;Edwin R. Law;Bahar Kor;Benyamin Davaji;Amit Lal;Peter C. Doerschuk
Computer representations of the structure, context, and behavior of physical systems are critical components of computational system optimization. Traditionally, such optimization is done by iterative physical experiments, which can be expensive both in time and resources. In this paper, these computer representations, called digital twins, are developed primarily using SEM images and equipment process parameters. HyperPix2Pix, the proposed methodology of the digital twins, is a deep neural network that uses SEM images of the input structure together with equipment process parameters to predict the output SEM images. We demonstrate HyperPix2Pix on a DUV photolithography stepper and plasma etcher. HyperPix2Pix predicts output images that closely match the experimental output images and have very similar critical dimensions. Compared to previous work, HyperPix2Pix includes the effects of process parameters through multimodal learning, elucidating the role of different parameters in nanofabrication processes and their effects on critical dimensions of the resulting structures.
{"title":"Process-Aware Digital Twins by Deep Learning for DUV Photolithography and Plasma Etch","authors":"Christina L. Lau;Shuhan Ding;Yutong Xie;Edwin R. Law;Bahar Kor;Benyamin Davaji;Amit Lal;Peter C. Doerschuk","doi":"10.1109/TSM.2025.3582194","DOIUrl":"https://doi.org/10.1109/TSM.2025.3582194","url":null,"abstract":"Computer representations of the structure, context, and behavior of physical systems are critical components of computational system optimization. Traditionally, such optimization is done by iterative physical experiments, which can be expensive both in time and resources. In this paper, these computer representations, called digital twins, are developed primarily using SEM images and equipment process parameters. HyperPix2Pix, the proposed methodology of the digital twins, is a deep neural network that uses SEM images of the input structure together with equipment process parameters to predict the output SEM images. We demonstrate HyperPix2Pix on a DUV photolithography stepper and plasma etcher. HyperPix2Pix predicts output images that closely match the experimental output images and have very similar critical dimensions. Compared to previous work, HyperPix2Pix includes the effects of process parameters through multimodal learning, elucidating the role of different parameters in nanofabrication processes and their effects on critical dimensions of the resulting structures.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"634-641"},"PeriodicalIF":2.3,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-23DOI: 10.1109/TSM.2025.3581909
Qian Yue;Chen Lan
The planarization of chip surfaces after chemical mechanical planarization (CMP) is becoming increasingly crucial as it can lead to problems such as depth of focus (DOF), voltage drop (IR drop), timing closure and electromigration (EM) problems. To enhance production yield, the industry requires an accurate CMP model to detect, localize, and control topography nonuniformity caused by layout dependent effects (LDE) prior to fabrication. However, existing semi-physical models heavily rely on manually specified empirical relationships during the calibration process, limiting their ability to meet the demands of advanced process nodes in terms of automated model construction and prediction accuracy. To address this limitation, we propose to construct empirical relationships in semi-physical models using embedded neural networks. Building upon this concept, we have developed a deep-learning-assisted semi-physical CMP model that eliminates the need for manual specification of empirical relationships. Experimentation conducted on silicon data from test chips across the process nodes of 28/32/40 nm highlights the advantages of our model, including rapid training (requiring fewer than 400 epochs), automated deployment and competitive prediction accuracy compared to data-driven models (RMSE reduction for dishing (18%/79%/55%) and erosion (25%/58%/61%) over traditional semi-physical models).
{"title":"Automated Construction of Semi-Physical CMP Models via Embedded Neural Networks","authors":"Qian Yue;Chen Lan","doi":"10.1109/TSM.2025.3581909","DOIUrl":"https://doi.org/10.1109/TSM.2025.3581909","url":null,"abstract":"The planarization of chip surfaces after chemical mechanical planarization (CMP) is becoming increasingly crucial as it can lead to problems such as depth of focus (DOF), voltage drop (IR drop), timing closure and electromigration (EM) problems. To enhance production yield, the industry requires an accurate CMP model to detect, localize, and control topography nonuniformity caused by layout dependent effects (LDE) prior to fabrication. However, existing semi-physical models heavily rely on manually specified empirical relationships during the calibration process, limiting their ability to meet the demands of advanced process nodes in terms of automated model construction and prediction accuracy. To address this limitation, we propose to construct empirical relationships in semi-physical models using embedded neural networks. Building upon this concept, we have developed a deep-learning-assisted semi-physical CMP model that eliminates the need for manual specification of empirical relationships. Experimentation conducted on silicon data from test chips across the process nodes of 28/32/40 nm highlights the advantages of our model, including rapid training (requiring fewer than 400 epochs), automated deployment and competitive prediction accuracy compared to data-driven models (RMSE reduction for dishing (18%/79%/55%) and erosion (25%/58%/61%) over traditional semi-physical models).","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"533-542"},"PeriodicalIF":2.3,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the process of Nch silicon MOSFET, BPSG is generally used as an interlayer film. BPSG has the purpose of gettering mobile ions and reflowing the BPSG film by annealing to reduce the steps on the wafer surface. This annealing process also activates the p+ diffusion layer. However, because the annealing temperature at which BPSG is reflowed is high, phosphorus oxide diffuses outward from the BPSG film and penetrates into the contact part. If the contact resistance increases, a serious problem occurs in which the avalanche capability decreases. We have devised two countermeasures to this problem and verified them through experiments. By changing the annealing conditions and increasing the titanium thickness, we were able to reduce the p+ contact resistance by 3 to 4 orders of magnitude and confirmed an improvement in avalanche capability. These countermeasures can be used universally by adjusting them even if the annealing condition changes.
{"title":"Avalanche Capability Improvement by Optimizing p+ Contact Resistance for N-Channel Trench Power MOSFETs","authors":"Keisuke Miyamoto;Daichi Ishi;Hiroyuki Kishimoto;Kazuyuki Sato;Tsuyoshi Kachi;Hiroaki Kato","doi":"10.1109/TSM.2025.3581170","DOIUrl":"https://doi.org/10.1109/TSM.2025.3581170","url":null,"abstract":"In the process of Nch silicon MOSFET, BPSG is generally used as an interlayer film. BPSG has the purpose of gettering mobile ions and reflowing the BPSG film by annealing to reduce the steps on the wafer surface. This annealing process also activates the p+ diffusion layer. However, because the annealing temperature at which BPSG is reflowed is high, phosphorus oxide diffuses outward from the BPSG film and penetrates into the contact part. If the contact resistance increases, a serious problem occurs in which the avalanche capability decreases. We have devised two countermeasures to this problem and verified them through experiments. By changing the annealing conditions and increasing the titanium thickness, we were able to reduce the p+ contact resistance by 3 to 4 orders of magnitude and confirmed an improvement in avalanche capability. These countermeasures can be used universally by adjusting them even if the annealing condition changes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"453-458"},"PeriodicalIF":2.3,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-16DOI: 10.1109/TSM.2025.3579970
Hsin-Tzu Hsu;Shi-Chung Chang
Dynamic Machine Allocation (DMA) is a vital aspect of production scheduling in semiconductor manufacturing. Current DMA practices heavily rely on engineers’ domain expertise and require a few days of manual adjustments in response to rapid but significant fab changes, for example, due to unfamiliar economic shifts. Slow and heuristic DMA policy adaptation very often leads to production shortfalls. To reduce dependence on human expertise and speed up quality responses to changes, we design a framework of effective deep reinforcement learning (DRL) for DMA. Design innovations of the framework include (1) a discrete-event simulator for predicting production flows among machines with state, DMA action and reward aligned to fab practices; (2) a DRL neural network output transformation module that ensures action feasibility in task compatibility and machine availability; and (3) a DRL-based, two-stage agent of DMA policy learning that integrates DRL with optimization techniques for both efficient computation and quality DMA. Operation simulation by using the DMA case and data of a metal sputtering machine group demonstrates that our DRL-based design effectively learns DMA policies in different scenarios, each within one hour. In throughput performance, learned policies surpass a traditional heuristic by 3% to 20%. Our framework and the DRL-based method designs are generic and applicable to DMA of various machine groups.
{"title":"Effective Deep Reinforcement Learning for Dynamic Machine Allocation: A Case Study on Metal Sputtering Tools","authors":"Hsin-Tzu Hsu;Shi-Chung Chang","doi":"10.1109/TSM.2025.3579970","DOIUrl":"https://doi.org/10.1109/TSM.2025.3579970","url":null,"abstract":"Dynamic Machine Allocation (DMA) is a vital aspect of production scheduling in semiconductor manufacturing. Current DMA practices heavily rely on engineers’ domain expertise and require a few days of manual adjustments in response to rapid but significant fab changes, for example, due to unfamiliar economic shifts. Slow and heuristic DMA policy adaptation very often leads to production shortfalls. To reduce dependence on human expertise and speed up quality responses to changes, we design a framework of effective deep reinforcement learning (DRL) for DMA. Design innovations of the framework include (1) a discrete-event simulator for predicting production flows among machines with state, DMA action and reward aligned to fab practices; (2) a DRL neural network output transformation module that ensures action feasibility in task compatibility and machine availability; and (3) a DRL-based, two-stage agent of DMA policy learning that integrates DRL with optimization techniques for both efficient computation and quality DMA. Operation simulation by using the DMA case and data of a metal sputtering machine group demonstrates that our DRL-based design effectively learns DMA policies in different scenarios, each within one hour. In throughput performance, learned policies surpass a traditional heuristic by 3% to 20%. Our framework and the DRL-based method designs are generic and applicable to DMA of various machine groups.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"430-438"},"PeriodicalIF":2.3,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, we examined a digital twin model that has multiple processes. Generally, previous processes affect subsequent processes in the semiconductor manufacturing process. Therefore, to construct reusable modular models, the mutual influences between processes should be defined and concisely represented. We built a digital twin model involving the post-annealing and wet etching of an oxide film formed by atomic layer deposition (ALD), as a case study. We developed a modular model that separated processes based on intermediate variables extracted through physical analysis. The high coefficient of determination obtained from the prediction results suggests that these intermediate variables sufficiently captured the effect of the preceding processes. Further, we explored concepts for improving model reusability using class structure analysis within an object-oriented programming (OOP) framework. We observed the need for encapsulating physics-based intermediate variables within appropriate classes to separate process- and device-specific descriptions. The encapsulated intermediate variables indirectly represented process influence and enabled the modularization of class-internal models. These findings help in reducing dependencies between models, thereby contributing to improved model reusability.
{"title":"The Modeling of Post-Annealing and Etching Processes of ALD SiO₂ Using Intermediate Variables Considering Digital Twin Model Reusability","authors":"Ryosuke Okachi;Masanori Usui;Tomohiko Mori;Junya Muramatsu;Makoto Kuwahara;Daigo Kikuta","doi":"10.1109/TSM.2025.3579474","DOIUrl":"https://doi.org/10.1109/TSM.2025.3579474","url":null,"abstract":"In this study, we examined a digital twin model that has multiple processes. Generally, previous processes affect subsequent processes in the semiconductor manufacturing process. Therefore, to construct reusable modular models, the mutual influences between processes should be defined and concisely represented. We built a digital twin model involving the post-annealing and wet etching of an oxide film formed by atomic layer deposition (ALD), as a case study. We developed a modular model that separated processes based on intermediate variables extracted through physical analysis. The high coefficient of determination obtained from the prediction results suggests that these intermediate variables sufficiently captured the effect of the preceding processes. Further, we explored concepts for improving model reusability using class structure analysis within an object-oriented programming (OOP) framework. We observed the need for encapsulating physics-based intermediate variables within appropriate classes to separate process- and device-specific descriptions. The encapsulated intermediate variables indirectly represented process influence and enabled the modularization of class-internal models. These findings help in reducing dependencies between models, thereby contributing to improved model reusability.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"487-491"},"PeriodicalIF":2.3,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-12DOI: 10.1109/TSM.2025.3579031
Itilekha Podder;Marco Miller;Tamas Fischl;Udo Bub
As wafer maps become increasingly complex and high-dimensional, conventional clustering methods often fail to uncover subtle but meaningful defect patterns critical for yield enhancement and fault diagnosis in semiconductor manufacturing. We present an unsupervised clustering framework tailored to wafer map analysis, combining a convolutional autoencoder for automated feature extraction with principal component analysis for dimensionality refinement. Additionally, we incorporate improved deep embedded clustering, which augments the autoencoder with a clustering-oriented Kullback-Leibler divergence loss to learn compact and confident latent representations. Using standard clustering metrics and extensive visualization, our method is evaluated on two private industrial micro-electromechanical systems datasets and the public MIR-WM811K dataset. Unlike prior approaches, we introduce a comprehensive evaluation strategy that includes (i) cluster confidence and entropy distributions to assess prediction determinism, (ii) semi-supervised scoring for structure-aware validation, and (iii) interpretable visual tools, such as SHapley Additive exPlanations maps, gradient-weighted class activation mapping overlays, and average cluster profiles to support human-in-the-loop decision-making. Results show that our framework consistently outperforms baseline methods, including pretrained visual models like DINOv2 and TIMM-ResNet, in both clustering quality and interpretability. By aligning unsupervised representations with domain-specific failure semantics, the proposed pipeline enables more transparent and actionable analysis of wafer maps. Integrating automated feature learning, probabilistic confidence modelling, and visual attribution offers a robust path toward root-cause identification and process optimization in modern semiconductor fabrication.
{"title":"Unsupervised Representation Learning and Explainable Clustering for Wafer Map Pattern Analysis","authors":"Itilekha Podder;Marco Miller;Tamas Fischl;Udo Bub","doi":"10.1109/TSM.2025.3579031","DOIUrl":"https://doi.org/10.1109/TSM.2025.3579031","url":null,"abstract":"As wafer maps become increasingly complex and high-dimensional, conventional clustering methods often fail to uncover subtle but meaningful defect patterns critical for yield enhancement and fault diagnosis in semiconductor manufacturing. We present an unsupervised clustering framework tailored to wafer map analysis, combining a convolutional autoencoder for automated feature extraction with principal component analysis for dimensionality refinement. Additionally, we incorporate improved deep embedded clustering, which augments the autoencoder with a clustering-oriented Kullback-Leibler divergence loss to learn compact and confident latent representations. Using standard clustering metrics and extensive visualization, our method is evaluated on two private industrial micro-electromechanical systems datasets and the public MIR-WM811K dataset. Unlike prior approaches, we introduce a comprehensive evaluation strategy that includes (i) cluster confidence and entropy distributions to assess prediction determinism, (ii) semi-supervised scoring for structure-aware validation, and (iii) interpretable visual tools, such as SHapley Additive exPlanations maps, gradient-weighted class activation mapping overlays, and average cluster profiles to support human-in-the-loop decision-making. Results show that our framework consistently outperforms baseline methods, including pretrained visual models like DINOv2 and TIMM-ResNet, in both clustering quality and interpretability. By aligning unsupervised representations with domain-specific failure semantics, the proposed pipeline enables more transparent and actionable analysis of wafer maps. Integrating automated feature learning, probabilistic confidence modelling, and visual attribution offers a robust path toward root-cause identification and process optimization in modern semiconductor fabrication.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"693-708"},"PeriodicalIF":2.3,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The advancement of high-power 4H-SiC devices demands innovative solutions to address doping challenges. This study introduces a 355 nm DPSS Nd:YAG laser scanning doping as a method for aluminum doping and surface modification in semi-insulating 4H-SiC, addressing the limitations of conventional ion-implantation techniques. Through a systematic investigation of laser fluence, we identify process windows that balance carrier activation and material properties. At a fluence threshold of 2.588 J/cm2, effective Al activation was achieved, while higher fluences induce polysilicon formation, as verified by Raman, GIXRD, SIMS, and Hall measurements. Remarkably, laser processing generates a multilayer surface structure—graphite, polysilicon, poly-SiC, and 4H-SiC—potentially reducing the barrier height. This method demonstrates significant potential for fabricating high-performance p-type contacts on 4H-SiC. These findings highlight the sensitivity and versatility of laser doping, offering critical insights into next-generation SiC fabrication strategies.
{"title":"Process Sensitivity of 355 nm-Laser-Induced High-Concentration Aluminum Doping for P-Type Layer in Semi-Insulating 4H-SiC","authors":"Chang-Shan Shen;Wei-Chi Aeneas Hsu;Ming-Chun Hsu;Hong-Yi Guo;Yu-Xian Liu;Hua-Yan Chen;Guan-Jie Liu;Duong Minh Hoang;Tsun-Hsu Chang","doi":"10.1109/TSM.2025.3577624","DOIUrl":"https://doi.org/10.1109/TSM.2025.3577624","url":null,"abstract":"The advancement of high-power 4H-SiC devices demands innovative solutions to address doping challenges. This study introduces a 355 nm DPSS Nd:YAG laser scanning doping as a method for aluminum doping and surface modification in semi-insulating 4H-SiC, addressing the limitations of conventional ion-implantation techniques. Through a systematic investigation of laser fluence, we identify process windows that balance carrier activation and material properties. At a fluence threshold of 2.588 J/cm2, effective Al activation was achieved, while higher fluences induce polysilicon formation, as verified by Raman, GIXRD, SIMS, and Hall measurements. Remarkably, laser processing generates a multilayer surface structure—graphite, polysilicon, poly-SiC, and 4H-SiC—potentially reducing the barrier height. This method demonstrates significant potential for fabricating high-performance p-type contacts on 4H-SiC. These findings highlight the sensitivity and versatility of laser doping, offering critical insights into next-generation SiC fabrication strategies.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"728-733"},"PeriodicalIF":2.3,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-04DOI: 10.1109/TSM.2025.3576496
Christian Milleneuve Budiono;Akira Hirata;Tatsuya Yamaguchi;Takafumi Koseki;Wataru Ohnishi
The semiconductor vertical furnace is a key component in semiconductor manufacturing, used for heat treatment processes such as oxidation, layer deposition, and annealing. Improving the speed of temperature control in this equipment is critical for increasing productivity, particularly by shortening the time required for large temperature changes, known as thermal ramps. Although modeling a linear time-invariant (LTI) system is effective around a fixed operating temperature, it becomes inaccurate during rapid heating and cooling processes that involve large temperature changes, especially when faster control performance is required. As a result, conventional model-based control methods often fail to deliver both fast and accurate temperature regulation in practical scenarios. The aim of this paper is to develop a data-driven approach that enables high-speed, high-precision temperature control in a semiconductor vertical furnace. The proposed method is based on an iterative experimental procedure that refines the control model using actual measurement data. Experimental results show that the approach achieves the target temperature accurately within just four iterations. Compared to the conventional Linear-Quadratic-Gaussian (LQG) control method, it reduces the settling time to within ±1°C of the setpoint by 18% and lowers energy consumption by 20%. These findings demonstrate that the proposed data-driven method enables faster, more accurate, and more energy-efficient temperature control in semiconductor vertical furnaces.
{"title":"Fast and High-Precision Temperature Control in Semiconductor Vertical Furnace via Iterative Experiments","authors":"Christian Milleneuve Budiono;Akira Hirata;Tatsuya Yamaguchi;Takafumi Koseki;Wataru Ohnishi","doi":"10.1109/TSM.2025.3576496","DOIUrl":"https://doi.org/10.1109/TSM.2025.3576496","url":null,"abstract":"The semiconductor vertical furnace is a key component in semiconductor manufacturing, used for heat treatment processes such as oxidation, layer deposition, and annealing. Improving the speed of temperature control in this equipment is critical for increasing productivity, particularly by shortening the time required for large temperature changes, known as thermal ramps. Although modeling a linear time-invariant (LTI) system is effective around a fixed operating temperature, it becomes inaccurate during rapid heating and cooling processes that involve large temperature changes, especially when faster control performance is required. As a result, conventional model-based control methods often fail to deliver both fast and accurate temperature regulation in practical scenarios. The aim of this paper is to develop a data-driven approach that enables high-speed, high-precision temperature control in a semiconductor vertical furnace. The proposed method is based on an iterative experimental procedure that refines the control model using actual measurement data. Experimental results show that the approach achieves the target temperature accurately within just four iterations. Compared to the conventional Linear-Quadratic-Gaussian (LQG) control method, it reduces the settling time to within ±1°C of the setpoint by 18% and lowers energy consumption by 20%. These findings demonstrate that the proposed data-driven method enables faster, more accurate, and more energy-efficient temperature control in semiconductor vertical furnaces.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"478-486"},"PeriodicalIF":2.3,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11023613","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-03DOI: 10.1109/TSM.2025.3576269
Yi Fang;Chun Wang;Sihai Zhang
The Scanning Electron Microscope (SEM) images of Random Access Memory (RAM) chips contain valuable process-related information, particularly at the edges, which can provide critical insights for hotspot detection and Line Edge Roughness (LER) measurement. However, significant noise and low grayscale variation in SEM images often lead to edge omissions and misdetections. In this paper, we introduce the concept of the SEM Interlayer Effect (SIE), based on empirical observations and theoretical analysis, to address these challenges. Leveraging insights from SIE, we propose a novel Physics-Informed Edge Detection (PIED) method, which enhances the underlying neural network architecture and incorporates a hierarchical weighted loss function. Based on the real-world SEM image dataset from RAM production, PIED achieves a superior Optimal Dataset Scale (ODS) F-measure compared to the Canny edge detector, improving from 0.9001 to 0.9701—a 7.8% increase. This demonstrates that even in the absence of ground truth, PIED significantly enhances edge detection performance, which is crucial for improving process control in semiconductor manufacturing.
{"title":"Physics-Informed Machine Learning-Based Edge Detection for SEM Images","authors":"Yi Fang;Chun Wang;Sihai Zhang","doi":"10.1109/TSM.2025.3576269","DOIUrl":"https://doi.org/10.1109/TSM.2025.3576269","url":null,"abstract":"The Scanning Electron Microscope (SEM) images of Random Access Memory (RAM) chips contain valuable process-related information, particularly at the edges, which can provide critical insights for hotspot detection and Line Edge Roughness (LER) measurement. However, significant noise and low grayscale variation in SEM images often lead to edge omissions and misdetections. In this paper, we introduce the concept of the SEM Interlayer Effect (SIE), based on empirical observations and theoretical analysis, to address these challenges. Leveraging insights from SIE, we propose a novel Physics-Informed Edge Detection (PIED) method, which enhances the underlying neural network architecture and incorporates a hierarchical weighted loss function. Based on the real-world SEM image dataset from RAM production, PIED achieves a superior Optimal Dataset Scale (ODS) F-measure compared to the Canny edge detector, improving from 0.9001 to 0.9701—a 7.8% increase. This demonstrates that even in the absence of ground truth, PIED significantly enhances edge detection performance, which is crucial for improving process control in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"579-587"},"PeriodicalIF":2.3,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：