Pub Date : 2024-03-07DOI: 10.1109/TSM.2024.3394310
{"title":"Call for Nominations: 2024 EDS Early Career Award","authors":"","doi":"10.1109/TSM.2024.3394310","DOIUrl":"https://doi.org/10.1109/TSM.2024.3394310","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522494","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-07DOI: 10.1109/TSM.2024.3378554
{"title":"IEEE Transactions on Semiconductor Manufacturing Information for Authors","authors":"","doi":"10.1109/TSM.2024.3378554","DOIUrl":"https://doi.org/10.1109/TSM.2024.3378554","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10522491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of the highly developed era of 5G, AI, and IoT, the latest generation of ICs is designed with smaller-sized FETs, lower time delays, and reduced power consumption. To address the challenges posed by these advancements, materials with a lower k value than silicon dioxide (low-k, <4.0) are being developed to reduce resistance-capacitance (RC) time delays and power consumption. While low-k materials are still emerging, various material companies continue to introduce innovative low-k products, such as SiLK, Fox, Coral, and Aurora from different companies. Simultaneously, considering proprietary business interests, the processes and materials associated with these products have not been clearly presented. In this report, we employ a novel set of equipment to validate an innovative formulation for synthesizing a low-k silicon dioxide layer. Thickness measurements confirm a higher deposition rate of silicon dioxide layers, with excellent uniformity observed on 8” wafer. Furthermore, the dielectric constant (k) decreases to 2.35, indicating the production of a great low-k material. Additionally, in the formulation of reactants, we avoid the use of silane and organic silane, contributing to improved safety in the facility and effective control of reactant costs. The results highlight an advantageous option for fabricating interconnect layers in ICs.
随着 5G、人工智能和物联网等高度发达时代的到来，最新一代集成电路的设计需要更小尺寸的 FET、更低的时间延迟和更低的功耗。为了应对这些进步带来的挑战，人们正在开发 k 值低于二氧化硅（低 k 值，<4.0）的材料，以减少电阻电容 (RC) 时间延迟和功耗。虽然低 k 值材料仍在不断涌现，但各材料公司仍在不断推出创新的低 k 值产品，如不同公司推出的 SiLK、Fox、Coral 和 Aurora。同时，考虑到专有商业利益，与这些产品相关的工艺和材料还没有得到清晰的介绍。在本报告中，我们采用了一套新型设备来验证合成低 K 值二氧化硅层的创新配方。厚度测量结果表明，二氧化硅层的沉积率更高，在 8" 晶圆上观察到了极佳的均匀性。此外，介电常数（k）降至 2.35，表明生产出了极佳的低 k 材料。此外，在反应物配方中，我们避免了硅烷和有机硅烷的使用，从而提高了设备的安全性，并有效控制了反应物成本。这些结果凸显了制造集成电路互连层的有利选择。
{"title":"Pioneering Fast and Safe Low-k Silicon Dioxide Synthesis for Modern Integrated Circuits","authors":"Yu-Ting Chow;Shou-Yen Chao;Pei-Cheng Jiang;Chung-Tzu Chang;Mei-Yuan Zheng;Mu-Chun Wang;Cheng-Hsun-Tony Chang;Chii-Ruey Lin;Chia-Fu Chen;Kuo-Wei Liu","doi":"10.1109/TSM.2024.3374067","DOIUrl":"10.1109/TSM.2024.3374067","url":null,"abstract":"With the advent of the highly developed era of 5G, AI, and IoT, the latest generation of ICs is designed with smaller-sized FETs, lower time delays, and reduced power consumption. To address the challenges posed by these advancements, materials with a lower k value than silicon dioxide (low-k, <4.0) are being developed to reduce resistance-capacitance (RC) time delays and power consumption. While low-k materials are still emerging, various material companies continue to introduce innovative low-k products, such as SiLK, Fox, Coral, and Aurora from different companies. Simultaneously, considering proprietary business interests, the processes and materials associated with these products have not been clearly presented. In this report, we employ a novel set of equipment to validate an innovative formulation for synthesizing a low-k silicon dioxide layer. Thickness measurements confirm a higher deposition rate of silicon dioxide layers, with excellent uniformity observed on 8” wafer. Furthermore, the dielectric constant (k) decreases to 2.35, indicating the production of a great low-k material. Additionally, in the formulation of reactants, we avoid the use of silane and organic silane, contributing to improved safety in the facility and effective control of reactant costs. The results highlight an advantageous option for fabricating interconnect layers in ICs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140073978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this work, the significant lifetime improvement of negative bias thermal instability (NBTI) is demonstrated by the introduction of a thin SiN layer fabricated by plasma enhanced atomic layer deposition (PEALD) in stress memorization technique (SMT). The thin SiN film is deposited before the plasma enhanced chemical vapor deposition (PECVD) of SiN layer with a high tensile stress. It is revealed that the possible H2 escape accompanied with interface de-passivation can be effectively suppressed by this thin PEALD SiN layer, which may further reduce the interface states at Si/gate dielectric interface. Hence, about 500% NBTI lifetime improvement for PMOSFETs is demonstrated without obvious performance degradation for both NMOSFETs and PMOSFETs.
在这项工作中，通过在应力记忆技术（SMT）中引入等离子体增强原子层沉积（PEALD）制造的氮化硅薄层，证明了负偏压热不稳定性（NBTI）寿命的显著改善。SiN 薄膜是在具有高拉伸应力的 SiN 层的等离子体增强化学气相沉积 (PECVD) 之前沉积的。结果表明，PEALD SiN 薄膜可以有效抑制可能伴随着界面去钝化的 H2 逸出，从而进一步减少硅/栅介质界面的界面态。因此，PMOSFET 的 NBTI 寿命提高了约 500%，而 NMOSFET 和 PMOSFET 的性能都没有明显下降。
{"title":"Significant Lifetime Improvement of Negative Bias Thermal Instability by Plasma Enhanced Atomic Layer Deposition SiN in Stress Memorization Technique","authors":"Cheng-Hao Liang;Zhao-Yang Li;Hao Liu;Yu-Long Jiang","doi":"10.1109/TSM.2024.3397814","DOIUrl":"10.1109/TSM.2024.3397814","url":null,"abstract":"In this work, the significant lifetime improvement of negative bias thermal instability (NBTI) is demonstrated by the introduction of a thin SiN layer fabricated by plasma enhanced atomic layer deposition (PEALD) in stress memorization technique (SMT). The thin SiN film is deposited before the plasma enhanced chemical vapor deposition (PECVD) of SiN layer with a high tensile stress. It is revealed that the possible H2 escape accompanied with interface de-passivation can be effectively suppressed by this thin PEALD SiN layer, which may further reduce the interface states at Si/gate dielectric interface. Hence, about 500% NBTI lifetime improvement for PMOSFETs is demonstrated without obvious performance degradation for both NMOSFETs and PMOSFETs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140936903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-06DOI: 10.1109/TSM.2024.3373690
Yiwen Liao;Raphaël Latty;Bin Yang
Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is typically performed by experienced human experts. However, with the fast development in semiconductor industry, test cases can contain hundreds of variables. The resulting high-dimensionality poses enormous challenges to experts. Thereby, some recent prior works have introduced data-driven variable selection algorithms to tackle these problems and achieved notable success. Nevertheless, for these methods, experts are not involved in training and inference phases, which may lead to bias and inaccuracy due to the lack of prior knowledge. Hence, this letter for the first time aims to design a novel conditional variable selection approach while keeping experts in the loop. In this way, we expect that our algorithm can be more efficiently and effectively trained to identify the most critical variables under certain expert knowledge. Extensive experiments on both synthetic and real-world datasets from industry have been conducted and shown the effectiveness of our method.
{"title":"Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation","authors":"Yiwen Liao;Raphaël Latty;Bin Yang","doi":"10.1109/TSM.2024.3373690","DOIUrl":"10.1109/TSM.2024.3373690","url":null,"abstract":"Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is typically performed by experienced human experts. However, with the fast development in semiconductor industry, test cases can contain hundreds of variables. The resulting high-dimensionality poses enormous challenges to experts. Thereby, some recent prior works have introduced data-driven variable selection algorithms to tackle these problems and achieved notable success. Nevertheless, for these methods, experts are not involved in training and inference phases, which may lead to bias and inaccuracy due to the lack of prior knowledge. Hence, this letter for the first time aims to design a novel conditional variable selection approach while keeping experts in the loop. In this way, we expect that our algorithm can be more efficiently and effectively trained to identify the most critical variables under certain expert knowledge. Extensive experiments on both synthetic and real-world datasets from industry have been conducted and shown the effectiveness of our method.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140057229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-06DOI: 10.1109/TSM.2024.3396994
Min Ho Kim;Hye Eun Sim;Sang Jeen Hong
Semiconductor manufacturing processing can be jeopardized due to process fluctuations, and the degradation of equipment parts can significantly influence process variation. Timely diagnosing equipment faults causing process variations is desired in current high-end product manufacturing. This paper proposes a diagnostic method for the SiH4 gas flow rate drift using N2 vibrational transition in oxide deposition. In this research, optical emission spectroscopy (OES) and quadrupole mass spectrometer (QMS) are employed as condition monitoring sensors serving as a reference model to compare the diagnostic performance for gas flow rate drift. The study observes that the OES model exhibits much higher performance for minor diagnoses of less than 5% drift. The diagnostic model performance can be enhanced by incorporating plasma condition and gas indicators compared to when these indicators are used individually. This suggests that when conducting diagnostics for equipment and processes, it is crucial to consider indirect indicators like plasma indicators along with direct indicators such as gas radical density. The comprehensive use of both types of indicators enhances the diagnostic performance, providing a more accurate assessment of the conditions and potential problem in semiconductor manufacturing.
{"title":"Part-Level Fault Classification of Mass Flow Controller Drift in Plasma Deposition Equipment","authors":"Min Ho Kim;Hye Eun Sim;Sang Jeen Hong","doi":"10.1109/TSM.2024.3396994","DOIUrl":"10.1109/TSM.2024.3396994","url":null,"abstract":"Semiconductor manufacturing processing can be jeopardized due to process fluctuations, and the degradation of equipment parts can significantly influence process variation. Timely diagnosing equipment faults causing process variations is desired in current high-end product manufacturing. This paper proposes a diagnostic method for the SiH4 gas flow rate drift using N2 vibrational transition in oxide deposition. In this research, optical emission spectroscopy (OES) and quadrupole mass spectrometer (QMS) are employed as condition monitoring sensors serving as a reference model to compare the diagnostic performance for gas flow rate drift. The study observes that the OES model exhibits much higher performance for minor diagnoses of less than 5% drift. The diagnostic model performance can be enhanced by incorporating plasma condition and gas indicators compared to when these indicators are used individually. This suggests that when conducting diagnostics for equipment and processes, it is crucial to consider indirect indicators like plasma indicators along with direct indicators such as gas radical density. The comprehensive use of both types of indicators enhances the diagnostic performance, providing a more accurate assessment of the conditions and potential problem in semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140882583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-04DOI: 10.1109/TSM.2024.3372521
Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui
In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.
{"title":"Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask","authors":"Aixi Pan;Chenxu Zhu;Zheng Yan;Xiaoli Zhu;Zhongyi Liu;Bo Cui","doi":"10.1109/TSM.2024.3372521","DOIUrl":"10.1109/TSM.2024.3372521","url":null,"abstract":"In view of the wide range of applications for ultra-sharp silicon (Si) nanocones, extensive research has been conducted on their fabrication processes. However, these conventional methods pose challenges in terms of achieving uniformity, controllability, and cost-efficiency. This study presents a novel approach to fabricating Si nanocone structures through reactive ion etching (RIE) using a tapered silicon dioxide mask, followed by thermal oxidation sharpening to reduce the apex diameter to 4 nm. Here the tapered SiO2 mask with a smooth sidewall was created through a combination of RIE and a buffered oxide etchant (BOE) etching. The lithography of the oxide mask is achieved using a cost-effective (compared to electron beam lithography) maskless aligner system (MLA). Subsequently, a non-switching pseudo-Bosch process, employing sulfur hexafluoride (SF6) gas and octafluorocyclobutane (C4F8) gas, is utilized for the etching the Si nanocone structures, resulting in an average apex diameter of 30 nm. Finally, thermal oxidation followed by oxide removal further sharpens these cones to 4 nm.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140037422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-03DOI: 10.1109/TSM.2024.3396423
Yongwon Jo;Jinsoo Bae;Hansam Cho;Heejoong Roh;Kyunghye Kim;Munki Jo;Jaeung Tae;Seoung Bum Kim
Semantic segmentation for automated measurement in semiconductor manufacturing, specifically with wafer transmission electron microscopy (TEM) images, poses significant challenges because of the difficulty of acquisition, prevalent noise, and ambiguous object boundaries. However, prior studies focused on broadening the application of semantic segmentation for automated measurement without considering the specific intricacies of TEM images. In this study, we propose a wafer TEM images-specific semantic segmentation and transfer learning (WTEM-SST) framework to address these issues. The proposed WTEM-SST involves a pre-training stage, wafer TEM-specific data augmentation methods, and a boundary-focused loss function. The pre-training stage addresses the difficulty of collecting and annotating wafer TEM images, followed by fine-tuning for process-specific segmentation models. Our data augmentation techniques mitigate challenges related to limited training samples, lots of noise, and unclear boundaries. The boundary-focused loss makes the model more precise in boundary recognition during fine-tuning. We demonstrate that WTEM-SST outperforms conventional segmentation models, with our studies highlighting the effectiveness of the three components in WTEM-SST.
在半导体制造领域，特别是晶圆透射电子显微镜（TEM）图像的自动测量中，语义分割是一项重大挑战，因为采集困难、噪声普遍存在、物体边界模糊不清。然而，之前的研究侧重于扩大语义分割在自动测量中的应用，却没有考虑到 TEM 图像的特殊复杂性。在本研究中，我们提出了晶圆 TEM 图像特定语义分割和迁移学习（WTEM-SST）框架来解决这些问题。拟议的 WTEM-SST 包括预训练阶段、晶圆 TEM 特定数据增强方法和以边界为重点的损失函数。预训练阶段解决了收集和注释晶圆 TEM 图像的困难，随后对特定于流程的分割模型进行微调。我们的数据增强技术可以缓解训练样本有限、噪音大和边界不清晰等难题。在微调过程中，以边界为重点的损失使模型的边界识别更加精确。我们的研究表明，WTEM-SST 优于传统的分割模型，并突出了 WTEM-SST 中三个组件的有效性。
{"title":"Semantic Segmentation for Noisy and Limited Wafer Transmission Electron Microscope Images","authors":"Yongwon Jo;Jinsoo Bae;Hansam Cho;Heejoong Roh;Kyunghye Kim;Munki Jo;Jaeung Tae;Seoung Bum Kim","doi":"10.1109/TSM.2024.3396423","DOIUrl":"10.1109/TSM.2024.3396423","url":null,"abstract":"Semantic segmentation for automated measurement in semiconductor manufacturing, specifically with wafer transmission electron microscopy (TEM) images, poses significant challenges because of the difficulty of acquisition, prevalent noise, and ambiguous object boundaries. However, prior studies focused on broadening the application of semantic segmentation for automated measurement without considering the specific intricacies of TEM images. In this study, we propose a wafer TEM images-specific semantic segmentation and transfer learning (WTEM-SST) framework to address these issues. The proposed WTEM-SST involves a pre-training stage, wafer TEM-specific data augmentation methods, and a boundary-focused loss function. The pre-training stage addresses the difficulty of collecting and annotating wafer TEM images, followed by fine-tuning for process-specific segmentation models. Our data augmentation techniques mitigate challenges related to limited training samples, lots of noise, and unclear boundaries. The boundary-focused loss makes the model more precise in boundary recognition during fine-tuning. We demonstrate that WTEM-SST outperforms conventional segmentation models, with our studies highlighting the effectiveness of the three components in WTEM-SST.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.3,"publicationDate":"2024-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140831626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-26DOI: 10.1109/TSM.2024.3370175
Ruian Ji;Rong Chen;Lan Chen
Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process.
{"title":"A Lightweight Chip-Scale Chemical Mechanical Polishing Model Based on Polynomial Network","authors":"Ruian Ji;Rong Chen;Lan Chen","doi":"10.1109/TSM.2024.3370175","DOIUrl":"10.1109/TSM.2024.3370175","url":null,"abstract":"Chemical mechanical polishing/planarization (CMP) combines physical grinding and chemical reactions to planarize the wafer surface. The complex mechanism of CMP brings great challenges to the mechanism-based modeling process. The data-driven CMP modeling process is limited by insufficient datasets. At the same time, these two types of models generally have high computational complexity. In this paper, we introduce the group method of data handling (GMDH)-type polynomial network to build the CMP model to address the above challenges. We designed and manufactured the test chip using a 28nm process. The measurement data from the test chip shows that compared with the mechanism-based CMP model, the trained CMP model based on GMDH-type polynomial network has higher accuracy and lower computational complexity, with the average simulation speed being 115x faster. Experiments based on silicon data show that this modeling method has a small demand for data, and 20 randomly selected sets of data can meet the needs for modeling the current CMP process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":null,"pages":null},"PeriodicalIF":2.7,"publicationDate":"2024-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139977641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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