Pub Date : 2025-03-12DOI: 10.1109/TSM.2025.3569278
Miyuki Kouda;Yumi Mori;Tomohiko Sugita;Youyang Ng
Recently, the complexity of semiconductor manufacturing processes has increased, resulting in a growing need for high-precision optimization of device structures. For example, in batch-type wet etching devices, the flow of chemical liquids in the process bath can vary depending on the device structure, which causes variations in the etching state of the wafer. This issue is addressed using a feedback mechanism that adjusts the device structure iteratively based on the results of an etching experiment, thereby achieving more uniform etching conditions. However, this approach requires a large number of trial experiments. In the fabrication process of 3D flash memory devices, the formation of word lines in the silicon substrate requires precise control of the silicon concentration in the etching solution. However, this concentration can fluctuate due to the dissolution of the SiN film during the etching process, which can cause various problems. Thus, this study proposes an innovative multi-objective Bayesian optimization method that is informed by image and physical quantity data from fluid dynamics simulations to derive optimal wet etching bath design parameters. The proposed method was validated through simulation experiments, and the simulation results were used to identify the best possible wet etching bath designs.
{"title":"Optimal Design of Wet Etching Bath for 3-D Flash Memories Using Multi-Objective Bayesian Optimization","authors":"Miyuki Kouda;Yumi Mori;Tomohiko Sugita;Youyang Ng","doi":"10.1109/TSM.2025.3569278","DOIUrl":"https://doi.org/10.1109/TSM.2025.3569278","url":null,"abstract":"Recently, the complexity of semiconductor manufacturing processes has increased, resulting in a growing need for high-precision optimization of device structures. For example, in batch-type wet etching devices, the flow of chemical liquids in the process bath can vary depending on the device structure, which causes variations in the etching state of the wafer. This issue is addressed using a feedback mechanism that adjusts the device structure iteratively based on the results of an etching experiment, thereby achieving more uniform etching conditions. However, this approach requires a large number of trial experiments. In the fabrication process of 3D flash memory devices, the formation of word lines in the silicon substrate requires precise control of the silicon concentration in the etching solution. However, this concentration can fluctuate due to the dissolution of the SiN film during the etching process, which can cause various problems. Thus, this study proposes an innovative multi-objective Bayesian optimization method that is informed by image and physical quantity data from fluid dynamics simulations to derive optimal wet etching bath design parameters. The proposed method was validated through simulation experiments, and the simulation results were used to identify the best possible wet etching bath designs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"439-445"},"PeriodicalIF":2.3,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advanced semiconductor manufacturing increasingly depends on Virtual Metrology (VM) for real-time quality monitoring, yet conventional data-driven models rarely capture the scarce or extreme process conditions critical for robust predictions. We propose a Multi-Stage Constrained Data Generative Augmentation (MSC-DGA) framework that integrates Variational Autoencoders (VAE), Normalizing Flows, and Constrained Diffusion to systematically expand coverage of seldom-seen regimes. By embedding strict engineering constraints during generation and applying a two-stage quality filter, MSC-DGA ensures physically plausible synthetic samples. We further present theoretical proofs showing that multi-stage generation can approximate complex sensor distributions while enforcing domain validity, thereby improving coverage and preserving essential process physics. Empirically, we demonstrate the approach on real WBG SiC data, incorporating these curated samples into a Generative Foundation Model (GFA-VM) with few-shot fine-tuning and uncertainty-based active sampling, yielding significant accuracy gains for rarely observed conditions. Experiments confirm notable performance improvements over single-stage augmentation and naive oversampling. By rigorously balancing distribution realism with engineering feasibility, MSC-DGA offers a practical and theoretically grounded advancement for VM, enhancing adaptive control and product quality in next-generation power semiconductor manufacturing.
{"title":"Generative AI-Driven Data Augmentation for Robust Virtual Metrology: GANs, VAEs, and Diffusion Models","authors":"Chin-Yi Lin;Tzu-Liang Tseng;Solayman Hossain Emon;Tsung-Han Tsai","doi":"10.1109/TSM.2025.3569229","DOIUrl":"https://doi.org/10.1109/TSM.2025.3569229","url":null,"abstract":"Advanced semiconductor manufacturing increasingly depends on Virtual Metrology (VM) for real-time quality monitoring, yet conventional data-driven models rarely capture the scarce or extreme process conditions critical for robust predictions. We propose a Multi-Stage Constrained Data Generative Augmentation (MSC-DGA) framework that integrates Variational Autoencoders (VAE), Normalizing Flows, and Constrained Diffusion to systematically expand coverage of seldom-seen regimes. By embedding strict engineering constraints during generation and applying a two-stage quality filter, MSC-DGA ensures physically plausible synthetic samples. We further present theoretical proofs showing that multi-stage generation can approximate complex sensor distributions while enforcing domain validity, thereby improving coverage and preserving essential process physics. Empirically, we demonstrate the approach on real WBG SiC data, incorporating these curated samples into a Generative Foundation Model (GFA-VM) with few-shot fine-tuning and uncertainty-based active sampling, yielding significant accuracy gains for rarely observed conditions. Experiments confirm notable performance improvements over single-stage augmentation and naive oversampling. By rigorously balancing distribution realism with engineering feasibility, MSC-DGA offers a practical and theoretically grounded advancement for VM, enhancing adaptive control and product quality in next-generation power semiconductor manufacturing.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"642-658"},"PeriodicalIF":2.3,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11002548","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study aims to enhance photovoltaic performance of dye-sensitized solar cells (DSSCs) by modification of photoanode with nanofibers (NFs) as an additional layer. g-C3N4 and ZnS (CN-ZnS) were selected for the modification of TiO2 nanofibers. The g-C3N4 was synthesized using a calcination method, while the CN-ZnS was successfully prepared through a simple hydrothermal method. Subsequently, CN-ZnS/TiO2 NFs with different mixing ratios were fabricated using electrospinning technology. The synthesized material was characterized by X-ray diffraction and scanning electron microscopy. The positive impact of incorporating the additional layer on the photovoltaic performance of DSSCs was confirmed through electrochemical impedance spectroscopy, UV-vis spectroscopy, J-V characterization, and incident photon-to-current efficiency measurements. Notably, the DSSC modified with 1% CN-ZnS/TiO2 NFs achieves an efficiency of 5.44%, and it reaches an efficiency of 7.04% under low illumination (30 mW/cm2). These results suggest that CN-ZnS/TiO2 NFs are promising for enhancing the performance of DSSCs.
{"title":"Manufacturing of g-C3N4-ZnS-Doped TiO2 Nanofibers by Electrospinning and Their Application to Dye-Sensitized Solar Cell as an Additional Layer in Photoanode","authors":"Yu-Hsun Nien;Jhih-Wei Zeng;Yu-Han Huang;Jung-Chuan Chou;Chih-Hsien Lai;Po-Yu Kuo;Po-Hui Yang;Yu-Wei Chen;Wen-Hao Chen","doi":"10.1109/TSM.2025.3550570","DOIUrl":"https://doi.org/10.1109/TSM.2025.3550570","url":null,"abstract":"This study aims to enhance photovoltaic performance of dye-sensitized solar cells (DSSCs) by modification of photoanode with nanofibers (NFs) as an additional layer. g-C3N4 and ZnS (CN-ZnS) were selected for the modification of TiO2 nanofibers. The g-C3N4 was synthesized using a calcination method, while the CN-ZnS was successfully prepared through a simple hydrothermal method. Subsequently, CN-ZnS/TiO2 NFs with different mixing ratios were fabricated using electrospinning technology. The synthesized material was characterized by X-ray diffraction and scanning electron microscopy. The positive impact of incorporating the additional layer on the photovoltaic performance of DSSCs was confirmed through electrochemical impedance spectroscopy, UV-vis spectroscopy, J-V characterization, and incident photon-to-current efficiency measurements. Notably, the DSSC modified with 1% CN-ZnS/TiO2 NFs achieves an efficiency of 5.44%, and it reaches an efficiency of 7.04% under low illumination (30 mW/cm2). These results suggest that CN-ZnS/TiO2 NFs are promising for enhancing the performance of DSSCs.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"332-342"},"PeriodicalIF":2.3,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-05DOI: 10.1109/TSM.2025.3567206
A. Abbadie;A. Desse;K. Melhem;S. Dario Mariani;D. Fagiani;P. Zuliani;F. Faller
A review of 300mm high-resistivity Czochralski silicon (Cz-Si) wafers after optimized thermal treatments, is presented. The challenge of resistivity monitoring due to the thermal donors phenomenon is highlighted. A new protocol based on the combination of several metrology techniques is proposed. Such a methodology is crucial as oxygen-related defects called thermal donors (TD) formed during 450°C anneals are electrically active across various substrates: n-type used typically in insulated-gate bipolar transistors (IGBT) and p-type used for example in radiofrequency (RF)-based technologies. We show that such TDs result in resistivity loss, with different behavior depending on substrate doping, and confirm the detrimental impact of these TDs on devices performances.
{"title":"Integration Challenges on 300-mm High Resistivity Silicon Substrates","authors":"A. Abbadie;A. Desse;K. Melhem;S. Dario Mariani;D. Fagiani;P. Zuliani;F. Faller","doi":"10.1109/TSM.2025.3567206","DOIUrl":"https://doi.org/10.1109/TSM.2025.3567206","url":null,"abstract":"A review of 300mm high-resistivity Czochralski silicon (Cz-Si) wafers after optimized thermal treatments, is presented. The challenge of resistivity monitoring due to the thermal donors phenomenon is highlighted. A new protocol based on the combination of several metrology techniques is proposed. Such a methodology is crucial as oxygen-related defects called thermal donors (TD) formed during 450°C anneals are electrically active across various substrates: n-type used typically in insulated-gate bipolar transistors (IGBT) and p-type used for example in radiofrequency (RF)-based technologies. We show that such TDs result in resistivity loss, with different behavior depending on substrate doping, and confirm the detrimental impact of these TDs on devices performances.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"383-390"},"PeriodicalIF":2.3,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The annealing properties of vacancies in HfO2 layers deposited on Si substrates and their role in amorphous-to-crystalline transition were studied with monoenergetic positron beams. HfO2 layers with a thickness of 4–30 nm were fabricated by the atomic layer deposition technique. The major vacancy-type defects in these layers were identified as a Hf vacancy (VHf) coupled with multiple oxygen vacancies (VOs) and larger vacancy clusters. After annealing at 500°C, the concentration of vacancy clusters started to increase, which was attributed to the agglomeration of intrinsic open spaces in the amorphous phase upon the phase transition from amorphous to monoclinic crystalline phases. The amorphous-crystalline transition started near the interface between the HfO2 layer and bottom electrodes (TiN). After the crystallization, the concentration of vacancy clusters decreased as the annealing temperature increased.
{"title":"Vacancy-Type Defects in HfO2 Layers and Their Role in Amorphous-to-Crystalline Transition Studied by Monoenergetic Positron Beams","authors":"Akira Uedono;Kazuya Kawakami;Tatsunori Kuribara;Ryu Hasunuma;Yosuke Harashima;Yasuteru Shigeta;Zeyuan Ni;Ruolin Yan;Hideo Nakamura;Akira Notake;Tsuyoshi Moriya;Koji Michishio;Shoji Ishibashi","doi":"10.1109/TSM.2025.3548450","DOIUrl":"https://doi.org/10.1109/TSM.2025.3548450","url":null,"abstract":"The annealing properties of vacancies in HfO2 layers deposited on Si substrates and their role in amorphous-to-crystalline transition were studied with monoenergetic positron beams. HfO2 layers with a thickness of 4–30 nm were fabricated by the atomic layer deposition technique. The major vacancy-type defects in these layers were identified as a Hf vacancy (VHf) coupled with multiple oxygen vacancies (VOs) and larger vacancy clusters. After annealing at 500°C, the concentration of vacancy clusters started to increase, which was attributed to the agglomeration of intrinsic open spaces in the amorphous phase upon the phase transition from amorphous to monoclinic crystalline phases. The amorphous-crystalline transition started near the interface between the HfO2 layer and bottom electrodes (TiN). After the crystallization, the concentration of vacancy clusters decreased as the annealing temperature increased.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"463-468"},"PeriodicalIF":2.3,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-03DOI: 10.1109/TSM.2025.3547026
Sungwon Hong;Younsoo Lee;Kyungsik Lee
In this paper, we consider the problem of production capacity estimation for a semiconductor wafer fabrication facility. Capacity estimation involves determining the maximum achievable throughput of a wafer fabrication facility during a given planning horizon in consideration of both product mix and target cycle time. The wafer fabrication facility (fab) is one of the most complex production systems, consisting of hundreds of process steps for each product as well as thousands of processing machines and re-entrant process flows wherein products must visit the same workcenter multiple times. In this regard, estimating production capacity by modeling the wafer manufacturing process is a challenging problem. To properly capture the dynamics of the process, we propose a flexible-lead-time-based optimization model that considers both the state of work-in-process (WIP) over time and the relationship between WIP levels and lead times. The results of simulation experiments using a real-sized instance demonstrate the advantages of the proposed model over existing alternatives.
{"title":"Capacity Estimation for Semiconductor Wafer Fabrication Facilities via an Optimization Model Based on Flexible Lead Times","authors":"Sungwon Hong;Younsoo Lee;Kyungsik Lee","doi":"10.1109/TSM.2025.3547026","DOIUrl":"https://doi.org/10.1109/TSM.2025.3547026","url":null,"abstract":"In this paper, we consider the problem of production capacity estimation for a semiconductor wafer fabrication facility. Capacity estimation involves determining the maximum achievable throughput of a wafer fabrication facility during a given planning horizon in consideration of both product mix and target cycle time. The wafer fabrication facility (fab) is one of the most complex production systems, consisting of hundreds of process steps for each product as well as thousands of processing machines and re-entrant process flows wherein products must visit the same workcenter multiple times. In this regard, estimating production capacity by modeling the wafer manufacturing process is a challenging problem. To properly capture the dynamics of the process, we propose a flexible-lead-time-based optimization model that considers both the state of work-in-process (WIP) over time and the relationship between WIP levels and lead times. The results of simulation experiments using a real-sized instance demonstrate the advantages of the proposed model over existing alternatives.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"292-310"},"PeriodicalIF":2.3,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-01DOI: 10.1109/TSM.2025.3562407
{"title":"Call for Nominations for Editor-in-Chief: IEEE Transactions on Semiconductor Manufacturing","authors":"","doi":"10.1109/TSM.2025.3562407","DOIUrl":"https://doi.org/10.1109/TSM.2025.3562407","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"368-368"},"PeriodicalIF":2.3,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10981907","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-01DOI: 10.1109/TSM.2025.3560206
{"title":"Call for Nominations for Editor-in-Chief: IEEE Electron Device Letters","authors":"","doi":"10.1109/TSM.2025.3560206","DOIUrl":"https://doi.org/10.1109/TSM.2025.3560206","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"364-364"},"PeriodicalIF":2.3,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10981910","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-01DOI: 10.1109/TSM.2025.3546539
{"title":"Journal of Lightwave Technology Special Issue on: OFS-29","authors":"","doi":"10.1109/TSM.2025.3546539","DOIUrl":"https://doi.org/10.1109/TSM.2025.3546539","url":null,"abstract":"","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"363-363"},"PeriodicalIF":2.3,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10981904","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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