Pub Date : 2025-06-02DOI: 10.1109/TSM.2025.3575588
Kangbai Li;Shun-Ichiro Ohmi
In this paper, the Ar/N2 gas flow rate dependence on the ferroelectric HfNx (x>1) formed by electron cyclotron resonance (ECR)-plasma sputtering was investigated. The equivalent oxide thickness (EOT) of 2.7 nm was obtained with Ar/N2 gas flow rate of 8/7 sccm followed by the 400°C/5 min post metallization annealing (PMA) in N2. The EOT was increased to 4.2 nm with the deposition of the Ar/N2 gas flow rate of 14/16 sccm. The density of interface states (Dit) was found to be as low as $2.0times 10{^{{11}}}$ ${mathrm {cm}}^{-2}$ ${mathrm {eV}}^{-1}$ . The P-V results demonstrate that a remanent polarization (2Pr) of $6.6~mu $ C/cm2, and positive-up negative-down measurement showed the switching polarization of $4.7~mu $ C/cm2 at an Ar/N2 flow rate of 8/7 sccm, which is high enough for metal-ferroelectric-Si field-effect transistor (MFSFET) application.
{"title":"Ar/N₂ Gas Flow Rate Dependence on the Ferroelectric HfNₓ Thin Film Formation by ECR-Plasma Sputtering","authors":"Kangbai Li;Shun-Ichiro Ohmi","doi":"10.1109/TSM.2025.3575588","DOIUrl":"https://doi.org/10.1109/TSM.2025.3575588","url":null,"abstract":"In this paper, the Ar/N2 gas flow rate dependence on the ferroelectric HfNx (x>1) formed by electron cyclotron resonance (ECR)-plasma sputtering was investigated. The equivalent oxide thickness (EOT) of 2.7 nm was obtained with Ar/N2 gas flow rate of 8/7 sccm followed by the 400°C/5 min post metallization annealing (PMA) in N2. The EOT was increased to 4.2 nm with the deposition of the Ar/N2 gas flow rate of 14/16 sccm. The density of interface states (Dit) was found to be as low as <inline-formula> <tex-math>$2.0times 10{^{{11}}}$ </tex-math></inline-formula> <inline-formula> <tex-math>${mathrm {cm}}^{-2}$ </tex-math></inline-formula><inline-formula> <tex-math>${mathrm {eV}}^{-1}$ </tex-math></inline-formula>. The P-V results demonstrate that a remanent polarization (2Pr) of <inline-formula> <tex-math>$6.6~mu $ </tex-math></inline-formula>C/cm2, and positive-up negative-down measurement showed the switching polarization of <inline-formula> <tex-math>$4.7~mu $ </tex-math></inline-formula>C/cm2 at an Ar/N2 flow rate of 8/7 sccm, which is high enough for metal-ferroelectric-Si field-effect transistor (MFSFET) application.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"459-462"},"PeriodicalIF":2.3,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study demonstrates the selective tuning of p-type and n-type conductivity in ZnO thin films by incorporating MXenes at varying molar concentrations. ZnO thin films were fabricated using a cost-effective sol-gel method and annealed at 450°C under thermal and magnetically assisted conditions. Rietveld analysis of the hot point probe and Hall measurements were performed to confirm the conductivity variations induced by MXene doping. The results suggest that the conductivity of n-ZnO increased significantly from 0.27 mho/cm to 1274 mho/cm, while p-ZnO conductivity ranged from 0.0012 mho/cm to $6.2times 10^{-4}$ mho/cm and $3.3times 10^{-3}$ mho/cm to 0.84 mho/cm under magnetic fields of 280 G and 400 G, respectively. XRD analysis revealed a polycrystalline structure with an average grain size of about ~100 nm. This novel approach offers a versatile method to control ZnO thin-film conductivity, including an extensive analysis of magnetic properties.
{"title":"MXenes as a Tool to Control p-Type Conductivity in ZnO Thin Film","authors":"Lucky Agarwal;Ajay Kumar Dwivedi;Tulika Bajpai;Uvanesh Kasiviswanathan;Shweta Tripathi","doi":"10.1109/TSM.2025.3575857","DOIUrl":"https://doi.org/10.1109/TSM.2025.3575857","url":null,"abstract":"This study demonstrates the selective tuning of p-type and n-type conductivity in ZnO thin films by incorporating MXenes at varying molar concentrations. ZnO thin films were fabricated using a cost-effective sol-gel method and annealed at 450°C under thermal and magnetically assisted conditions. Rietveld analysis of the hot point probe and Hall measurements were performed to confirm the conductivity variations induced by MXene doping. The results suggest that the conductivity of n-ZnO increased significantly from 0.27 mho/cm to 1274 mho/cm, while p-ZnO conductivity ranged from 0.0012 mho/cm to <inline-formula> <tex-math>$6.2times 10^{-4}$ </tex-math></inline-formula> mho/cm and <inline-formula> <tex-math>$3.3times 10^{-3}$ </tex-math></inline-formula> mho/cm to 0.84 mho/cm under magnetic fields of 280 G and 400 G, respectively. XRD analysis revealed a polycrystalline structure with an average grain size of about ~100 nm. This novel approach offers a versatile method to control ZnO thin-film conductivity, including an extensive analysis of magnetic properties.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"588-595"},"PeriodicalIF":2.3,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-02DOI: 10.1109/TSM.2025.3575743
K. Tsutano;T. Mawaki;Y. Shirai;R. Kuroda
Metal contamination control in semiconductor manufacturing processes is important because it affects device reliability and yield. The metal contamination control value in deionized water (DIW) is required at the pg/L level for advanced device manufacturing. However, previous studies on metallic contamination proved insufficient owing to their utilization of highly concentrated solutions at a $mu $ g/L level with batch rinsing processes. In this study, we investigated the contamination behavior of metal impurities at the pg/L level in DIW on the silicon dioxide (SiO2) surface during a single-wafer cleaning process. We found that Al, Ti, Fe, Zn, and Ga were highly adsorbed for the $SiO_{2}$ surface, and these surface concentrations were positively correlated with the concentration in DIW and the rinse time. Whereas the adsorption behavior of these metals affected by rinse fluid parameters such as the rotation speed and the flow rate. The adsorption probability increased owing to thinning of the liquid-firm thickness and increasing radial velocity. Furthermore, the metal adsorption ratio was decreased with thinning boundary-layer thickness. Herein, we provide new insights into the pertinence of reducing metal concentrations in DIW and optimizing fluid parameters during a single-wafer cleaning to prevent metal contamination for advanced the semiconductor manufacturing process.
{"title":"Metal Contamination Behavior on Silicon Dioxide Surface Rinsed With Deionized Water Containing Ultra-Trace Metal During Single-Wafer Cleaning","authors":"K. Tsutano;T. Mawaki;Y. Shirai;R. Kuroda","doi":"10.1109/TSM.2025.3575743","DOIUrl":"https://doi.org/10.1109/TSM.2025.3575743","url":null,"abstract":"Metal contamination control in semiconductor manufacturing processes is important because it affects device reliability and yield. The metal contamination control value in deionized water (DIW) is required at the pg/L level for advanced device manufacturing. However, previous studies on metallic contamination proved insufficient owing to their utilization of highly concentrated solutions at a <inline-formula> <tex-math>$mu $ </tex-math></inline-formula>g/L level with batch rinsing processes. In this study, we investigated the contamination behavior of metal impurities at the pg/L level in DIW on the silicon dioxide (SiO2) surface during a single-wafer cleaning process. We found that Al, Ti, Fe, Zn, and Ga were highly adsorbed for the <inline-formula> <tex-math>$SiO_{2}$ </tex-math></inline-formula> surface, and these surface concentrations were positively correlated with the concentration in DIW and the rinse time. Whereas the adsorption behavior of these metals affected by rinse fluid parameters such as the rotation speed and the flow rate. The adsorption probability increased owing to thinning of the liquid-firm thickness and increasing radial velocity. Furthermore, the metal adsorption ratio was decreased with thinning boundary-layer thickness. Herein, we provide new insights into the pertinence of reducing metal concentrations in DIW and optimizing fluid parameters during a single-wafer cleaning to prevent metal contamination for advanced the semiconductor manufacturing process.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"492-498"},"PeriodicalIF":2.3,"publicationDate":"2025-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-24DOI: 10.1109/TSM.2025.3564051
Hongxu Li;Jie Ren;Teng Wu;Yonghong Zhang;Jianhua Chang;Hongen Yang;Ronghua Chi
Wafer defect detection and classification are essential for ensuring the quality of semiconductor wafers, optimizing production efficiency. However, existing methods often fail to process shallow and deep feature information concurrently, restricting their capacity to utilize multi-level features for accurate classification. To overcome this limitation, this paper introduces a novel dual-path architecture, DPFEE-Net, which integrates PeleeNet’s dense connection structure and multi-channel feature fusion techniques with the deep feature extraction capabilities of Convolutional Neural Networks (CNNs). By combining these two approaches, DPFEE-Net effectively captures both shallow and deep features, enhancing the detection of critical wafer surface defect patterns. Additionally, squeeze-and-excitation (SE) attention mechanism is incorporated, enabling the model to prioritize defect-prone areas in images, further improving classification accuracy. Experimental results demonstrate that DPFEE-Net achieves a remarkable average accuracy of 96.8% on the WM-811K dataset, surpassing existing methods such as WM-PeleeNet, WDD-SCA and MobileNetV2. Moreover, the model delivers superior detection performance with reduced computational complexity and parameter requirements, making it highly suitable for practical deployment in production environments.
{"title":"DPFEE-Net: Enhancing Wafer Defect Classification Through Dual-Path Neural Architecture","authors":"Hongxu Li;Jie Ren;Teng Wu;Yonghong Zhang;Jianhua Chang;Hongen Yang;Ronghua Chi","doi":"10.1109/TSM.2025.3564051","DOIUrl":"https://doi.org/10.1109/TSM.2025.3564051","url":null,"abstract":"Wafer defect detection and classification are essential for ensuring the quality of semiconductor wafers, optimizing production efficiency. However, existing methods often fail to process shallow and deep feature information concurrently, restricting their capacity to utilize multi-level features for accurate classification. To overcome this limitation, this paper introduces a novel dual-path architecture, DPFEE-Net, which integrates PeleeNet’s dense connection structure and multi-channel feature fusion techniques with the deep feature extraction capabilities of Convolutional Neural Networks (CNNs). By combining these two approaches, DPFEE-Net effectively captures both shallow and deep features, enhancing the detection of critical wafer surface defect patterns. Additionally, squeeze-and-excitation (SE) attention mechanism is incorporated, enabling the model to prioritize defect-prone areas in images, further improving classification accuracy. Experimental results demonstrate that DPFEE-Net achieves a remarkable average accuracy of 96.8% on the WM-811K dataset, surpassing existing methods such as WM-PeleeNet, WDD-SCA and MobileNetV2. Moreover, the model delivers superior detection performance with reduced computational complexity and parameter requirements, making it highly suitable for practical deployment in production environments.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"605-611"},"PeriodicalIF":2.3,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-17DOI: 10.1109/TSM.2025.3561919
Tsung-Ta Hsieh;Jui-Hsin Hsiao;Chia-Yen Lee;Hung-Kai Wang
In TFT-LCD (thin film transistor-liquid crystal display) manufacturing industry, achieving accurate defect detection is a critical and a complex task, which involves using optical inspection technology to capture images of the testing objects and classify defects by image recognition. However, using cameras to capture panel images often results in moiré patterns, which can distort the appearance of defects, making defect classification challenging. Previous studies on moiré pattern removal in TFT-LCD panel often relies on paired data with labels. This study proposes a new method for eliminating moiré patterns without label data, and we propose 3-phase self-consistent generative adversarial networks (3SC-GANs) considering the frequency loss, compared with other existing supervised and unsupervised models. An empirical study of a leading panel manufacturer is conducted to validate the proposed model, and the results show that the proposed model outperforms other benchmark methods by evaluating image quality and defect classification metrics.
{"title":"Unsupervised Image Demoiréing With Self-Consistent GAN for TFT-LCD Defect Recognition","authors":"Tsung-Ta Hsieh;Jui-Hsin Hsiao;Chia-Yen Lee;Hung-Kai Wang","doi":"10.1109/TSM.2025.3561919","DOIUrl":"https://doi.org/10.1109/TSM.2025.3561919","url":null,"abstract":"In TFT-LCD (thin film transistor-liquid crystal display) manufacturing industry, achieving accurate defect detection is a critical and a complex task, which involves using optical inspection technology to capture images of the testing objects and classify defects by image recognition. However, using cameras to capture panel images often results in moiré patterns, which can distort the appearance of defects, making defect classification challenging. Previous studies on moiré pattern removal in TFT-LCD panel often relies on paired data with labels. This study proposes a new method for eliminating moiré patterns without label data, and we propose 3-phase self-consistent generative adversarial networks (3SC-GANs) considering the frequency loss, compared with other existing supervised and unsupervised models. An empirical study of a leading panel manufacturer is conducted to validate the proposed model, and the results show that the proposed model outperforms other benchmark methods by evaluating image quality and defect classification metrics.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"510-521"},"PeriodicalIF":2.3,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-10DOI: 10.1109/TSM.2025.3559471
Ah Hyun Park;Yeonjin Lee;Seyun Jo;Sang Jeen Hong
Continuous deposition processes in PECVD environments are critical for ensuring the uniformity and reproducibility of thin films across various applications. Silicon dioxide (SiO2), widely used in these processes for its excellent properties, can leave residual materials in PECVD chambers, leading to material buildup that compromises process consistency and reproducibility. A representative example of compromised process consistency and reproducibility is found in the manufacturing of 3D-NAND flash memory, which involves oxide-nitride (ON) stacking processes. Effective chamber cleaning is essential to ensure consistent and reproducible performance in continuous deposition processes. Nitrogen trifluoride (NF3), a commonly used as chamber cleaning gas, is expected to be newly belong to the greenhouse gas regulations due to its high global warming potential (GWP), which may pose both environmental and industrial risks. In this study, we explored the potential of carbonyl fluoride (COF2) as an alternative chamber cleaning gas with low GWP, albeit with an inferior cleaning rate compared to NF3. This study investigates gas dissociation in the plasma environment and analyzes plasma species and changes in the deposited film surface affecting the cleaning rate. Based on the results, proposed improvements are made to the cleaning process design for COF2, considering factors influencing plasma enhanced chemical vapor deposition (PECVD) chamber cleaning efficiency.
{"title":"An Alternative PECVD Chamber Cleaning Gas of COF2 for Low-GWP Consideration","authors":"Ah Hyun Park;Yeonjin Lee;Seyun Jo;Sang Jeen Hong","doi":"10.1109/TSM.2025.3559471","DOIUrl":"https://doi.org/10.1109/TSM.2025.3559471","url":null,"abstract":"Continuous deposition processes in PECVD environments are critical for ensuring the uniformity and reproducibility of thin films across various applications. Silicon dioxide (SiO2), widely used in these processes for its excellent properties, can leave residual materials in PECVD chambers, leading to material buildup that compromises process consistency and reproducibility. A representative example of compromised process consistency and reproducibility is found in the manufacturing of 3D-NAND flash memory, which involves oxide-nitride (ON) stacking processes. Effective chamber cleaning is essential to ensure consistent and reproducible performance in continuous deposition processes. Nitrogen trifluoride (NF3), a commonly used as chamber cleaning gas, is expected to be newly belong to the greenhouse gas regulations due to its high global warming potential (GWP), which may pose both environmental and industrial risks. In this study, we explored the potential of carbonyl fluoride (COF2) as an alternative chamber cleaning gas with low GWP, albeit with an inferior cleaning rate compared to NF3. This study investigates gas dissociation in the plasma environment and analyzes plasma species and changes in the deposited film surface affecting the cleaning rate. Based on the results, proposed improvements are made to the cleaning process design for COF2, considering factors influencing plasma enhanced chemical vapor deposition (PECVD) chamber cleaning efficiency.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"596-604"},"PeriodicalIF":2.3,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-09DOI: 10.1109/TSM.2025.3559301
Min Ho Kim;Jeong Eun Jeon;Sang Jeen Hong
Optical emission spectroscopy (OES) data analysis with inert gas, called rare gas tracing method, has become a widely accepted method for the monitoring of plasma process. However, it is becoming less desirable due to the need for a higher hardmask selectivity in etch. Conventional OES analysis focuses on bulk plasma properties, such as electron temperature and density, but fail to capture the full complexity of etch rate changes influenced by both ohmic heating and ion acceleration. To address these limitations, we propose an alternative approach that incorporates multiple plasma information (PI), offering a more comprehensive view of plasma mechanisms. This new framework was applied to develop an OES-based monitoring technique without inert gases. By modulating source and bias powers to vary both ohmic heating and ion acceleration, the multiple PI model demonstrated a higher $R^{2}$ score (~0.97) compared to the traditional Ar-based PI model (~0.8). In addition, explainable artificial intelligence (XAI) indicated that multiple PI had greater importance, demonstrating its effectiveness in monitoring etch rates in non-inert gas processes. It not only detects changes in the etch process, but also identifies whether the variations stem from chemical or physical reactions to be useful for advanced process control.
{"title":"In-Situ Plasma Monitoring Using Multiple Plasma Information in SiO₂ Etch Process","authors":"Min Ho Kim;Jeong Eun Jeon;Sang Jeen Hong","doi":"10.1109/TSM.2025.3559301","DOIUrl":"https://doi.org/10.1109/TSM.2025.3559301","url":null,"abstract":"Optical emission spectroscopy (OES) data analysis with inert gas, called rare gas tracing method, has become a widely accepted method for the monitoring of plasma process. However, it is becoming less desirable due to the need for a higher hardmask selectivity in etch. Conventional OES analysis focuses on bulk plasma properties, such as electron temperature and density, but fail to capture the full complexity of etch rate changes influenced by both ohmic heating and ion acceleration. To address these limitations, we propose an alternative approach that incorporates multiple plasma information (PI), offering a more comprehensive view of plasma mechanisms. This new framework was applied to develop an OES-based monitoring technique without inert gases. By modulating source and bias powers to vary both ohmic heating and ion acceleration, the multiple PI model demonstrated a higher <inline-formula> <tex-math>$R^{2}$ </tex-math></inline-formula> score (~0.97) compared to the traditional Ar-based PI model (~0.8). In addition, explainable artificial intelligence (XAI) indicated that multiple PI had greater importance, demonstrating its effectiveness in monitoring etch rates in non-inert gas processes. It not only detects changes in the etch process, but also identifies whether the variations stem from chemical or physical reactions to be useful for advanced process control.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"543-553"},"PeriodicalIF":2.3,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Achieving long-duration, large bulk GaN growth is crucial to supply low-cost, high-quality GaN. Halogen-free vapor phase epitaxy (HF-VPE) is a promising method for bulk GaN growth but faces challenges due to severe polycrystals deposition on reactor components, such as the source-gas nozzles, which impedes stable, extended growth. In this study, we developed models to simulate the polycrystal deposition in HF-VPE-GaN growth conditions by including surface reactions of GaN formation and NH3 decomposition. Moreover, we devised conditions for controlling gas flow and interdiffusion to suppress polycrystal deposition around the source-gas nozzles. Experimental results aligned with simulations, showing that increasing the distance between Ga and NH3 nozzles and replacing the sheath gas from H2 to N2 effectively minimized polycrystal formation. The findings confirm that reducing NH3 concentration through catalytic surface decomposition on refractory components is crucial to polycrystal suppression. Optimizing nozzle dimensions and gas species synergistically controls the gas flow and interdiffusion. The constructed models contribute to advancing the design of polycrystal suppressive structures and conditions for long-duration bulk GaN growth.
{"title":"Modeling and Designing a GaN-Growth Reactor With Halogen-Free Vapor Phase Epitaxy: NH3 Decomposition at the Catalytic Surface of Components to Replicate Parasitic Polycrystal Formation","authors":"Hiroki Shimazu;Shin-Ichi Nishizawa;Shugo Nitta;Hiroshi Amano;Daisuke Nakamura","doi":"10.1109/TSM.2025.3558328","DOIUrl":"https://doi.org/10.1109/TSM.2025.3558328","url":null,"abstract":"Achieving long-duration, large bulk GaN growth is crucial to supply low-cost, high-quality GaN. Halogen-free vapor phase epitaxy (HF-VPE) is a promising method for bulk GaN growth but faces challenges due to severe polycrystals deposition on reactor components, such as the source-gas nozzles, which impedes stable, extended growth. In this study, we developed models to simulate the polycrystal deposition in HF-VPE-GaN growth conditions by including surface reactions of GaN formation and NH3 decomposition. Moreover, we devised conditions for controlling gas flow and interdiffusion to suppress polycrystal deposition around the source-gas nozzles. Experimental results aligned with simulations, showing that increasing the distance between Ga and NH3 nozzles and replacing the sheath gas from H2 to N2 effectively minimized polycrystal formation. The findings confirm that reducing NH3 concentration through catalytic surface decomposition on refractory components is crucial to polycrystal suppression. Optimizing nozzle dimensions and gas species synergistically controls the gas flow and interdiffusion. The constructed models contribute to advancing the design of polycrystal suppressive structures and conditions for long-duration bulk GaN growth.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"311-323"},"PeriodicalIF":2.3,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-04DOI: 10.1109/TSM.2025.3558015
Shuai Guo;Dengao Li;Jumin Zhao;Shuang Qiu;Bao Tang;Biao Luo
Dark line defects (DLDs) are critical factors that significantly limit the performance of vertical-cavity surface-emitting lasers (VCSELs). Recently, convolutional neural network (CNN)-based methods have shown strong feature extraction capabilities, achieving exceptional performance across various fields. However, these methods still face limitations on the segmentation samples with weak texture, varying shapes and blurred boundary information. To overcome these limitations, a novel segmentation method named VECSNet is proposed in this work. Electroluminescence imaging technology is employed to capture the emission characteristics of VCSELs and develop the corresponding dataset. To improve the extraction of emission features, a parallel dual-encoding structure is designed to capture both spatial and semantic information. Additionally, a feature fusion attention (FFA) block is introduced to effectively fuse features extracted from different branches. Faced with blurred boundary information, a boundary detector is proposed to guide each fusion connection in acquiring boundary feature information and enrich feature representation. Furthermore, to improve segmentation precision for areas with varying shapes, auxiliary logits are introduced to enhance discriminative ability of the network from multiple levels. Experimental results on the VCSEL emission segmentation dataset demonstrate that the proposed method achieves a high Dice score (92.5%) with fewer parameters (6.4M), outperforming other state-of-the-art segmentation approaches.
{"title":"VECSNet: A Nondestructive Automatic VCSEL Chip Detection Network With Pixelwise Segmentation","authors":"Shuai Guo;Dengao Li;Jumin Zhao;Shuang Qiu;Bao Tang;Biao Luo","doi":"10.1109/TSM.2025.3558015","DOIUrl":"https://doi.org/10.1109/TSM.2025.3558015","url":null,"abstract":"Dark line defects (DLDs) are critical factors that significantly limit the performance of vertical-cavity surface-emitting lasers (VCSELs). Recently, convolutional neural network (CNN)-based methods have shown strong feature extraction capabilities, achieving exceptional performance across various fields. However, these methods still face limitations on the segmentation samples with weak texture, varying shapes and blurred boundary information. To overcome these limitations, a novel segmentation method named VECSNet is proposed in this work. Electroluminescence imaging technology is employed to capture the emission characteristics of VCSELs and develop the corresponding dataset. To improve the extraction of emission features, a parallel dual-encoding structure is designed to capture both spatial and semantic information. Additionally, a feature fusion attention (FFA) block is introduced to effectively fuse features extracted from different branches. Faced with blurred boundary information, a boundary detector is proposed to guide each fusion connection in acquiring boundary feature information and enrich feature representation. Furthermore, to improve segmentation precision for areas with varying shapes, auxiliary logits are introduced to enhance discriminative ability of the network from multiple levels. Experimental results on the VCSEL emission segmentation dataset demonstrate that the proposed method achieves a high Dice score (92.5%) with fewer parameters (6.4M), outperforming other state-of-the-art segmentation approaches.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"270-280"},"PeriodicalIF":2.3,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143896211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Double-Sided Polishing (DSP) is a critical process for achieving flatness in silicon wafers. This study explores the relationship between the variations in the gap between polishing plates and the surface convexity of wafers. The study indicates that differences in the gap between the upper and lower plates affect the stress distribution on the wafers, altering the removal rate at different positions during the DSP process. This results in the formation of convex curves on the wafer surface. Additionally, this research proposes a calculation method to determine the convex curves, by coupling the contact stress on wafer surface with its relative motion path to the pad, to calculate the removal amount at different positions. The reliability of the model was ultimately verified through experimental results. This method provides guidance for optimizing DSP processes to improve wafer flatness.
{"title":"Mechanistic Analysis of the Effect of Gap on Convex Curves of Wafer in Double-Sided Polishing","authors":"Jiayu Chen;Yiran Liu;Xiangang Wang;Jun Cao;Wenjie Yu;Lei Zhu","doi":"10.1109/TSM.2025.3574490","DOIUrl":"https://doi.org/10.1109/TSM.2025.3574490","url":null,"abstract":"Double-Sided Polishing (DSP) is a critical process for achieving flatness in silicon wafers. This study explores the relationship between the variations in the gap between polishing plates and the surface convexity of wafers. The study indicates that differences in the gap between the upper and lower plates affect the stress distribution on the wafers, altering the removal rate at different positions during the DSP process. This results in the formation of convex curves on the wafer surface. Additionally, this research proposes a calculation method to determine the convex curves, by coupling the contact stress on wafer surface with its relative motion path to the pad, to calculate the removal amount at different positions. The reliability of the model was ultimately verified through experimental results. This method provides guidance for optimizing DSP processes to improve wafer flatness.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"571-578"},"PeriodicalIF":2.3,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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