Pub Date : 2024-10-01DOI: 10.1109/TSM.2024.3471738
Jingjun Li;Xiukun Wang;Yadong Sun;Lei Zhang
Aiming at the poor film evenness in conventional ultrasonic spraying coating methods, an acoustic resonance atomization (ARA) is proposed for spray coating on silicon wafers using an in-house experimental prototype. By modulating the acoustic pressure distribution in the optimized acoustic chamber, the ARA can achieve atomized photoresist droplets with $sim 8.5~mu $ m in median diameter and concentrated droplet concentration. For mesoscale photoresist droplets, the uniform film of AZ P4620 photoresist is coated on silicon wafers by exploring and optimizing the substrate temperatures and spray velocity. The mechanism of uniform film formation by mesoscale photoresist droplets is explored. Smaller droplets can effectively fill the micro-gaps within the photoresist film layer, forming a dense and uniform film. The experimental results demonstrate that the employed coating process can obtain a controllable photoresist film thickness and evenness index of less than 5% with a high-quality film layer, which provides an alternative technological solution for the spray coating.
针对传统超声波喷涂方法涂膜均匀性差的问题，我们提出了一种声共振雾化技术（ARA），并利用内部实验原型在硅片上进行了喷涂。通过调节优化声学室中的声压分布，ARA 可以实现中值直径为 8.5~mu $ m 的雾化光刻胶液滴，并且液滴浓度集中。对于中尺度光刻胶液滴，通过探索和优化基底温度和喷雾速度，在硅片上涂覆了均匀的 AZ P4620 光刻胶膜。探索了中尺度光刻胶液滴均匀成膜的机理。较小的液滴能有效填充光刻胶膜层内的微间隙，形成致密均匀的薄膜。实验结果表明，所采用的喷涂工艺可获得可控的光刻胶膜厚，均匀度指数小于 5%，膜层质量高，为喷涂工艺提供了另一种技术解决方案。
{"title":"Photoresist Spray Coating on Silicon Wafers With Acoustic Resonance Atomization","authors":"Jingjun Li;Xiukun Wang;Yadong Sun;Lei Zhang","doi":"10.1109/TSM.2024.3471738","DOIUrl":"https://doi.org/10.1109/TSM.2024.3471738","url":null,"abstract":"Aiming at the poor film evenness in conventional ultrasonic spraying coating methods, an acoustic resonance atomization (ARA) is proposed for spray coating on silicon wafers using an in-house experimental prototype. By modulating the acoustic pressure distribution in the optimized acoustic chamber, the ARA can achieve atomized photoresist droplets with \u0000<inline-formula> <tex-math>$sim 8.5~mu $ </tex-math></inline-formula>\u0000m in median diameter and concentrated droplet concentration. For mesoscale photoresist droplets, the uniform film of AZ P4620 photoresist is coated on silicon wafers by exploring and optimizing the substrate temperatures and spray velocity. The mechanism of uniform film formation by mesoscale photoresist droplets is explored. Smaller droplets can effectively fill the micro-gaps within the photoresist film layer, forming a dense and uniform film. The experimental results demonstrate that the employed coating process can obtain a controllable photoresist film thickness and evenness index of less than 5% with a high-quality film layer, which provides an alternative technological solution for the spray coating.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"576-582"},"PeriodicalIF":2.3,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142694677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-25DOI: 10.1109/TSM.2024.3468000
Chen-Fu Chien;Butsayarin Suwattananuruk
Wafer probing test is crucial for selecting the known good dies via the probe card as the testing signal interface between the tester and the integrated circuits on the fabricated wafers. The consistency of probe cards is critical to ensure the integrity of the testing data. Motivated by realistic needs, this research aims to develop an effective approach for spatial clustering to select PCB materials while considering Time Domain Reflectometry (TDR) data. To estimate the validity, experiments are conducted with 20 datasets collected in real settings to compare the proposed DBSCAN with three spatial clustering models including Agglomerative Hierarchical Clustering (AHC), K-means, and Spectral Clustering. An empirical study is conducted in a lead semiconductor testing company in Taiwan for validation. The results have shown that the proposed approach can improve the impedance value of material selection by at least 15% for single-signal and 25% for differential signals, respectively. Thus, the proposed solution can effectively reduce intrinsic variance and enhance probing test integrity to reduce both the producer’s risk and the customer’s risk. Indeed, the developed solution is implemented to enhance virtual vertical integration for the semiconductor supply chain.
{"title":"Density-Based Spatial Clustering of Applications With Noise (DBSCAN) for Probe Card Production for Advanced Quality Control of Wafer Probing Test","authors":"Chen-Fu Chien;Butsayarin Suwattananuruk","doi":"10.1109/TSM.2024.3468000","DOIUrl":"https://doi.org/10.1109/TSM.2024.3468000","url":null,"abstract":"Wafer probing test is crucial for selecting the known good dies via the probe card as the testing signal interface between the tester and the integrated circuits on the fabricated wafers. The consistency of probe cards is critical to ensure the integrity of the testing data. Motivated by realistic needs, this research aims to develop an effective approach for spatial clustering to select PCB materials while considering Time Domain Reflectometry (TDR) data. To estimate the validity, experiments are conducted with 20 datasets collected in real settings to compare the proposed DBSCAN with three spatial clustering models including Agglomerative Hierarchical Clustering (AHC), K-means, and Spectral Clustering. An empirical study is conducted in a lead semiconductor testing company in Taiwan for validation. The results have shown that the proposed approach can improve the impedance value of material selection by at least 15% for single-signal and 25% for differential signals, respectively. Thus, the proposed solution can effectively reduce intrinsic variance and enhance probing test integrity to reduce both the producer’s risk and the customer’s risk. Indeed, the developed solution is implemented to enhance virtual vertical integration for the semiconductor supply chain.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"567-575"},"PeriodicalIF":2.3,"publicationDate":"2024-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-23DOI: 10.1109/TSM.2024.3465603
S. Nicoleau;J.-L. Champseix;D. Tagarian;F. Boeuf;P. Quinio
The impact of human activity on the environment is well documented. While citizens and responsible leaders aim at a more sustainable future, it is our duty as industrial companies to examine our products portfolio from its life cycle perspective. A promising approach is to use sustainable manufacturing technologies, that minimize negative environmental impact, while boosting the product benefits towards decarbonization objectives. This paper enriches our earlier description (Nicoleau et al., 2023) of STMicroelectronics approach in developing sustainable technologies. It starts by examining the global context while putting in perspective the definition of responsible products. Then we will go through the different phases of the product lifecycle by illustrating the involved processes during technology development and product manufacturing. And we will complete our Life Cycle Assessment methodology by illustrating the efforts in striving to reduce our ecological footprint towards our ambition of carbon neutrality by 2027.
{"title":"Sustainable Technologies for Responsible Products and a More Sustainable Future","authors":"S. Nicoleau;J.-L. Champseix;D. Tagarian;F. Boeuf;P. Quinio","doi":"10.1109/TSM.2024.3465603","DOIUrl":"https://doi.org/10.1109/TSM.2024.3465603","url":null,"abstract":"The impact of human activity on the environment is well documented. While citizens and responsible leaders aim at a more sustainable future, it is our duty as industrial companies to examine our products portfolio from its life cycle perspective. A promising approach is to use sustainable manufacturing technologies, that minimize negative environmental impact, while boosting the product benefits towards decarbonization objectives. This paper enriches our earlier description (Nicoleau et al., 2023) of STMicroelectronics approach in developing sustainable technologies. It starts by examining the global context while putting in perspective the definition of responsible products. Then we will go through the different phases of the product lifecycle by illustrating the involved processes during technology development and product manufacturing. And we will complete our Life Cycle Assessment methodology by illustrating the efforts in striving to reduce our ecological footprint towards our ambition of carbon neutrality by 2027.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"433-439"},"PeriodicalIF":2.3,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-12DOI: 10.1109/TSM.2024.3431207
Hyunchul Lee;Hyunjin Chang;Hosung Woo;WonGu Lee
The miniaturization of semiconductor chips creates discrepancies between the designed node size and physical values. It has resulted in a tightened on-product overlay (OPO) budget and increased the demand for improved measurement noise reduction and accuracy in optical systems. A solution utilizing moiré targets can address such challenges by enabling the amplification of small misalignments that cannot be achieved with conventional overlay targets using an image-based overlay (IBO) estimator. However, moiré patterns formed within a layer introduce noise sources and problems owing to interference from the reflected light, adversely affecting the precision of overlay measurements and limiting the effective utilization of moiré patterns. We investigate the problems associated with moiré patterns in the IBO measurement method and propose a novel overlay measurement algorithm to mitigate the problems. The proposed algorithm increases the accuracy of the filtering method in the spatial frequency domain and improves the overlay precision by approximately 2% compared with conventional measurement algorithms. The proposed low-frequency selection algorithm and signal indexing algorithm effectively address the challenges posed by high-frequency problems and signal strength degradation in moiré patterns. The proposed practical solution achieves more accurate overlay measurements in semiconductor manufacturing, enabling better control and optimization of chip fabrication processes.
{"title":"Overlay Measurement Algorithm for Moiré Targets Using Frequency Analysis","authors":"Hyunchul Lee;Hyunjin Chang;Hosung Woo;WonGu Lee","doi":"10.1109/TSM.2024.3431207","DOIUrl":"10.1109/TSM.2024.3431207","url":null,"abstract":"The miniaturization of semiconductor chips creates discrepancies between the designed node size and physical values. It has resulted in a tightened on-product overlay (OPO) budget and increased the demand for improved measurement noise reduction and accuracy in optical systems. A solution utilizing moiré targets can address such challenges by enabling the amplification of small misalignments that cannot be achieved with conventional overlay targets using an image-based overlay (IBO) estimator. However, moiré patterns formed within a layer introduce noise sources and problems owing to interference from the reflected light, adversely affecting the precision of overlay measurements and limiting the effective utilization of moiré patterns. We investigate the problems associated with moiré patterns in the IBO measurement method and propose a novel overlay measurement algorithm to mitigate the problems. The proposed algorithm increases the accuracy of the filtering method in the spatial frequency domain and improves the overlay precision by approximately 2% compared with conventional measurement algorithms. The proposed low-frequency selection algorithm and signal indexing algorithm effectively address the challenges posed by high-frequency problems and signal strength degradation in moiré patterns. The proposed practical solution achieves more accurate overlay measurements in semiconductor manufacturing, enabling better control and optimization of chip fabrication processes.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"489-498"},"PeriodicalIF":2.3,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-02DOI: 10.1109/TSM.2024.3452947
Yonghan Ju;Yung-Seop Lee
The Fourth Industrial Revolution offers an opportunity to companies to improve their competitiveness by utilizing data analytics. Particularly, real-time analysis of data gathered using various sensors is an area of interest for manufacturing companies aiming to use captured data for developing more robust monitoring systems. Therefore, trace data related to real-time processes have attracted attention in various fields. However, exploiting large amounts of trace data requires high-performance smart infrastructure. To this end, this study proposes statistics that incorporate the characteristics of trace data based on functional data analysis (FDA) and applies them to supervised learning. The empirical test results indicate that the functional principal component of FDA exhibits a significantly lower misclassification rate for the proposed model compared with that of the summary statistics-based model. Particularly, the FDA-based supervised model is less complex and exhibits less variability in terms of the number of explanatory variables based on the sample size of training data. When using summary statistics, the FDA variables were potentially selected as important variables in the least absolute shrinkage and selection operator model. The results of this study may assist various industries dealing with the aggregation of trace data for anomaly detection and intelligent factory management.
{"title":"Performance Evaluation of Supervised Learning Model Based on Functional Data Analysis and Summary Statistics","authors":"Yonghan Ju;Yung-Seop Lee","doi":"10.1109/TSM.2024.3452947","DOIUrl":"10.1109/TSM.2024.3452947","url":null,"abstract":"The Fourth Industrial Revolution offers an opportunity to companies to improve their competitiveness by utilizing data analytics. Particularly, real-time analysis of data gathered using various sensors is an area of interest for manufacturing companies aiming to use captured data for developing more robust monitoring systems. Therefore, trace data related to real-time processes have attracted attention in various fields. However, exploiting large amounts of trace data requires high-performance smart infrastructure. To this end, this study proposes statistics that incorporate the characteristics of trace data based on functional data analysis (FDA) and applies them to supervised learning. The empirical test results indicate that the functional principal component of FDA exhibits a significantly lower misclassification rate for the proposed model compared with that of the summary statistics-based model. Particularly, the FDA-based supervised model is less complex and exhibits less variability in terms of the number of explanatory variables based on the sample size of training data. When using summary statistics, the FDA variables were potentially selected as important variables in the least absolute shrinkage and selection operator model. The results of this study may assist various industries dealing with the aggregation of trace data for anomaly detection and intelligent factory management.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 1","pages":"65-72"},"PeriodicalIF":2.3,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/TSM.2024.3450286
Hüsnü Murat Koçak;Jesse Davis;Michel Houssa;Ahmet Teoman Naskali;Jerome Mitard
The threshold voltage $(V_{th})$ enables us to measure the functionality of ultra-scaled field effect transistors (FETs) and plays a key role in the performance evaluation of devices. Although many $V_{th}$ extraction methods exist and are in use in the industry, selecting an optimized and universal method is still difficult. Additionally, these methods often rely on expert validation, which increases the time cost for researchers to optimize the extraction process. In this work, we propose a universal and autonomous machine learning model, specifically a convolutional neural network based $V_{th}$ extractor model. The novelty of this work lies in simultaneously processing gate, drain, source, and bulk currents combined with gate voltage to remove the dependency on setting boundaries for gate voltage. Additionally, the training dataset is composed of measurements coming from transistors of different technology nodes (Planar, MOSFET, FinFET, Gate-All-Around) to provide generalization. Our method produces significantly more accurate results than traditional ML algorithms by extracting $V_{th}$ in 3mV mean absolute error rate and is verified with different performance metrics.
{"title":"Machine Learning-Based Universal Threshold Voltage Extraction of Transistors Using Convolutional Neural Networks","authors":"Hüsnü Murat Koçak;Jesse Davis;Michel Houssa;Ahmet Teoman Naskali;Jerome Mitard","doi":"10.1109/TSM.2024.3450286","DOIUrl":"10.1109/TSM.2024.3450286","url":null,"abstract":"The threshold voltage \u0000<inline-formula> <tex-math>$(V_{th})$ </tex-math></inline-formula>\u0000 enables us to measure the functionality of ultra-scaled field effect transistors (FETs) and plays a key role in the performance evaluation of devices. Although many \u0000<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>\u0000 extraction methods exist and are in use in the industry, selecting an optimized and universal method is still difficult. Additionally, these methods often rely on expert validation, which increases the time cost for researchers to optimize the extraction process. In this work, we propose a universal and autonomous machine learning model, specifically a convolutional neural network based \u0000<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>\u0000 extractor model. The novelty of this work lies in simultaneously processing gate, drain, source, and bulk currents combined with gate voltage to remove the dependency on setting boundaries for gate voltage. Additionally, the training dataset is composed of measurements coming from transistors of different technology nodes (Planar, MOSFET, FinFET, Gate-All-Around) to provide generalization. Our method produces significantly more accurate results than traditional ML algorithms by extracting \u0000<inline-formula> <tex-math>$V_{th}$ </tex-math></inline-formula>\u0000 in 3mV mean absolute error rate and is verified with different performance metrics.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"615-619"},"PeriodicalIF":2.3,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-23DOI: 10.1109/TSM.2024.3448458
Jinyang Li;Hung-Fei Kuo
The continuous miniaturization of semiconductor devices has increased the demand for advanced process control technologies. This process requires real-time measurement systems to monitor manufacturing parameters to ensure efficiency and high quality. This study introduces a novel optical module that uses a spatial light modulator to extract key-point intensity distributions from diffraction images in scatterometry. The efficacy of this method is demonstrated on a grating target with a pitch of 855 nm using a feature extraction algorithm that identifies key point locations based on calculated diffraction images. A particularly designed off-axis extraction pattern facilitates the acquisition of key-point intensity distributions. Moreover, incorporating a cylindrical lens into the optical setup reduces the image feature dimensionality, thereby decreasing the data storage space and enabling the output in a streamlined vector format conducive to further analysis. Experimental data on the development of this scatterometry-based optical module and the subsequent validation of the key-point extraction method indicate a maximum mean absolute error of 0.0080 and a cosine similarity consistently above 0.9999. This study integrates image analysis and measurement techniques by optics, providing a more efficient pathway for key-point extraction in diffraction images, offering the potential for improving real-time process monitoring in the semiconductor manufacturing industry.
{"title":"Feature Extraction From Diffraction Images Using a Spatial Light Modulator in Scatterometry","authors":"Jinyang Li;Hung-Fei Kuo","doi":"10.1109/TSM.2024.3448458","DOIUrl":"10.1109/TSM.2024.3448458","url":null,"abstract":"The continuous miniaturization of semiconductor devices has increased the demand for advanced process control technologies. This process requires real-time measurement systems to monitor manufacturing parameters to ensure efficiency and high quality. This study introduces a novel optical module that uses a spatial light modulator to extract key-point intensity distributions from diffraction images in scatterometry. The efficacy of this method is demonstrated on a grating target with a pitch of 855 nm using a feature extraction algorithm that identifies key point locations based on calculated diffraction images. A particularly designed off-axis extraction pattern facilitates the acquisition of key-point intensity distributions. Moreover, incorporating a cylindrical lens into the optical setup reduces the image feature dimensionality, thereby decreasing the data storage space and enabling the output in a streamlined vector format conducive to further analysis. Experimental data on the development of this scatterometry-based optical module and the subsequent validation of the key-point extraction method indicate a maximum mean absolute error of 0.0080 and a cosine similarity consistently above 0.9999. This study integrates image analysis and measurement techniques by optics, providing a more efficient pathway for key-point extraction in diffraction images, offering the potential for improving real-time process monitoring in the semiconductor manufacturing industry.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"518-526"},"PeriodicalIF":2.3,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-23DOI: 10.1109/TSM.2024.3448359
Yi Liu;Wei-Te Lee;Hsueh-Ping Lu;Hung-Wen Chen
In the field of thin-film transistor liquid crystal display (TFT-LCD) manufacturing, the challenge of automated defect classification across multi-layered array processes is profound due to the intricate patterns involved. Traditional deep learning approaches, while promising, often fail to achieve high accuracy in cross-process recognition tasks. To address this gap, we propose a multi-modal learning approach that synergistically combines a knowledge engineering technique called Descriptive Embedding Generation (DEG) with a cross-modal contrastive learning strategy. Unlike conventional methods that primarily rely on visual data, our approach incorporates fine-grained descriptive information generated by DEG, enhancing the discriminative power of the learned model. The performance of this innovative training strategy is demonstrated through rigorous experiments, which show a notable accuracy improvement ranging from 0.92% to 7.89% over existing methods. Our approach has been validated by a leading TFT-LCD manufacturer in Taiwan, confirming its practical relevance and setting a new benchmark in cross-process and multi-product defect classification. This study not only advances the state of defect classification in smart manufacturing but also paves the way for future research in complex recognition tasks.
{"title":"A Novel Multi-Modal Learning Approach for Cross-Process Defect Classification in TFT-LCD Array Manufacturing","authors":"Yi Liu;Wei-Te Lee;Hsueh-Ping Lu;Hung-Wen Chen","doi":"10.1109/TSM.2024.3448359","DOIUrl":"10.1109/TSM.2024.3448359","url":null,"abstract":"In the field of thin-film transistor liquid crystal display (TFT-LCD) manufacturing, the challenge of automated defect classification across multi-layered array processes is profound due to the intricate patterns involved. Traditional deep learning approaches, while promising, often fail to achieve high accuracy in cross-process recognition tasks. To address this gap, we propose a multi-modal learning approach that synergistically combines a knowledge engineering technique called Descriptive Embedding Generation (DEG) with a cross-modal contrastive learning strategy. Unlike conventional methods that primarily rely on visual data, our approach incorporates fine-grained descriptive information generated by DEG, enhancing the discriminative power of the learned model. The performance of this innovative training strategy is demonstrated through rigorous experiments, which show a notable accuracy improvement ranging from 0.92% to 7.89% over existing methods. Our approach has been validated by a leading TFT-LCD manufacturer in Taiwan, confirming its practical relevance and setting a new benchmark in cross-process and multi-product defect classification. This study not only advances the state of defect classification in smart manufacturing but also paves the way for future research in complex recognition tasks.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"527-534"},"PeriodicalIF":2.3,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent decades, Scanning Acoustic Tomography (SAT) has become a vital technique for characterizing semiconductor devices in non-destructive evaluation. Precise and efficient segmentation of SAT images is crucial for detecting defects and assessing material properties in the semiconductor industry. However, current manual methods are often expensive and susceptible to human error. This study enhances the segmentation process of SAT images using the deep learning model SemiSA, which is fine-tuned from the Segment Anything model. In our experiments, SemiSA was trained and evaluated on a large-scale dataset from the Ohlabs TSAM-400 system, encompassing various semiconductor devices such as Flip Chip, Power Semiconductor, 6-inch and 12-inch Wafer, Transistor, and Multilayer Ceramic Capacitor. The results demonstrate that SemiSA significantly improves segmentation tasks across all types of SAT images of semiconductor devices. On average, there was a 17.89% enhancement in Dice Similarity Coefficient scores and a 24.26% improvement in Intersection over Union scores across all tasks. Additionally, this work also proposes an efficient framework tailored specifically for SAT images. The main objective of developing this segmentation tool is to provide researchers and experts with a valuable tool for advancing the semiconductor evaluation and quality control field. The code is available at https://github.com/ThuHa96/SemiSA.
近几十年来，扫描声断层扫描（SAT）已成为无损评估半导体器件特性的重要技术。对 SAT 图像进行精确、高效的分割对于半导体行业检测缺陷和评估材料特性至关重要。然而，目前的手动方法往往成本高昂，而且容易出现人为错误。本研究使用深度学习模型 SemiSA 增强了 SAT 图像的分割过程，该模型由 Segment Anything 模型微调而来。在我们的实验中，SemiSA 在来自 Ohlabs TSAM-400 系统的大规模数据集上进行了训练和评估，该数据集涵盖了各种半导体器件，如倒装芯片、功率半导体、6 英寸和 12 英寸晶圆、晶体管和多层陶瓷电容器。结果表明，SemiSA 显著改善了所有类型半导体器件 SAT 图像的分割任务。平均而言，在所有任务中，骰子相似系数得分提高了 17.89%，交叉比联合得分提高了 24.26%。此外，这项工作还提出了一个专门针对 SAT 图像的高效框架。开发该分割工具的主要目的是为研究人员和专家提供一个有价值的工具，以推动半导体评估和质量控制领域的发展。代码见 https://github.com/ThuHa96/SemiSA。
{"title":"Optimizing Scanning Acoustic Tomography Image Segmentation With Segment Anything Model for Semiconductor Devices","authors":"Thi Thu Ha Vu;Tan Hung Vo;Trong Nhan Nguyen;Jaeyeop Choi;Sudip Mondal;Junghwan Oh","doi":"10.1109/TSM.2024.3444850","DOIUrl":"10.1109/TSM.2024.3444850","url":null,"abstract":"In recent decades, Scanning Acoustic Tomography (SAT) has become a vital technique for characterizing semiconductor devices in non-destructive evaluation. Precise and efficient segmentation of SAT images is crucial for detecting defects and assessing material properties in the semiconductor industry. However, current manual methods are often expensive and susceptible to human error. This study enhances the segmentation process of SAT images using the deep learning model SemiSA, which is fine-tuned from the Segment Anything model. In our experiments, SemiSA was trained and evaluated on a large-scale dataset from the Ohlabs TSAM-400 system, encompassing various semiconductor devices such as Flip Chip, Power Semiconductor, 6-inch and 12-inch Wafer, Transistor, and Multilayer Ceramic Capacitor. The results demonstrate that SemiSA significantly improves segmentation tasks across all types of SAT images of semiconductor devices. On average, there was a 17.89% enhancement in Dice Similarity Coefficient scores and a 24.26% improvement in Intersection over Union scores across all tasks. Additionally, this work also proposes an efficient framework tailored specifically for SAT images. The main objective of developing this segmentation tool is to provide researchers and experts with a valuable tool for advancing the semiconductor evaluation and quality control field. The code is available at \u0000<uri>https://github.com/ThuHa96/SemiSA</uri>\u0000.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"591-601"},"PeriodicalIF":2.3,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-22DOI: 10.1109/TSM.2024.3447892
Min Zhai;Serena Calvelli;Haolian Shi;Marco Ricci;Stefano Laureti;Prabjit Singh;Haley Fu;Alexandre Locquet;D. S. Citrin
Conformal coatings are used to protect microelectronic circuitry and increasingly optoelectronics and photonics from detrimental effects of the environment, such as moisture, dust, gasses, and mechanical abrasion. The conventional approach to determine the mean time to failure of conformally coated microelectronic components is usually labor-intensive and time-consuming. We recently showed (Shi et al., 2024) that the quasi-optical approach terahertz (THz) time-of-flight tomography (TOFT) could in principle be used to map conformal-coating thickness over a sample of dimensions on the scale of square centimeters. In this study, we employ THz TOFT to characterize several conformal-coating types on microelectronic test samples in a nondestructive and noncontact manner. This study extends previous work on acrylic conformal coatings. THz TOFT is shown to be effective in the thickness characterization of silicone and acrylic conformal coatings, but not nanometric atomic-layer-deposition metal-oxide coating, which is too thin for the technique.
{"title":"Comparative Study of Nondestructive Mapping of Conformal-Coating Thickness on Microelectronics by Terahertz Time-of-Flight Tomography","authors":"Min Zhai;Serena Calvelli;Haolian Shi;Marco Ricci;Stefano Laureti;Prabjit Singh;Haley Fu;Alexandre Locquet;D. S. Citrin","doi":"10.1109/TSM.2024.3447892","DOIUrl":"10.1109/TSM.2024.3447892","url":null,"abstract":"Conformal coatings are used to protect microelectronic circuitry and increasingly optoelectronics and photonics from detrimental effects of the environment, such as moisture, dust, gasses, and mechanical abrasion. The conventional approach to determine the mean time to failure of conformally coated microelectronic components is usually labor-intensive and time-consuming. We recently showed (Shi et al., 2024) that the quasi-optical approach terahertz (THz) time-of-flight tomography (TOFT) could in principle be used to map conformal-coating thickness over a sample of dimensions on the scale of square centimeters. In this study, we employ THz TOFT to characterize several conformal-coating types on microelectronic test samples in a nondestructive and noncontact manner. This study extends previous work on acrylic conformal coatings. THz TOFT is shown to be effective in the thickness characterization of silicone and acrylic conformal coatings, but not nanometric atomic-layer-deposition metal-oxide coating, which is too thin for the technique.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"37 4","pages":"499-504"},"PeriodicalIF":2.3,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142212250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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