Pub Date : 2025-12-04DOI: 10.1109/JETCAS.2025.3640223
Jun-Wei Liang;Iris Hui-Ru Jiang;Kai-Hsiang Chiu;Tung-Yu Su
With the advancement of high-speed and energy-efficient optical interconnect and computation, photonic integrated circuits (PICs) have become a promising alternative to traditional CMOS circuits. A PIC can be synthesized by mapping the binary decision diagram (BDD) of target functions to optical switches and combiners. However, excessive signal attenuation along the light propagation may require extra optical-electrical signal conversion, thus introducing unwanted delays. In this paper, we aim to overcome this deficiency during logic synthesis: First, we optimize the signal efficiency factor by applying the concept of harmonic mean to optimize DC combiners. Second, we properly arrange these proposed techniques in an optimal sequence of operations to form our main framework. Furthermore, we propose partial harmonic mean to minimize the hardware cost under an efficiency factor constraint. Experimental results show that our framework outperforms the state of the art in terms of efficiency factor.
{"title":"p-Harrow: Optical Logic Synthesis for Efficiency Optimization via Partial Harmonic Mean and Integer Partition","authors":"Jun-Wei Liang;Iris Hui-Ru Jiang;Kai-Hsiang Chiu;Tung-Yu Su","doi":"10.1109/JETCAS.2025.3640223","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3640223","url":null,"abstract":"With the advancement of high-speed and energy-efficient optical interconnect and computation, photonic integrated circuits (PICs) have become a promising alternative to traditional CMOS circuits. A PIC can be synthesized by mapping the binary decision diagram (BDD) of target functions to optical switches and combiners. However, excessive signal attenuation along the light propagation may require extra optical-electrical signal conversion, thus introducing unwanted delays. In this paper, we aim to overcome this deficiency during logic synthesis: First, we optimize the signal efficiency factor by applying the concept of harmonic mean to optimize DC combiners. Second, we properly arrange these proposed techniques in an optimal sequence of operations to form our main framework. Furthermore, we propose partial harmonic mean to minimize the hardware cost under an efficiency factor constraint. Experimental results show that our framework outperforms the state of the art in terms of efficiency factor.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"80-90"},"PeriodicalIF":3.8,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chiplet technology has emerged as a transformative approach in integrated circuit design. Although it has attracted significant attention recently, there has been limited effort dedicated to clearly defining its concept, terminology, composition, and evolution phases etc. This survey paper gives a formal definition by proposing chiplet terminology and composition, name it as a new design methodology, then analyze over 200 recent publications from both academia and industry to establish chiplet as a technology domain composed of four distinct fields: chiplet-based SoC architecture, interconnect, EDA tools, and advanced packaging. For each field composing chiplets, the paper traces the technology development, analyze challenges, outline the evolution trend and challenges. This survey aims to provides an in-depth examination of chiplet domain and each field’s progress, offering insights drawn from literature analysis to outline the current and emerging landscape of chiplet technology.
{"title":"Survey of Chiplet Technology: SoC Architecture, Interconnect, EDA, and Advanced Packaging","authors":"Hongwei Liu;Yuan Du;Bo Pu;Guojun Yuan;Yuhang Liu;Linji Zheng;Pengchao Wang;An Yang;Yu Li;Chengming Yu;Fei Guo;Xiaoteng Zhao;Xuqiang Zheng;He Sun;Yongfu Li;Shaolin Xiang;Qinfen Hao","doi":"10.1109/JETCAS.2025.3636408","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3636408","url":null,"abstract":"Chiplet technology has emerged as a transformative approach in integrated circuit design. Although it has attracted significant attention recently, there has been limited effort dedicated to clearly defining its concept, terminology, composition, and evolution phases etc. This survey paper gives a formal definition by proposing chiplet terminology and composition, name it as a new design methodology, then analyze over 200 recent publications from both academia and industry to establish chiplet as a technology domain composed of four distinct fields: chiplet-based SoC architecture, interconnect, EDA tools, and advanced packaging. For each field composing chiplets, the paper traces the technology development, analyze challenges, outline the evolution trend and challenges. This survey aims to provides an in-depth examination of chiplet domain and each field’s progress, offering insights drawn from literature analysis to outline the current and emerging landscape of chiplet technology.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"514-536"},"PeriodicalIF":3.8,"publicationDate":"2025-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11265742","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-03DOI: 10.1109/JETCAS.2025.3628047
Juan Bonetti
Next-generation optical communication systems will require digital-to-analog converters (DACs) with bandwidths exceeding 100 GHz. To address this demand, several techniques have been proposed that interleave multiple DACs within a single circuit, introducing new challenges in digital signal processing. In this work, we revisit the principles of interleaved DAC architectures, commonly employed in high-speed converter design. We show that any interleaving scheme, whether in the time domain, frequency domain, or a hybrid of both, can be effectively modeled as a multiple-input multiple-output (MIMO) linear system. This unified framework not only captures the behavior of diverse interleaved architectures but also enables low-complexity digital pre-equalization through a simple MIMO filter. To further streamline implementation, we propose a general algorithm for constructing such equalizers, significantly reducing the design of the associated digital signal processor (DSP). Numerical simulations validate the theoretical framework and demonstrate the effectiveness of the proposed approach.
{"title":"Low-Complexity MIMO DSP for Jointly Time- and Frequency-Interleaved DACs in >100 GHz Single-Wavelength Optical Transceivers","authors":"Juan Bonetti","doi":"10.1109/JETCAS.2025.3628047","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3628047","url":null,"abstract":"Next-generation optical communication systems will require digital-to-analog converters (DACs) with bandwidths exceeding 100 GHz. To address this demand, several techniques have been proposed that interleave multiple DACs within a single circuit, introducing new challenges in digital signal processing. In this work, we revisit the principles of interleaved DAC architectures, commonly employed in high-speed converter design. We show that any interleaving scheme, whether in the time domain, frequency domain, or a hybrid of both, can be effectively modeled as a multiple-input multiple-output (MIMO) linear system. This unified framework not only captures the behavior of diverse interleaved architectures but also enables low-complexity digital pre-equalization through a simple MIMO filter. To further streamline implementation, we propose a general algorithm for constructing such equalizers, significantly reducing the design of the associated digital signal processor (DSP). Numerical simulations validate the theoretical framework and demonstrate the effectiveness of the proposed approach.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"67-79"},"PeriodicalIF":3.8,"publicationDate":"2025-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11224331","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/JETCAS.2025.3626703
Zahra Ghanaatian;Amin Shafiee;Mahdi Nikdast
Silicon photonics (SiPh) has quickly emerged as a leading technology for photonic integrated circuits, offering advantages such as low latency, low power consumption, and high bandwidth in different application domains from data communication to computation. Among different SiPh devices, Mach–Zehnder interferometers (MZIs) are highly attractive for applications such as modulators, switches, biosensors, and neural networks. However, MZIs are sensitive to fabrication-process variations (FPVs), which can significantly impact MZI performance even with minute changes in the device’s critical dimensions. To address this problem, we present a variation-aware design optimization method for MZIs to minimize optical response shift and changes in free spectral range (FSR), and maximize extinction ratio (ER) under FPVs. We develop detailed analytical models to accurately capture the impact of FPVs in MZIs. Leveraging these models, device layout and design parameters, such as waveguide width, are efficiently explored and optimized based on single-mode and multi-mode design considerations to improve device resilience under FPVs. The simulation results show that, compared to conventional MZIs, our optimized MZIs result in more than a 57% reduction in optical-response shift, as well as FSR and ER changes under FPVs. Moreover, the simulation results show great agreement with the measured optical response of fabricated MZIs. We also present a system-level case study of an MZI-based photonic neural network under FPVs, showcasing up to a 65% improvement in the network inferencing accuracy when using optimized MZIs.
{"title":"Robust-by-Design Silicon Photonic Mach–Zehnder Interferometers Under Fabrication Nonuniformities","authors":"Zahra Ghanaatian;Amin Shafiee;Mahdi Nikdast","doi":"10.1109/JETCAS.2025.3626703","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3626703","url":null,"abstract":"Silicon photonics (SiPh) has quickly emerged as a leading technology for photonic integrated circuits, offering advantages such as low latency, low power consumption, and high bandwidth in different application domains from data communication to computation. Among different SiPh devices, Mach–Zehnder interferometers (MZIs) are highly attractive for applications such as modulators, switches, biosensors, and neural networks. However, MZIs are sensitive to fabrication-process variations (FPVs), which can significantly impact MZI performance even with minute changes in the device’s critical dimensions. To address this problem, we present a variation-aware design optimization method for MZIs to minimize optical response shift and changes in free spectral range (FSR), and maximize extinction ratio (ER) under FPVs. We develop detailed analytical models to accurately capture the impact of FPVs in MZIs. Leveraging these models, device layout and design parameters, such as waveguide width, are efficiently explored and optimized based on single-mode and multi-mode design considerations to improve device resilience under FPVs. The simulation results show that, compared to conventional MZIs, our optimized MZIs result in more than a 57% reduction in optical-response shift, as well as FSR and ER changes under FPVs. Moreover, the simulation results show great agreement with the measured optical response of fabricated MZIs. We also present a system-level case study of an MZI-based photonic neural network under FPVs, showcasing up to a 65% improvement in the network inferencing accuracy when using optimized MZIs.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"52-66"},"PeriodicalIF":3.8,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-22DOI: 10.1109/JETCAS.2025.3624556
Zhenye Zhao;Fuhao Yu;Wei Jiang;Jin Sha
Forward error correction (FEC) techniques are widely used in various communication systems, including 4G/5G wireless communication, Internet, optical communication, etc. FEC en/decoders are normally implemented with silicon-based circuits and their power consumption and throughput are usually the crucial concerns. Photonic approaches have demonstrated extraordinary potential for some computation-hungry applications like neural networks. In this work, an on-chip electro-optical circuit is proposed to perform FEC decoding tasks with high integration potential and low power consumption characteristics. Leveraging optical computing-friendly algorithmic transformations and a meticulously crafted optical path design, an electro-optical decoder for Reed-Muller (RM) codes is presented. We show by simulation that our proposed decoders achieve a significant computational benefit in energy consumption compared to the standard Dumer’s recursive decoder without an appreciable performance penalty. This on-chip FEC decoder provides a potential solution for improving future FEC hardware with enhanced performance. It may be suitable for optical communication systems to lower the bit error rate at the front end.
{"title":"Electro-Optical Reed–Muller Code Decoders Based on Integrated Optics","authors":"Zhenye Zhao;Fuhao Yu;Wei Jiang;Jin Sha","doi":"10.1109/JETCAS.2025.3624556","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3624556","url":null,"abstract":"Forward error correction (FEC) techniques are widely used in various communication systems, including 4G/5G wireless communication, Internet, optical communication, etc. FEC en/decoders are normally implemented with silicon-based circuits and their power consumption and throughput are usually the crucial concerns. Photonic approaches have demonstrated extraordinary potential for some computation-hungry applications like neural networks. In this work, an on-chip electro-optical circuit is proposed to perform FEC decoding tasks with high integration potential and low power consumption characteristics. Leveraging optical computing-friendly algorithmic transformations and a meticulously crafted optical path design, an electro-optical decoder for Reed-Muller (RM) codes is presented. We show by simulation that our proposed decoders achieve a significant computational benefit in energy consumption compared to the standard Dumer’s recursive decoder without an appreciable performance penalty. This on-chip FEC decoder provides a potential solution for improving future FEC hardware with enhanced performance. It may be suitable for optical communication systems to lower the bit error rate at the front end.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"115-123"},"PeriodicalIF":3.8,"publicationDate":"2025-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of optical logic gates suitable for multi-stage processes is a central issue in emerging computational applications such as optical neural networks. In this work, we introduce and analyze a scheme for an all-optical AND logic gate, which allows achieving an almost ideal extinction ratio, a feature that simplifies cascaded architectures for complex operations such as multibit sums and multiplications. We analytically demonstrate how our scheme forces three logical states, namely ‘00’, ‘11’ and ‘10’, to be necessarily ideal in behavior. We also outline the conditions for ideal behavior of the remaining logical state ‘01’, which requires the use of semiconductor optical amplifiers (SOA) in their non-linear operations, by tuning the optical input and feeding current. Our numerical analysis on symmetrically balanced SOAs shows that there are multiple conditions enabling a very small output at logical ‘01’; also, our results suggest that those solutions are strongly influenced by the phase shifts induced in SOAs, which requires to avoid small $alpha $ factors. The performance outlined in our transitions are promising for the implementation of universal gates to be deployed in future architectures for neural optical computation.
{"title":"All-optical AND Logic Gate With High Extinction Ratio for Neural Network Hardware Implementation","authors":"Rita Asquini;Alessio Buzzin;Badrul Alam;Andrea Ceschini;Antonello Rosato;Massimo Panella","doi":"10.1109/JETCAS.2025.3623865","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3623865","url":null,"abstract":"The development of optical logic gates suitable for multi-stage processes is a central issue in emerging computational applications such as optical neural networks. In this work, we introduce and analyze a scheme for an all-optical AND logic gate, which allows achieving an almost ideal extinction ratio, a feature that simplifies cascaded architectures for complex operations such as multibit sums and multiplications. We analytically demonstrate how our scheme forces three logical states, namely ‘00’, ‘11’ and ‘10’, to be necessarily ideal in behavior. We also outline the conditions for ideal behavior of the remaining logical state ‘01’, which requires the use of semiconductor optical amplifiers (SOA) in their non-linear operations, by tuning the optical input and feeding current. Our numerical analysis on symmetrically balanced SOAs shows that there are multiple conditions enabling a very small output at logical ‘01’; also, our results suggest that those solutions are strongly influenced by the phase shifts induced in SOAs, which requires to avoid small <inline-formula> <tex-math>$alpha $ </tex-math></inline-formula> factors. The performance outlined in our transitions are promising for the implementation of universal gates to be deployed in future architectures for neural optical computation.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"106-114"},"PeriodicalIF":3.8,"publicationDate":"2025-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-13DOI: 10.1109/JETCAS.2025.3621067
Guillermo Da Silva Valdecasa;Jose A. Altabas;Jesper Bevensee Jensen;Tom K. Johansen
This work presents a monolithically integrated, analog-based quasi-coherent optical receiver, targeting the demands for increased efficiency in next-generation Passive Optical Networks (PONs). The receiver features an optical front-end including light coupling and combining structures, paired with balanced germanium (Ge) waveguide photodetectors. The electrical front-end is based on a common-base shunt-feedback linear transimpedance amplifier (TIA) and a high-speed envelope detector. Facilitated by the electronic–photonic integration, the optical and electrical front-ends are co-optimized, demonstrating a bandpass opto-electrical (O/E) bandwidth of 5–57 GHz with a TIA gain above 74 dB$Omega $ . Performance is reported at a setup-limited bitrate of 25 Gbps, achieving –31.5 dBm receiver sensitivity at a bit error rate (BER) of $1times 10^{-3}$ . By operating the receiver in single-sideband (SSB) mode, a sensitivity of –19 dBm (BER = $1times 10^{-3}$ ) is demonstrated for a 25 km standard single-mode fiber (SSMF) transmission. The reported performance represents an improvement over hybrid quasi-coherent receiver implementations, and validates the proposed receiver as a suitable upgrade to realize the full potential of existing PON deployments.
{"title":"Electronic–Photonic Integration of Quasi-Coherent Optical Receivers: Toward Efficient and Scalable Passive Optical Networks","authors":"Guillermo Da Silva Valdecasa;Jose A. Altabas;Jesper Bevensee Jensen;Tom K. Johansen","doi":"10.1109/JETCAS.2025.3621067","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3621067","url":null,"abstract":"This work presents a monolithically integrated, analog-based quasi-coherent optical receiver, targeting the demands for increased efficiency in next-generation Passive Optical Networks (PONs). The receiver features an optical front-end including light coupling and combining structures, paired with balanced germanium (Ge) waveguide photodetectors. The electrical front-end is based on a common-base shunt-feedback linear transimpedance amplifier (TIA) and a high-speed envelope detector. Facilitated by the electronic–photonic integration, the optical and electrical front-ends are co-optimized, demonstrating a bandpass opto-electrical (O/E) bandwidth of 5–57 GHz with a TIA gain above 74 dB<inline-formula> <tex-math>$Omega $ </tex-math></inline-formula>. Performance is reported at a setup-limited bitrate of 25 Gbps, achieving –31.5 dBm receiver sensitivity at a bit error rate (BER) of <inline-formula> <tex-math>$1times 10^{-3}$ </tex-math></inline-formula>. By operating the receiver in single-sideband (SSB) mode, a sensitivity of –19 dBm (BER = <inline-formula> <tex-math>$1times 10^{-3}$ </tex-math></inline-formula>) is demonstrated for a 25 km standard single-mode fiber (SSMF) transmission. The reported performance represents an improvement over hybrid quasi-coherent receiver implementations, and validates the proposed receiver as a suitable upgrade to realize the full potential of existing PON deployments.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"27-39"},"PeriodicalIF":3.8,"publicationDate":"2025-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-10DOI: 10.1109/JETCAS.2025.3619942
Chengpeng Xia;Haibo Zhang;Yawen Chen;Amanda S. Barnard
With the substantial increase in computing workload for deep learning applications, traditional electronic accelerators are facing growing constraints and approaching their practical limits. Silicon photonics has emerged as a promising technology for both communication and computation in accelerating deep learning workloads. Existing photonic accelerators focus on either designing monolithic photonic computing cores or using photonic interconnects with electronic cores for deep neural network (DNN) acceleration. However, the integration of photonic computing within many-core photonic interconnect architectures has not been extensively studied. In this paper, we propose a novel scalable chiplet-based photonic accelerator named SIPHON that leverages both photonic computing and communication for ultrafast and energy-efficient DNN training and inference. A photonic interconnection with dynamically configurable multiple communication modes is proposed to address the broad wavelength and bandwidth demands of general photonic computing cores. We design a photonic computing unit (PCU) for the multiply-accumulate operations and gradient computations in forward and backward propagations. A dataflow is developed to facilitate efficient data reuse and parallel computing by leveraging multiple communication modes. To validate SIPHON’s photonic computing, we prototype the optical platform using FPGA, RF, and photonic devices. Simulations on five deep learning models show that, compared with the GPU and the state-of-the-art optical-memristor-based backpropagation accelerators, SIPHON achieves up to $11.5times $ and $2.2times $ acceleration in time and $55.4times $ and $6.0times $ in energy efficiency for DNN training.
{"title":"SIPHON: Silicon Photonic Computing-Based Chiplet Accelerator for Deep Learning","authors":"Chengpeng Xia;Haibo Zhang;Yawen Chen;Amanda S. Barnard","doi":"10.1109/JETCAS.2025.3619942","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3619942","url":null,"abstract":"With the substantial increase in computing workload for deep learning applications, traditional electronic accelerators are facing growing constraints and approaching their practical limits. Silicon photonics has emerged as a promising technology for both communication and computation in accelerating deep learning workloads. Existing photonic accelerators focus on either designing monolithic photonic computing cores or using photonic interconnects with electronic cores for deep neural network (DNN) acceleration. However, the integration of photonic computing within many-core photonic interconnect architectures has not been extensively studied. In this paper, we propose a novel scalable chiplet-based photonic accelerator named SIPHON that leverages both photonic computing and communication for ultrafast and energy-efficient DNN training and inference. A photonic interconnection with dynamically configurable multiple communication modes is proposed to address the broad wavelength and bandwidth demands of general photonic computing cores. We design a photonic computing unit (PCU) for the multiply-accumulate operations and gradient computations in forward and backward propagations. A dataflow is developed to facilitate efficient data reuse and parallel computing by leveraging multiple communication modes. To validate SIPHON’s photonic computing, we prototype the optical platform using FPGA, RF, and photonic devices. Simulations on five deep learning models show that, compared with the GPU and the state-of-the-art optical-memristor-based backpropagation accelerators, SIPHON achieves up to <inline-formula> <tex-math>$11.5times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$2.2times $ </tex-math></inline-formula> acceleration in time and <inline-formula> <tex-math>$55.4times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$6.0times $ </tex-math></inline-formula> in energy efficiency for DNN training.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"91-105"},"PeriodicalIF":3.8,"publicationDate":"2025-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sequence alignment, a cornerstone application in bioinformatics, is critical for enabling personalized medicine and disease diagnostics. However, the rapid growth of genomic data has led to significant computational challenges, including limited throughput, high latency, and excessive data movement in current sequencing solutions. To address these issues, we propose Opto-Aligner, a high-performance and energy-efficient optical near-sensor accelerator framework tailored for multiple genetic tasks, mainly as DNA/RNA pre-alignment filtering in hyperdimensional space. Opto-Aligner harnesses Silicon Photonics’ promising efficiency and hyperdimensional computing (HDC) robustness to accelerate genome sequence alignment directly at the sensor level. We develop innovative microarchitectural and circuit-level solutions, including specialized hardware partitioning and mapping strategies, to overcome challenges inherent in photonic computing—our cross-layer design accounts for photonic device variability and noise, optimizing HDC algorithms for optical hardware constraints. Opto-Aligner significantly improves throughput and energy efficiency over leading electronic DNA aligners. Relative to the best published electronic aligner (BioHD-HAM), Opto-Aligner delivers a $5.7times $ higher single-die throughput (0.93 Mb s−1 vs. 0.163 Mb s−1) and a $3.0times 10 {^{{5}}}$ -fold reduction in energy–delay product, all with sub-nanosecond comparator latency and seamless scaling to multi-bit precision. Opto-Aligner effectively bridges the gap between the computational demands of genome alignment and the limitations of optical hardware.
序列比对是生物信息学的基础应用，对于实现个性化医疗和疾病诊断至关重要。然而，基因组数据的快速增长带来了重大的计算挑战，包括当前测序解决方案中有限的吞吐量、高延迟和过度的数据移动。为了解决这些问题，我们提出了一种高性能、节能的光学近传感器加速器框架Opto-Aligner，该框架专为多种遗传任务量身定制，主要用于超维空间中的DNA/RNA预校准过滤。Opto-Aligner利用硅光子学有前途的效率和超维计算（HDC）鲁棒性，直接在传感器水平上加速基因组序列校准。我们开发创新的微架构和电路级解决方案，包括专门的硬件分区和映射策略，以克服光子计算固有的挑战-我们的跨层设计考虑了光子器件的可变性和噪声，优化了光学硬件约束的HDC算法。与领先的电子DNA校准器相比，Opto-Aligner显着提高了吞吐量和能源效率。与已发表的最佳电子校准器（BioHD-HAM）相比，Opto-Aligner提供了5.7倍的单芯片吞吐量（0.93 Mb s - 1 vs. 0.163 Mb s - 1）和3.0倍的10{^{{5}}}$ $ 1的能量延迟产品减少，所有这些都具有亚纳秒比较器延迟和无缝缩放到多比特精度。Opto-Aligner有效地弥合了基因组比对的计算需求和光学硬件限制之间的差距。
{"title":"Opto-Aligner: Optical Near-Sensor Architecture for Accelerating DNA Pre-Alignment Filtering","authors":"Deniz Najafi;Hamza Errahmouni Barkam;Zahra Ghanaatian;Mehrdad Morsali;Hanning Chen;Tamoghno Das;Arman Roohi;Pietro Mercati;Mahdi Nikdast;Mohsen Imani;Shaahin Angizi","doi":"10.1109/JETCAS.2025.3619017","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3619017","url":null,"abstract":"Sequence alignment, a cornerstone application in bioinformatics, is critical for enabling personalized medicine and disease diagnostics. However, the rapid growth of genomic data has led to significant computational challenges, including limited throughput, high latency, and excessive data movement in current sequencing solutions. To address these issues, we propose Opto-Aligner, a high-performance and energy-efficient optical near-sensor accelerator framework tailored for multiple genetic tasks, mainly as DNA/RNA pre-alignment filtering in hyperdimensional space. Opto-Aligner harnesses Silicon Photonics’ promising efficiency and hyperdimensional computing (HDC) robustness to accelerate genome sequence alignment directly at the sensor level. We develop innovative microarchitectural and circuit-level solutions, including specialized hardware partitioning and mapping strategies, to overcome challenges inherent in photonic computing—our cross-layer design accounts for photonic device variability and noise, optimizing HDC algorithms for optical hardware constraints. Opto-Aligner significantly improves throughput and energy efficiency over leading electronic DNA aligners. Relative to the best published electronic aligner (BioHD-HAM), Opto-Aligner delivers a <inline-formula> <tex-math>$5.7times $ </tex-math></inline-formula> higher single-die throughput (0.93 Mb s<sup>−1</sup> vs. 0.163 Mb s<sup>−1</sup>) and a <inline-formula> <tex-math>$3.0times 10 {^{{5}}}$ </tex-math></inline-formula>-fold reduction in energy–delay product, all with sub-nanosecond comparator latency and seamless scaling to multi-bit precision. Opto-Aligner effectively bridges the gap between the computational demands of genome alignment and the limitations of optical hardware.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"124-136"},"PeriodicalIF":3.8,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-01DOI: 10.1109/JETCAS.2025.3616366
Krishnanunni R. A;Sooraj Ravindran
We propose and simulate a two-dimensional optical phased array using a silicon-based optical integrated circuit. Beam steering is achieved over a range of $11.73^{circ } times 11.9^{circ }$ at a fixed wavelength of 1550 nm. Steering along the transverse direction ($phi $ ) is accomplished using the phased array principle, while steering along the longitudinal direction ($theta $ ) is performed by routing light beams into optical phased arrays (OPAs) of variable grating period, coupled with the use of tunable grating antennas. The phased array principle and the operation of tunable grating antennas are implemented using carrier injection. Continuous beam steering is demonstrated in both directions at a fixed wavelength of 1550 nm.
我们提出并模拟了一种基于硅基光学集成电路的二维光学相控阵。在1550纳米的固定波长下，光束控制在$11.73^{circ } times 11.9^{circ }$范围内实现。横向转向（$phi $）是利用相控阵原理实现的，而纵向转向（$theta $）是通过将光束路由到可变光栅周期的光学相控阵（opa）中，再加上可调谐光栅天线的使用来实现的。利用载波注入实现了相控阵原理和可调谐光栅天线的工作。在1550 nm的固定波长下，演示了两个方向的连续光束转向。
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