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A 185-to-240 GHz SiGe Power Amplifier Using Non-Zero Base-Impedances for Power Gain and Output Power Optimizations 利用非零基极阻抗优化功率增益和输出功率的 185 至 240 GHz SiGe 功率放大器
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2024-01-16 DOI: 10.1109/JETCAS.2024.3355011
Xin Zhang;Nengxu Zhu;Fanyi Meng
It is commonly practiced in millimeter-wave and terahertz cascode amplifiers to enhance the power gain by shorting the base-impedance in the common-base transistor. However, it is found that the merit of high output power is not achieved simultaneously under the zero base-impedance scenarios. This paper theoretically analyzes the optimum designs by varying the base-impedances for power gain and output power level enhancement. In addition, numerically results are given to prove that non-zero base-impedances are key parameters towards gain and output power enhancements. Thus, each stages of the power amplifier must contain different and optimized base-impedances, based on their power gain and output power targets. To validate the design theory, a 220 GHz power amplifier is designed and fabricated in a 0.13- $mu text{m}$ SiGe technology. The measurement reveals that the amplifier achieves operation bandwidth of 185 to 240 GHz, power gain of 25 dB, and output $P_{mathrm {1dB}}/P_{mathrm {SAT}}$ of 7.3/9.5 dBm. It consumes 310~324 mW dc power and occupies a core area of 0.09 mm2.
毫米波和太赫兹级联放大器通常采用的方法是通过缩短共基晶体管中的基极阻抗来提高功率增益。但研究发现,在基极阻抗为零的情况下,并不能同时实现高输出功率的优点。本文从理论上分析了通过改变基极阻抗来提高功率增益和输出功率水平的最佳设计。此外,本文还给出了数值结果,证明非零基极阻抗是增益和输出功率增强的关键参数。因此,根据功率增益和输出功率目标,功率放大器的每一级都必须包含不同的优化基极阻抗。为了验证设计理论,我们设计了一款 220 GHz 功率放大器,并采用 0.13- $mu text{m}$ SiGe 技术进行制造。测量结果表明,该放大器的工作带宽为 185 至 240 GHz,功率增益为 25 dB,输出 $P_{mathrm {1dB}}/P_{mathrm {SAT}}$ 为 7.3/9.5 dBm。它的直流功耗为 310~324 mW,核心面积为 0.09 mm2。
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引用次数: 0
Broadband Millimeter-Wave GaAs Dual-Function Switching Attenuators With Low Insertion Loss and Large Attenuation Range 具有低插入损耗和大衰减范围的宽带毫米波砷化镓双功能开关衰减器
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2024-01-16 DOI: 10.1109/JETCAS.2024.3354778
Yutong Wang;Bo Li;Feng Lin;Houjun Sun;Hongjiang Wu;Chunliang Xu;Yuan Fang;Zhiqiang Li
This paper presents millimeter-wave (mmW) wide-band dual-function switching attenuator chips based on gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT). The broadband attenuator chips integrate the function of absorption single-pole-single-throw (SPST) switch by using balanced architecture. By analyzing the effects of transistor size and parasitic couplings from bias lines on mmW attenuator chips, the attenuation range is further improved. Based on the 90-nm GaAs pHEMT process, a 26~80 GHz attenuator chip I and a 40~110 GHz attenuator chip II were designed and measured, with chip sizes of $1.65ast 0.85$ mm2 and $1.30ast 0.80$ mm2, respectively. In the operating frequency band, the measured insertion losses (IL) of chips I and II are less than 2.8 dB and 2.2 dB, respectively, with the return losses (RL) of better than 12.4 dB and 11.6 dB. At the center frequency, the measured attenuation ranges of Chip I and II are $1.4sim 34.4$ dB and $1.1sim 30.9$ dB, respectively, and the 1dB compressed input power ( $IP_{mathrm {1dB}})$ of both chips are greater than 21 dBm. To the best of authors’ knowledge, this is the first wide-band mmW GaAs pHEMT attenuator chip integrated with absorption SPST switching function.
本文介绍了基于砷化镓(GaAs)拟态高电子迁移率晶体管(pHEMT)的毫米波(mmW)宽带双功能开关衰减器芯片。这种宽带衰减器芯片采用平衡式结构,集成了吸收式单刀单掷(SPST)开关的功能。通过分析晶体管尺寸和偏置线寄生耦合对毫米波衰减器芯片的影响,衰减范围得到了进一步改善。基于 90 纳米砷化镓 pHEMT 工艺,设计并测量了 26~80 GHz 衰减器芯片 I 和 40~110 GHz 衰减器芯片 II,芯片尺寸分别为 1.65/ast 0.85$ mm2 和 1.30/ast 0.80$ mm2。在工作频段,芯片 I 和芯片 II 测得的插入损耗(IL)分别小于 2.8 dB 和 2.2 dB,回波损耗(RL)分别优于 12.4 dB 和 11.6 dB。在中心频率,芯片 I 和芯片 II 的测量衰减范围分别为 1.4/sim 34.4$ dB 和 1.1/sim 30.9$ dB,两个芯片的 1dB 压缩输入功率 ( $IP_{mathrm {1dB}})$ 均大于 21 dBm。据作者所知,这是第一款集成了吸收 SPST 开关功能的宽带毫米波砷化镓 pHEMT 衰减器芯片。
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引用次数: 0
Design of Broadband Doherty Power Amplifier Based on Single Loop Load Modulation Network 基于单回路负载调制网络的宽带 Doherty 功率放大器设计
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2024-01-15 DOI: 10.1109/JETCAS.2024.3354503
Ge Bai;Zhijiang Dai;Jingsong Wang;Cheng Bi;Weimin Shi;Jingzhou Pang;Mingyu Li
This paper proposes a Doherty power amplifier (DPA) architecture with potential for wideband and high efficiency, denoted as single-loop load matching network DPA (SL-LMN). The conventional single combination node network is replaced by an SL-LMN, which adds a new current combination node. This architecture can bring new circuit design freedom, which expands the operating bandwidth of the load modulation network. Using the same prototype topology, the working mechanism of SL-LMN DPA is further illustrated based on three sets of comparative designs. To prove this theory, a broadband asymmetric DPA (ADPA) functioning over 1.9-2.9 GHz is developed and fabricated using two asymmetric GaN transistors. Under continuous wave excitation, the observed data indicates that the drain efficiency of this ADPA is 42.1%-68.9% at saturation and 45.5%-58.5% at 8 dB back-off, respectively. The ADPA has a maximum output power and saturated gain of 44–46 dBm and 6.8-10.9 dB, respectively.
本文提出了一种具有宽带和高效潜力的 Doherty 功率放大器(DPA)结构,称为单回路负载匹配网络 DPA(SL-LMN)。SL-LMN 增加了一个新的电流组合节点,取代了传统的单组合节点网络。这种结构带来了新的电路设计自由度,从而扩大了负载调制网络的工作带宽。使用相同的原型拓扑结构,基于三组对比设计进一步说明了 SL-LMN DPA 的工作机制。为了证明这一理论,我们使用两个非对称氮化镓晶体管开发并制造了一种工作频率为 1.9-2.9 GHz 的宽带非对称 DPA(ADPA)。在连续波激励下,观测数据表明,该 ADPA 的漏极效率在饱和时分别为 42.1%-68.9%,在 8 dB 关断时分别为 45.5%-58.5%。ADPA 的最大输出功率和饱和增益分别为 44-46 dBm 和 6.8-10.9 dB。
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引用次数: 0
A 39 GHz Doherty-Like Power Amplifier With 22dBm Output Power and 21% Power-Added Efficiency at 6dB Power Back-Off 在 6dB 功率衰减时输出功率为 22dBm 且功率附加效率为 21% 的 39 GHz 类多赫蒂功率放大器
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2024-01-08 DOI: 10.1109/JETCAS.2024.3351075
Lang Chen;Lisheng Chen;Depeng Sun;Yichuang Sun;Yulin Pan;Xi Zhu
The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical load-modulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use of a non- $50~Omega $ load at the isolation port of the output quadrature coupler. Moreover, magnitude and phase control networks are carefully designed to generate the specific magnitude and phase information for the designed S-LMBA. To demonstrate the proposed ideas, the S-LMBA is fabricated in a 45-nm CMOS SOI technology. At 39 GHz, a 22.1 dBm saturated output power ( $text{P}_{mathrm {sat}}$ ) with a maximum power-added efficiency (PAE) of 25.7% is achieved. In addition, 1.68 times drain efficiency enhancement is obtained over an ideal Class-B operation, when the designed S-LMBA is operated at 6 dB power back-off. An average output power of 13.1 dBm with a PAE of 14.4% at an error vector magnitude (EVM $_{mathrm {rms}}$ ) above -22.5 dB and adjacent channel power ratio (ACPR) of -23 dBc is also achieved, when a 200 MHz single carrier 64-quadrature-amplitude-modulation (QAM) signal is used. Including all testing pads, the footprint of the designed S-LMBA is only 1.56 mm2.
本作品介绍了一种用于毫米波(mm-wave)应用的类 Doherty 功率放大器的设计。所设计的功率放大器采用了新颖的对称负载调制平衡放大器(S-LMBA)结构。这种设计的优势在于最大限度地减少了经典 LMBA 方法中经常遇到的不期望的阻抗相互作用。这种相互作用通常是由于在输出正交耦合器的隔离端口使用了非 50~Omega $ 负载。此外,还精心设计了幅值和相位控制网络,以便为所设计的 S-LMBA 生成特定的幅值和相位信息。为了证明所提出的想法,S-LMBA 采用 45 纳米 CMOS SOI 技术制造。在 39 GHz 频率下,实现了 22.1 dBm 的饱和输出功率($text{P}_{mathrm {sat}}$),最大功率附加效率(PAE)为 25.7%。此外,当所设计的 S-LMBA 在 6 dB 功率衰减条件下工作时,其漏极效率比理想的 Class-B 工作方式提高了 1.68 倍。当使用 200 MHz 单载波 64-quadrature-amplitude-modulation (QAM) 信号时,平均输出功率为 13.1 dBm,PAE 为 14.4%,误差矢量幅度(EVM $_{mathrm {rms}}$ )高于 -22.5 dB,相邻信道功率比(ACPR)为 -23 dBc。包括所有测试垫在内,所设计的 S-LMBA 的占地面积仅为 1.56 平方毫米。
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引用次数: 0
Guest Editorial Dynamical Neuro-AI Learning Systems: Devices, Circuits, Architecture and Algorithms 客座编辑 动态神经-人工智能学习系统:设备、电路、架构和算法
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2023-12-28 DOI: 10.1109/JETCAS.2023.3343932
Jason K. Eshraghian;Arindam Basu;Corey Lammie;Shih-Chii Liu;Priydarshini Panda
This Special Issue of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to demonstrating the latest research progress on dynamical neuro-artificial intelligence (AI) learning systems that bridge the gap between devices, circuits, architectures, and algorithms. The growing demand for AI has spurred the development of systems that: 1) co-localize computation and memory; 2) enhance circuits and devices optimized for operations prevalent in deep learning; and 3) implement lightweight and compressed machine learning models thereby achieving greater accuracy with less resources.
本期《IEEE 电路与系统新兴选题期刊》(JETCAS)特刊致力于展示动态神经人工智能(AI)学习系统的最新研究进展,这些系统是设备、电路、架构和算法之间的桥梁。对人工智能日益增长的需求推动了以下系统的发展:1)共同定位计算和内存;2)增强针对深度学习中普遍存在的操作进行优化的电路和设备;3)实施轻量级压缩机器学习模型,从而以更少的资源实现更高的精度。
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引用次数: 0
IEEE Circuits and Systems Society Information 电气和电子工程师学会电路与系统协会信息
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2023-12-28 DOI: 10.1109/JETCAS.2023.3340568
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引用次数: 0
IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information 电气和电子工程师学会电路与系统新专题与选题期刊》出版信息
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2023-12-28 DOI: 10.1109/JETCAS.2023.3340572
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引用次数: 0
IEEE Journal on Emerging and Selected Topics in Circuits and Systems Information for Authors IEEE 《电路与系统新兴选题》期刊 作者须知
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2023-12-28 DOI: 10.1109/JETCAS.2023.3340570
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引用次数: 0
TechRxiv: Share Your Preprint Research with the World! TechRxiv:与世界分享您的预印本研究成果!
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2023-12-28 DOI: 10.1109/JETCAS.2023.3345229
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引用次数: 0
Low-Loss and Compact Millimeter-Wave Silicon-Based Filters: Overview, New Developments in Silicon-on-Insulator Technology, and Future Trends 低损耗和紧凑型毫米波硅基滤波器:概览、绝缘体上硅技术的新发展和未来趋势
IF 4.6 2区 工程技术 Q1 Engineering Pub Date : 2023-12-21 DOI: 10.1109/JETCAS.2023.3345476
Robert Nericua;Ke Wang;He Zhu;Roberto Gómez-García;Xi Zhu
This paper presents an overview of Silicon-based millimeter-wave (mm-wave) passive devices for bandpass and bandstop filtering applications, while also reporting originally-conceived filter developments and future trends. First of all, the state-of-the-art on mm-wave low-loss bandpass filters (BPFs) is covered, and new BPF designs are shown. The engineered BPFs employ a center-tapped ring architecture with shunt-connected capacitors to realize a standard 2nd-order baseline BPF design, which is subsequently scaled to 30-GHz and 60-GHz operational frequencies. To increase the selectivity as well as the stopband rejection levels of this baseline BPF, the in-series cascade connection of the baseline BPF units is used for a higher-order BPF realization. For experimental-validation purposes, a total of four mm-wave BPFs based on these design strategies are implemented, fabricated in 45-nm Silicon-on-Insulator (SOI) complementary-metal-oxide-semiconductor-(CMOS) technology, and tested. Afterward, a review of Silicon-based-integrated bandstop filters (BSFs) operating in the mm-wave region is provided, which includes both reflective-type and reflectionless/absorptive filter realizations for RF-interference-suppression in highly-congested electromagnetic (EM) environments. Finally, future research trends in the Silicon-based-integrated filter area are discussed. They are expected to play a key role in the development of modern radio-frequency (RF) front-ends for emerging beyond 5G and EM-sensing scenarios.
本文概述了用于带通和带阻滤波器应用的硅基毫米波(mm-wave)无源器件,同时还报告了最初设想的滤波器发展情况和未来趋势。首先,介绍了毫米波低损耗带通滤波器(BPF)的最新技术,并展示了新的 BPF 设计。所设计的带通滤波器采用了带并联电容器的中心抽头环形结构,实现了标准的二阶基线带通滤波器设计,随后将其扩展到 30 千兆赫和 60 千兆赫的工作频率。为了提高基线 BPF 的选择性和阻带抑制水平,基线 BPF 单元的串联级联被用于实现高阶 BPF。为了进行实验验证,基于这些设计策略共实现了四个毫米波 BPF,并在 45 纳米硅绝缘体(SOI)互补金属氧化物半导体(CMOS)技术中进行了制造和测试。随后,回顾了在毫米波区域工作的硅基集成带阻滤波器(BSF),包括反射型和无反射/吸收型滤波器,用于在高度拥挤的电磁(EM)环境中抑制射频干扰。最后,讨论了硅基集成滤波器领域的未来研究趋势。预计它们将在为新兴的 5G 和电磁传感场景开发现代射频(RF)前端中发挥关键作用。
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引用次数: 0
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IEEE Journal on Emerging and Selected Topics in Circuits and Systems
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