Pub Date : 2023-12-21DOI: 10.1109/JETCAS.2023.3345358
Chun Wang;Pin-Chun Chiu;Chun-Lin Ko;Sheng-Hsiang Tseng;Chun-Hsing Li
A 340-GHz compact terahertz (THz) amplifier-frequency-multiplier chain (AMC) offering a full 360° phase shifting range for phased-array applications is proposed in this paper. The AMC comprises an 85 -GHz phase-shifter-embedded ( $Delta varphi $ -embedded) power amplifier (PA) and a high-output-power frequency quadrupler (FQ). The PA is equipped with multifunctional impedance matching networks (M-IMNs) that can simultaneously provide balun, impedance transformation, and phase-shifting functions. Analytic expressions have been derived to provide design guidelines for the M-IMNs. With the integrated M-IMNs, the proposed PA can concurrently deliver high output power and a phase shift exceeding 90° in a compact chip area. The proposed FQ can achieve optimal impedance matching at second and fourth harmonic frequencies, leading to the output power enhancement of 2.6 dB. Furthermore, the output phase of the PA is quadrupled by the FQ, resulting in the output signal of the AMC with a full 360° phase-shifting capability. A measurement setup for characterizing the phase of a THz signal is also presented. Implemented in a 40-nm CMOS technology without ultra-thick metal layers available, the proposed THz AMC achieves a peak output power of −3.5 dBm at 368 GHz with a conversion gain of 1.8 dB and a 3-dB bandwidth from 340 to 376 GHz. The output phase can continuously vary over 360° within the 324 to 346 GHz frequency range. The phase noise of the output signal at 346 GHz is −105 dBc/Hz at a 10-MHz offset frequency. The proposed 340-GHz AMC consumes 215.1 mW from a 0.9-V supply.
{"title":"A 340-GHz THz Amplifier-Frequency-Multiplier Chain With 360° Phase-Shifting Range and its Phase Characterization","authors":"Chun Wang;Pin-Chun Chiu;Chun-Lin Ko;Sheng-Hsiang Tseng;Chun-Hsing Li","doi":"10.1109/JETCAS.2023.3345358","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3345358","url":null,"abstract":"A 340-GHz compact terahertz (THz) amplifier-frequency-multiplier chain (AMC) offering a full 360° phase shifting range for phased-array applications is proposed in this paper. The AMC comprises an 85 -GHz phase-shifter-embedded (\u0000<inline-formula> <tex-math>$Delta varphi $ </tex-math></inline-formula>\u0000-embedded) power amplifier (PA) and a high-output-power frequency quadrupler (FQ). The PA is equipped with multifunctional impedance matching networks (M-IMNs) that can simultaneously provide balun, impedance transformation, and phase-shifting functions. Analytic expressions have been derived to provide design guidelines for the M-IMNs. With the integrated M-IMNs, the proposed PA can concurrently deliver high output power and a phase shift exceeding 90° in a compact chip area. The proposed FQ can achieve optimal impedance matching at second and fourth harmonic frequencies, leading to the output power enhancement of 2.6 dB. Furthermore, the output phase of the PA is quadrupled by the FQ, resulting in the output signal of the AMC with a full 360° phase-shifting capability. A measurement setup for characterizing the phase of a THz signal is also presented. Implemented in a 40-nm CMOS technology without ultra-thick metal layers available, the proposed THz AMC achieves a peak output power of −3.5 dBm at 368 GHz with a conversion gain of 1.8 dB and a 3-dB bandwidth from 340 to 376 GHz. The output phase can continuously vary over 360° within the 324 to 346 GHz frequency range. The phase noise of the output signal at 346 GHz is −105 dBc/Hz at a 10-MHz offset frequency. The proposed 340-GHz AMC consumes 215.1 mW from a 0.9-V supply.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-18DOI: 10.1109/JETCAS.2023.3344510
Yuetong Lyu;Changwenquan Song;Pei Qin;Liang Wu
Conventional transformer-based magnetic tuning has demonstrated dual-band or even multi-band operation for voltage-controlled oscillators (VCOs). However, the destructive magnetic coupling employed introduces implicit loss to the transformer thus degrading its quality factor (Q), and achieves a continuous frequency coverage resulting in inferior performance. To address this issue, this paper proposes a constructive switched magnetic coupling (CSMC) technique, realizing dual-band operation with the Q improvement into one band due to the in-phase coupling and the explicit switch. For validation, a transformer employing the CSMC technique is designed and deployed in a dual-band VCO design. Fabricated in a 65-nm CMOS process, the VCO is measured with an oscillation frequency range of 37.8%, from 11.3 to 16.6 GHz, while consuming 2.5-mW from a 0.65-V voltage supply. Within the entire frequency coverage, the measured phase noise ranges from −129.6 to −123.7 at 10-MHz offset, resulting in FoM of 186-192.1 dBc/Hz. The core area of the chip is $0.43times 0.25$ mm2 excluding pads.
{"title":"A 11.3–16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS","authors":"Yuetong Lyu;Changwenquan Song;Pei Qin;Liang Wu","doi":"10.1109/JETCAS.2023.3344510","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3344510","url":null,"abstract":"Conventional transformer-based magnetic tuning has demonstrated dual-band or even multi-band operation for voltage-controlled oscillators (VCOs). However, the destructive magnetic coupling employed introduces implicit loss to the transformer thus degrading its quality factor (Q), and achieves a continuous frequency coverage resulting in inferior performance. To address this issue, this paper proposes a constructive switched magnetic coupling (CSMC) technique, realizing dual-band operation with the Q improvement into one band due to the in-phase coupling and the explicit switch. For validation, a transformer employing the CSMC technique is designed and deployed in a dual-band VCO design. Fabricated in a 65-nm CMOS process, the VCO is measured with an oscillation frequency range of 37.8%, from 11.3 to 16.6 GHz, while consuming 2.5-mW from a 0.65-V voltage supply. Within the entire frequency coverage, the measured phase noise ranges from −129.6 to −123.7 at 10-MHz offset, resulting in FoM of 186-192.1 dBc/Hz. The core area of the chip is \u0000<inline-formula> <tex-math>$0.43times 0.25$ </tex-math></inline-formula>\u0000 mm2 excluding pads.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-07DOI: 10.1109/JETCAS.2023.3340957
Sudipta Chakraborty;Gayatri Neeharika Sreepada;Michael Heimlich;Anand K. Verma
This work reports three designs of transverse resonance (TR)-based high-performance compact 5-pole Butterworth low-pass filters (TR-LPFs) at the cut-off frequency ( $f_{c}$ ) 10.5 GHz in $0.15~mu text{m}$ Gallium Arsenide (GaAs) pHEMT technology, with a chip size of 0.82 mm $times0.87$ mm. Two fabricated TR-LPFs have 20 dB, 30 dB, 40 dB, and 50 dB attenuation levels with rejection bandwidths of (54 GHz, 54 GHz), (32 GHz, 52 GHz), (31 GHz, 50 GHz), and (18.5 GHz, 27 GHz) respectively, and insertion loss of 0.5 dB and 0.6 dB. The TR-LPF is a microstrip-based design, so unlike the lumped elements-based design, it could be designed and fabricated in the GaAs, and other technologies even at millimeter-wave frequencies. Such high performance LPF, using microstrip on a GaAs chip is not reported in the open literature.
{"title":"Compact Transverse-Resonance Low-Pass Filter With Wide Stop-Band Rejection Implemented in Gallium Arsenide Technology","authors":"Sudipta Chakraborty;Gayatri Neeharika Sreepada;Michael Heimlich;Anand K. Verma","doi":"10.1109/JETCAS.2023.3340957","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3340957","url":null,"abstract":"This work reports three designs of transverse resonance (TR)-based high-performance compact 5-pole Butterworth low-pass filters (TR-LPFs) at the cut-off frequency (\u0000<inline-formula> <tex-math>$f_{c}$ </tex-math></inline-formula>\u0000) 10.5 GHz in \u0000<inline-formula> <tex-math>$0.15~mu text{m}$ </tex-math></inline-formula>\u0000 Gallium Arsenide (GaAs) pHEMT technology, with a chip size of 0.82 mm \u0000<inline-formula> <tex-math>$times0.87$ </tex-math></inline-formula>\u0000 mm. Two fabricated TR-LPFs have 20 dB, 30 dB, 40 dB, and 50 dB attenuation levels with rejection bandwidths of (54 GHz, 54 GHz), (32 GHz, 52 GHz), (31 GHz, 50 GHz), and (18.5 GHz, 27 GHz) respectively, and insertion loss of 0.5 dB and 0.6 dB. The TR-LPF is a microstrip-based design, so unlike the lumped elements-based design, it could be designed and fabricated in the GaAs, and other technologies even at millimeter-wave frequencies. Such high performance LPF, using microstrip on a GaAs chip is not reported in the open literature.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140123541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-16DOI: 10.1109/JETCAS.2023.3330832
Marco Rasetto;Qingzhou Wan;Himanshu Akolkar;Feng Xiong;Bertram Shi;Ryad Benosman
Memristors have emerged as a promising technology for efficient neuromorphic architectures owing to their ability to act as programmable synapses, combining processing and memory into a single device. Although they are most commonly used for static encoding of synaptic weights, recent work has begun to investigate the use of their dynamical properties, such as Short Term Plasticity (STP), to integrate events over time in event-based architectures. However, we are still far from completely understanding the range of possible behaviors and how they might be exploited in neuromorphic computation. This work focuses on a newly developed Li $_{text {x}}$ WO $_{text {3}}$ -based three-terminal memristor that exhibits tunable STP and a conductance response modeled by a double exponential decay. We derive a stochastic model of the device from experimental data and investigate how device stochasticity, STP, and the double exponential decay affect accuracy in a hierarchy of time-surfaces (HOTS) architecture. We found that the device’s stochasticity does not affect accuracy, that STP can reduce the effect of salt and pepper noise in signals from event-based sensors, and that the double exponential decay improves accuracy by integrating temporal information over multiple time scales. Our approach can be generalized to study other memristive devices to build a better understanding of how control over temporal dynamics can enable neuromorphic engineers to fine-tune devices and architectures to fit their problems at hand.
忆阻器能够充当可编程的突触，将处理和记忆功能整合到单个设备中，因此已成为高效神经形态架构的一项前景广阔的技术。虽然晶闸管最常用于对突触权重进行静态编码，但最近的研究工作已开始研究如何利用其动态特性，如短期可塑性（STP），在基于事件的架构中整合随时间变化的事件。然而，我们还远远没有完全了解可能的行为范围以及如何在神经形态计算中利用这些行为。这项工作的重点是新开发的基于 Li $_{text {x}}$ WO $_{text {3}}$ 的三端忆阻器，它具有可调的 STP 和以双指数衰减为模型的电导响应。我们根据实验数据推导出了该器件的随机模型，并研究了器件随机性、STP 和双指数衰减如何影响分层时间表面（HOTS）架构的精度。我们发现，设备的随机性不会影响准确性，STP 可以减少基于事件的传感器信号中的椒盐噪声的影响，而双指数衰减则可以通过整合多个时间尺度上的时间信息来提高准确性。我们的方法可以推广到对其他记忆器件的研究中，从而更好地理解对时间动态的控制如何使神经形态工程师能够对器件和架构进行微调，以适应手头的问题。
{"title":"Building Time-Surfaces by Exploiting the Complex Volatility of an ECRAM Memristor","authors":"Marco Rasetto;Qingzhou Wan;Himanshu Akolkar;Feng Xiong;Bertram Shi;Ryad Benosman","doi":"10.1109/JETCAS.2023.3330832","DOIUrl":"https://doi.org/10.1109/JETCAS.2023.3330832","url":null,"abstract":"Memristors have emerged as a promising technology for efficient neuromorphic architectures owing to their ability to act as programmable synapses, combining processing and memory into a single device. Although they are most commonly used for static encoding of synaptic weights, recent work has begun to investigate the use of their dynamical properties, such as Short Term Plasticity (STP), to integrate events over time in event-based architectures. However, we are still far from completely understanding the range of possible behaviors and how they might be exploited in neuromorphic computation. This work focuses on a newly developed Li\u0000<inline-formula> <tex-math>$_{text {x}}$ </tex-math></inline-formula>\u0000WO\u0000<inline-formula> <tex-math>$_{text {3}}$ </tex-math></inline-formula>\u0000-based three-terminal memristor that exhibits tunable STP and a conductance response modeled by a double exponential decay. We derive a stochastic model of the device from experimental data and investigate how device stochasticity, STP, and the double exponential decay affect accuracy in a hierarchy of time-surfaces (HOTS) architecture. We found that the device’s stochasticity does not affect accuracy, that STP can reduce the effect of salt and pepper noise in signals from event-based sensors, and that the double exponential decay improves accuracy by integrating temporal information over multiple time scales. Our approach can be generalized to study other memristive devices to build a better understanding of how control over temporal dynamics can enable neuromorphic engineers to fine-tune devices and architectures to fit their problems at hand.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10320285","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.1109/JETCAS.2023.3330428
Mohammed A. Alhartomi;Mohd Tasleem Khan;Saeed Alzahrani;Ahmed Alzahmi;Rafi Ahamed Shaik;Jinti Hazarika;Ruwaybih Alsulami;Abdulaziz Alotaibi;Meshal Al-Harthi
Long short-term memory (LSTM) networks are extensively used in various sequential learning tasks, including speech recognition. Their significance in real-world applications has prompted the demand for cost-effective and power-efficient designs. This paper introduces LSTM architectures based on distributed arithmetic (DA), utilizing circulant and block-circulant matrix-vector multiplications (MVMs) for network compression. The quantized weights-oriented approach for training circulant and block-circulant matrices is considered. By formulating fixed-point circulant/block-circulant MVMs, we explore the impact of kernel size on accuracy. Our DA-based approach employs shared full and partial methods of add-store/store-add followed by a select unit to realize an MVM. It is then coupled with a multi-partial strategy to reduce complexity for larger kernel sizes. Further complexity reduction is achieved by optimizing decoders of multiple select units. Pipelining in add-store enhances speed at the expense of a few pipelined registers. The results of the field-programmable gate array showcase the superiority of our proposed architectures based on the partial store-add method, delivering reductions of 98.71% in DSP slices, 33.59% in slice look-up tables, 13.43% in flip-flops, and 29.76% in power compared to the state-of-the-art.
{"title":"Low-Area and Low-Power VLSI Architectures for Long Short-Term Memory Networks","authors":"Mohammed A. Alhartomi;Mohd Tasleem Khan;Saeed Alzahrani;Ahmed Alzahmi;Rafi Ahamed Shaik;Jinti Hazarika;Ruwaybih Alsulami;Abdulaziz Alotaibi;Meshal Al-Harthi","doi":"10.1109/JETCAS.2023.3330428","DOIUrl":"10.1109/JETCAS.2023.3330428","url":null,"abstract":"Long short-term memory (LSTM) networks are extensively used in various sequential learning tasks, including speech recognition. Their significance in real-world applications has prompted the demand for cost-effective and power-efficient designs. This paper introduces LSTM architectures based on distributed arithmetic (DA), utilizing circulant and block-circulant matrix-vector multiplications (MVMs) for network compression. The quantized weights-oriented approach for training circulant and block-circulant matrices is considered. By formulating fixed-point circulant/block-circulant MVMs, we explore the impact of kernel size on accuracy. Our DA-based approach employs shared full and partial methods of add-store/store-add followed by a select unit to realize an MVM. It is then coupled with a multi-partial strategy to reduce complexity for larger kernel sizes. Further complexity reduction is achieved by optimizing decoders of multiple select units. Pipelining in add-store enhances speed at the expense of a few pipelined registers. The results of the field-programmable gate array showcase the superiority of our proposed architectures based on the partial store-add method, delivering reductions of 98.71% in DSP slices, 33.59% in slice look-up tables, 13.43% in flip-flops, and 29.76% in power compared to the state-of-the-art.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135503788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-06DOI: 10.1109/JETCAS.2023.3330432
Fabrizio Ottati;Chang Gao;Qinyu Chen;Giovanni Brignone;Mario R. Casu;Jason K. Eshraghian;Luciano Lavagno
As deep learning models scale, they become increasingly competitive from domains spanning from computer vision to natural language processing; however, this happens at the expense of efficiency since they require increasingly more memory and computing power. The power efficiency of the biological brain outperforms any large-scale deep learning (DL) model; thus, neuromorphic computing tries to mimic the brain operations, such as spike-based information processing, to improve the efficiency of DL models. Despite the benefits of the brain, such as efficient information transmission, dense neuronal interconnects, and the co-location of computation and memory, the available biological substrate has severely constrained the evolution of biological brains. Electronic hardware does not have the same constraints; therefore, while modeling spiking neural networks (SNNs) might uncover one piece of the puzzle, the design of efficient hardware backends for SNNs needs further investigation, potentially taking inspiration from the available work done on the artificial neural networks (ANNs) side. As such, when is it wise to look at the brain while designing new hardware, and when should it be ignored? To answer this question, we quantitatively compare the digital hardware acceleration techniques and platforms of ANNs and SNNs. As a result, we provide the following insights: (i) ANNs currently process static data more efficiently, (ii) applications targeting data produced by neuromorphic sensors, such as event-based cameras and silicon cochleas, need more investigation since the behavior of these sensors might naturally fit the SNN paradigm, and (iii) hybrid approaches combining SNNs and ANNs might lead to the best solutions and should be investigated further at the hardware level, accounting for both efficiency and loss optimization.
{"title":"To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration","authors":"Fabrizio Ottati;Chang Gao;Qinyu Chen;Giovanni Brignone;Mario R. Casu;Jason K. Eshraghian;Luciano Lavagno","doi":"10.1109/JETCAS.2023.3330432","DOIUrl":"10.1109/JETCAS.2023.3330432","url":null,"abstract":"As deep learning models scale, they become increasingly competitive from domains spanning from computer vision to natural language processing; however, this happens at the expense of efficiency since they require increasingly more memory and computing power. The power efficiency of the biological brain outperforms any large-scale deep learning (DL) model; thus, neuromorphic computing tries to mimic the brain operations, such as spike-based information processing, to improve the efficiency of DL models. Despite the benefits of the brain, such as efficient information transmission, dense neuronal interconnects, and the co-location of computation and memory, the available biological substrate has severely constrained the evolution of biological brains. Electronic hardware does not have the same constraints; therefore, while modeling spiking neural networks (SNNs) might uncover one piece of the puzzle, the design of efficient hardware backends for SNNs needs further investigation, potentially taking inspiration from the available work done on the artificial neural networks (ANNs) side. As such, when is it wise to look at the brain while designing new hardware, and when should it be ignored? To answer this question, we quantitatively compare the digital hardware acceleration techniques and platforms of ANNs and SNNs. As a result, we provide the following insights: (i) ANNs currently process static data more efficiently, (ii) applications targeting data produced by neuromorphic sensors, such as event-based cameras and silicon cochleas, need more investigation since the behavior of these sensors might naturally fit the SNN paradigm, and (iii) hybrid approaches combining SNNs and ANNs might lead to the best solutions and should be investigated further at the hardware level, accounting for both efficiency and loss optimization.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135500935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Biological neurons exhibit rich and complex nonlinear dynamics, which are computationally expensive and area/power hungry for hardware implementation. This paper presents a mathematical analysis and hardware realization of neural networks using a nonlinear neuron model that utilizes two excitable systems operating at different timescales. The neuron consists of a mixed-feedback system operating at multiple timescales to exhibit a variety of modalities that resemble the biophysical mechanisms found in neurophysiology. The single neuron dynamics emerge from four voltage-controlled current sources and feature spiking and bursting output modes that can be controlled using tunable parameters. The bifurcation structures of the neuron, modeled as a 4D dynamical system, illustrate the roles of sources acting on different timescales in shaping neural dynamics. A comprehensive understanding of the system’s dynamic behavior is obtained by studying the state space variables and performing bifurcation analysis on the different parameters. The model is implemented to a 1mm x 2mm prototype chip utilizing the 180nm CMOS process. Each neural network consists of 1 isolated test neuron and 5 fully connected neurons using 20 synapses. By carefully selecting bias voltages according to the I-V characterization curves, the neurons are shown to exhibit spike, burst, and burst excitable behavior. Multiple small-scale neural networks with inhibitory or excitatory synapses were verified to achieve coupled rhythms with neuron bursts in-phase or out-of-phase. To demonstrate an application, the generated burst waveforms from the 4-neuron network were used to form a Central Pattern Generator (CPG) for locomotion control of the four legs of the Petoi, a quadruped robot, enabling the bot to jump successfully.
{"title":"BioNN: Bio-Mimetic Neural Networks on Hardware Using Nonlinear Multi-Timescale Mixed-Feedback Control for Neuromodulatory Bursting Rhythms","authors":"Kangni Liu;Shahin Hashemkhani;Jonathan Rubin;Rajkumar Kubendran","doi":"10.1109/JETCAS.2023.3330084","DOIUrl":"10.1109/JETCAS.2023.3330084","url":null,"abstract":"Biological neurons exhibit rich and complex nonlinear dynamics, which are computationally expensive and area/power hungry for hardware implementation. This paper presents a mathematical analysis and hardware realization of neural networks using a nonlinear neuron model that utilizes two excitable systems operating at different timescales. The neuron consists of a mixed-feedback system operating at multiple timescales to exhibit a variety of modalities that resemble the biophysical mechanisms found in neurophysiology. The single neuron dynamics emerge from four voltage-controlled current sources and feature spiking and bursting output modes that can be controlled using tunable parameters. The bifurcation structures of the neuron, modeled as a 4D dynamical system, illustrate the roles of sources acting on different timescales in shaping neural dynamics. A comprehensive understanding of the system’s dynamic behavior is obtained by studying the state space variables and performing bifurcation analysis on the different parameters. The model is implemented to a 1mm x 2mm prototype chip utilizing the 180nm CMOS process. Each neural network consists of 1 isolated test neuron and 5 fully connected neurons using 20 synapses. By carefully selecting bias voltages according to the I-V characterization curves, the neurons are shown to exhibit spike, burst, and burst excitable behavior. Multiple small-scale neural networks with inhibitory or excitatory synapses were verified to achieve coupled rhythms with neuron bursts in-phase or out-of-phase. To demonstrate an application, the generated burst waveforms from the 4-neuron network were used to form a Central Pattern Generator (CPG) for locomotion control of the four legs of the Petoi, a quadruped robot, enabling the bot to jump successfully.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134982249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-02DOI: 10.1109/JETCAS.2023.3330069
Swagat Bhattacharyya;Praveen Raj Ayyappan;Jennifer O. Hasler
The study of biorealistic neuron circuits has been limited by the efficiency of digital implementations. Efficient digital approaches generally use I&F variants, losing important neural properties for network computation. In contrast, accurate neuron ODEs tend to utilize computationally intensive operations, causing the overhead to become prohibitive for large spiking neural network applications. This effort presents efficient digital approximations for coupled HH neurons derived from transistor-channel neural modeling. Neuron models are implemented in C using floating-point and 32-bit fixed-point arithmetic, and small networks are simulated using a fixed-step ODE solver. Our approach enables large network simulation of HH-like neurons, facilitating scalable digital modeling while also providing a direct path towards a framework for analog computation.
{"title":"Towards Scalable Digital Modeling of Networks of Biorealistic Silicon Neurons","authors":"Swagat Bhattacharyya;Praveen Raj Ayyappan;Jennifer O. Hasler","doi":"10.1109/JETCAS.2023.3330069","DOIUrl":"10.1109/JETCAS.2023.3330069","url":null,"abstract":"The study of biorealistic neuron circuits has been limited by the efficiency of digital implementations. Efficient digital approaches generally use I&F variants, losing important neural properties for network computation. In contrast, accurate neuron ODEs tend to utilize computationally intensive operations, causing the overhead to become prohibitive for large spiking neural network applications. This effort presents efficient digital approximations for coupled HH neurons derived from transistor-channel neural modeling. Neuron models are implemented in C using floating-point and 32-bit fixed-point arithmetic, and small networks are simulated using a fixed-step ODE solver. Our approach enables large network simulation of HH-like neurons, facilitating scalable digital modeling while also providing a direct path towards a framework for analog computation.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134890832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-01DOI: 10.1109/JETCAS.2023.3329430
Wei-Cheng Chen;Hong-Yeh Chang
A low-phase-noise local oscillator (LO) is a crucial component in communication systems. However, the design challenge of the LO significantly increases as the operating frequency rises. This paper focuses on the design and analysis of a $V$ -band CMOS sextuple sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with a frequency-tracking loop (FTL). To further enhance the locking range and efficiently generate high-order harmonic components, a cascade-series coupling injector is proposed for employment in the SILVCO. The design methodology of the proposed circuit is thoroughly presented, accompanied by analysis and calculated results. The SILVCO with FTL is implemented using a 90-nm CMOS process. With a sub-harmonic number of 6 and a dc power consumption of 23 mW, the measured output frequency ranges from 50.8 to 53.4 GHz, achieving a differential output power close to 0 dBm. The measured phase noise at a 1 MHz offset and the rms jitter integrated from 1 kHz to 10 MHz are both lower than −109.4 dBc/Hz and 43 fs, respectively.
{"title":"Design and Analysis of a V-Band CMOS Sextuple SILVCO Using Transformer and Cascade-Series Coupling With a Frequency-Tracking Loop","authors":"Wei-Cheng Chen;Hong-Yeh Chang","doi":"10.1109/JETCAS.2023.3329430","DOIUrl":"10.1109/JETCAS.2023.3329430","url":null,"abstract":"A low-phase-noise local oscillator (LO) is a crucial component in communication systems. However, the design challenge of the LO significantly increases as the operating frequency rises. This paper focuses on the design and analysis of a \u0000<inline-formula> <tex-math>$V$ </tex-math></inline-formula>\u0000-band CMOS sextuple sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with a frequency-tracking loop (FTL). To further enhance the locking range and efficiently generate high-order harmonic components, a cascade-series coupling injector is proposed for employment in the SILVCO. The design methodology of the proposed circuit is thoroughly presented, accompanied by analysis and calculated results. The SILVCO with FTL is implemented using a 90-nm CMOS process. With a sub-harmonic number of 6 and a dc power consumption of 23 mW, the measured output frequency ranges from 50.8 to 53.4 GHz, achieving a differential output power close to 0 dBm. The measured phase noise at a 1 MHz offset and the rms jitter integrated from 1 kHz to 10 MHz are both lower than −109.4 dBc/Hz and 43 fs, respectively.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135361182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-01DOI: 10.1109/JETCAS.2023.3329449
Julian Büchel;Athanasios Vasilopoulos;Benedikt Kersting;Corey Lammie;Kevin Brew;Timothy Philip;Nicole Saulnier;Vijay Narayanan;Manuel Le Gallo;Abu Sebastian
Accurate programming of non-volatile memory (NVM) devices in analog in-memory computing (AIMC) cores is critical to achieve high matrix-vector multiplication (MVM) accuracy during deep learning inference workloads. In this paper, we propose a novel programming approach that directly minimizes the MVM error by performing stochastic gradient descent optimization with synthetic random input data. The MVM error is significantly reduced compared to the conventional unit-cell by unit-cell iterative programming. We demonstrate that the optimal hyperparameters in our method are agnostic to the weights being programmed, enabling large-scale deployment across multiple AIMC cores without further fine tuning. It also eliminates the need for high-resolution analog to digital converters (ADCs) to decipher the small unit-cell conductance during programming. We experimentally validate this approach by demonstrating an inference accuracy increase of 1.26% on ResNet-9. The experiments were performed using phase change memory (PCM)-based AIMC cores fabricated in 14nm CMOS technology.
{"title":"Programming Weights to Analog In-Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication Error","authors":"Julian Büchel;Athanasios Vasilopoulos;Benedikt Kersting;Corey Lammie;Kevin Brew;Timothy Philip;Nicole Saulnier;Vijay Narayanan;Manuel Le Gallo;Abu Sebastian","doi":"10.1109/JETCAS.2023.3329449","DOIUrl":"10.1109/JETCAS.2023.3329449","url":null,"abstract":"Accurate programming of non-volatile memory (NVM) devices in analog in-memory computing (AIMC) cores is critical to achieve high matrix-vector multiplication (MVM) accuracy during deep learning inference workloads. In this paper, we propose a novel programming approach that directly minimizes the MVM error by performing stochastic gradient descent optimization with synthetic random input data. The MVM error is significantly reduced compared to the conventional unit-cell by unit-cell iterative programming. We demonstrate that the optimal hyperparameters in our method are agnostic to the weights being programmed, enabling large-scale deployment across multiple AIMC cores without further fine tuning. It also eliminates the need for high-resolution analog to digital converters (ADCs) to decipher the small unit-cell conductance during programming. We experimentally validate this approach by demonstrating an inference accuracy increase of 1.26% on ResNet-9. The experiments were performed using phase change memory (PCM)-based AIMC cores fabricated in 14nm CMOS technology.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":null,"pages":null},"PeriodicalIF":4.6,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135362614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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