Pub Date : 2025-09-18DOI: 10.1109/JETCAS.2025.3611595
Mohammad Amin Mahdian;Ebadollah Taheri;Mahdi Nikdast
Silicon photonic (SiPh) interposers offer a promising solution to overcome the bandwidth, latency, and energy limitations of electrical interconnects in chiplet-based systems. By enabling dense Wavelength Division Multiplexing (WDM) and high-speed optical signaling, they support scalable and efficient inter-chiplet communication. However, conventional SiPh interposer architectures face critical challenges, including fabrication-induced yield loss due to active photonic integration, and performance degradation from vertical link misalignments during packaging. This paper introduces MARVEL, a scalable and resilient SiPh interposer network that addresses these challenges through architectural and algorithmic innovations. MARVEL employs a passive interposer design, avoiding yield-limiting active components, and proposes to use optical vertical links (OVLs) to provide direct optical connections between chiplets and a centralized optical circuit switch (OCS). To mitigate the effects of packaging-induced misalignment, MARVEL incorporates redundancy-aware OVL selection using lightweight, reconfigurable on-chip switches. A dynamic in situ characterization protocol ranks available OVLs by loss, enabling the system to route traffic through the best performing links. This mechanism ensures 100% system reachability under modeled manufacturing variations. Additionally, MARVEL introduces a loss-aware recursive backtracking routing algorithm with precomputed lookup tables (LUTs) to optimize switch configurations for reduced insertion loss and tuning power. Comprehensive evaluations—including analytical modeling, Monte Carlo-based variability analysis, and discrete-event network simulation—show that MARVEL achieves up to 82% latency reduction over bus-based architectures and up to 86% improvement compared to prior work under synthetic traffic. On PARSEC benchmark workloads, MARVEL reduces latency by up to 75% while delivering approximately 10% total power savings. These results demonstrate MARVEL’s potential as a robust, energy-efficient, and scalable interposer architecture for next-generation heterogeneous computing platforms, including AI accelerators, high-performance computing (HPC), and data center systems.
{"title":"MARVEL: A Reconfigurable Chiplet-Integrated Photonic Interposer With Optical Vertical Links and Robust Misalignment Tolerance","authors":"Mohammad Amin Mahdian;Ebadollah Taheri;Mahdi Nikdast","doi":"10.1109/JETCAS.2025.3611595","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3611595","url":null,"abstract":"Silicon photonic (SiPh) interposers offer a promising solution to overcome the bandwidth, latency, and energy limitations of electrical interconnects in chiplet-based systems. By enabling dense Wavelength Division Multiplexing (WDM) and high-speed optical signaling, they support scalable and efficient inter-chiplet communication. However, conventional SiPh interposer architectures face critical challenges, including fabrication-induced yield loss due to active photonic integration, and performance degradation from vertical link misalignments during packaging. This paper introduces MARVEL, a scalable and resilient SiPh interposer network that addresses these challenges through architectural and algorithmic innovations. MARVEL employs a passive interposer design, avoiding yield-limiting active components, and proposes to use optical vertical links (OVLs) to provide direct optical connections between chiplets and a centralized optical circuit switch (OCS). To mitigate the effects of packaging-induced misalignment, MARVEL incorporates redundancy-aware OVL selection using lightweight, reconfigurable on-chip switches. A dynamic in situ characterization protocol ranks available OVLs by loss, enabling the system to route traffic through the best performing links. This mechanism ensures 100% system reachability under modeled manufacturing variations. Additionally, MARVEL introduces a loss-aware recursive backtracking routing algorithm with precomputed lookup tables (LUTs) to optimize switch configurations for reduced insertion loss and tuning power. Comprehensive evaluations—including analytical modeling, Monte Carlo-based variability analysis, and discrete-event network simulation—show that MARVEL achieves up to 82% latency reduction over bus-based architectures and up to 86% improvement compared to prior work under synthetic traffic. On PARSEC benchmark workloads, MARVEL reduces latency by up to 75% while delivering approximately 10% total power savings. These results demonstrate MARVEL’s potential as a robust, energy-efficient, and scalable interposer architecture for next-generation heterogeneous computing platforms, including AI accelerators, high-performance computing (HPC), and data center systems.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"619-633"},"PeriodicalIF":3.8,"publicationDate":"2025-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-16DOI: 10.1109/JETCAS.2025.3600772
Qinfen Hao;Kuan-Neng Chen;Sandeep Kumar Goel;Hai Li;Erik Jan Marinissen
{"title":"Guest Editorial 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test—Part I","authors":"Qinfen Hao;Kuan-Neng Chen;Sandeep Kumar Goel;Hai Li;Erik Jan Marinissen","doi":"10.1109/JETCAS.2025.3600772","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3600772","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"362-367"},"PeriodicalIF":3.8,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165062","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145073178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15DOI: 10.1109/JETCAS.2025.3603800
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems Information for Authors","authors":"","doi":"10.1109/JETCAS.2025.3603800","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3603800","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"506-506"},"PeriodicalIF":3.8,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11164806","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15DOI: 10.1109/JETCAS.2025.3603804
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","authors":"","doi":"10.1109/JETCAS.2025.3603804","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3603804","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"C3-C3"},"PeriodicalIF":3.8,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11165123","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-15DOI: 10.1109/JETCAS.2025.3603802
{"title":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems Publication Information","authors":"","doi":"10.1109/JETCAS.2025.3603802","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3603802","url":null,"abstract":"","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"C2-C2"},"PeriodicalIF":3.8,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11164995","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-11DOI: 10.1109/JETCAS.2025.3608825
Tao Zhang;Dehui Kong;Xinwei Fu;Yilin Zhong;Zhaosheng Liu;Renlin Dai;He Shi;Junhui Song
Passive Optical Networks (PON) have advantages such as stable performance, convenient installation, high bandwidth, and resource saving, making them a mainstream network access technology with broad application prospects. The development of such as 8K video, digital twins, VR and other technologies causes explosive growth of network traffic and drives the next generation of PON to evolve towards higher rates, which results in the use of forward error correction (FEC) coding with higher coding gain to improve the power budget of PON. Quasi-cyclic low density parity check (QC-LDPC) codes are widely utilized in PON systems due to high coding gain and parallel encoding and decoding capabilities. However, the application of turbo-decode message passing (TDMP) decoding method is inevitably equated with high hardware complexity of the decoder caused by storing and processing massive information, which is one of the obstacles to PON evolution. Reducing the quantization word length is effective to reduce hardware complexity, but it also leads to saturation of decoding information, causing errors and affecting decoding performance. This work proposes an nonlinear mapping method which utilizes adaptive compression of decoding information through node saturation state monitoring during the decoding process, in order to ensure that the probability density of node information has a reasonable distribution. The simulation results indicate that the method can effectively mitigate the decline in decoding performance under low-word-length conditions.
{"title":"Research on QC-LDPC Decoding Method With Low Quantization Word Length Based on Adaptive Information Mapping in Passive Optical Network","authors":"Tao Zhang;Dehui Kong;Xinwei Fu;Yilin Zhong;Zhaosheng Liu;Renlin Dai;He Shi;Junhui Song","doi":"10.1109/JETCAS.2025.3608825","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3608825","url":null,"abstract":"Passive Optical Networks (PON) have advantages such as stable performance, convenient installation, high bandwidth, and resource saving, making them a mainstream network access technology with broad application prospects. The development of such as 8K video, digital twins, VR and other technologies causes explosive growth of network traffic and drives the next generation of PON to evolve towards higher rates, which results in the use of forward error correction (FEC) coding with higher coding gain to improve the power budget of PON. Quasi-cyclic low density parity check (QC-LDPC) codes are widely utilized in PON systems due to high coding gain and parallel encoding and decoding capabilities. However, the application of turbo-decode message passing (TDMP) decoding method is inevitably equated with high hardware complexity of the decoder caused by storing and processing massive information, which is one of the obstacles to PON evolution. Reducing the quantization word length is effective to reduce hardware complexity, but it also leads to saturation of decoding information, causing errors and affecting decoding performance. This work proposes an nonlinear mapping method which utilizes adaptive compression of decoding information through node saturation state monitoring during the decoding process, in order to ensure that the probability density of node information has a reasonable distribution. The simulation results indicate that the method can effectively mitigate the decline in decoding performance under low-word-length conditions.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"16 1","pages":"5-14"},"PeriodicalIF":3.8,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147429278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-07DOI: 10.1109/JETCAS.2025.3596593
Janak Sharda;Shimeng Yu
Recent progress in large language models (LLMs) suggests the feasibility of their deployment on personal devices with model size reduction to a few to dozens of GB. Still, intermediate data’s computing needs are intensive, requiring frequent data reloading from the high-bandwidth memory (HBM). Today’s HBM bandwidth is limited by the number of channels embedded in a 2.5D integrated system. Advanced packaging techniques such as through silicon vias (TSV) and Cu-Cu hybrid bonding (HB) could potentially provide higher bandwidth interconnects between memory and logic dies in a 3D integrated system, where the vertical interconnect can reduce the distance between memory and logic, reducing the total energy consumption. However, this creates a large design exploration space for mixing and matching different packaging techniques and can result in complex thermal management issues due to the proximity of various components. In this work, we describe an evaluation methodology which is used to construct a framework capable of benchmarking system-level power, performance, and area (PPA) metrics for 2.5D/3D integrated systems for LLM accelerators. Additionally, we utilize the framework to conduct a detailed analysis to identify the bottlenecks for training and inference across various models and batch sizes. It is observed that the memory bandwidth and routing energy bottlenecks the inference performance, and the available compute bottlenecks the training performance. Finally, we perform thermal evaluations to observe the trade-off between peak operating temperature and the throughput across different packaging configurations.
{"title":"System-Technology Co-Optimization Methodology for LLM Accelerators With Advanced Packaging","authors":"Janak Sharda;Shimeng Yu","doi":"10.1109/JETCAS.2025.3596593","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3596593","url":null,"abstract":"Recent progress in large language models (LLMs) suggests the feasibility of their deployment on personal devices with model size reduction to a few to dozens of GB. Still, intermediate data’s computing needs are intensive, requiring frequent data reloading from the high-bandwidth memory (HBM). Today’s HBM bandwidth is limited by the number of channels embedded in a 2.5D integrated system. Advanced packaging techniques such as through silicon vias (TSV) and Cu-Cu hybrid bonding (HB) could potentially provide higher bandwidth interconnects between memory and logic dies in a 3D integrated system, where the vertical interconnect can reduce the distance between memory and logic, reducing the total energy consumption. However, this creates a large design exploration space for mixing and matching different packaging techniques and can result in complex thermal management issues due to the proximity of various components. In this work, we describe an evaluation methodology which is used to construct a framework capable of benchmarking system-level power, performance, and area (PPA) metrics for 2.5D/3D integrated systems for LLM accelerators. Additionally, we utilize the framework to conduct a detailed analysis to identify the bottlenecks for training and inference across various models and batch sizes. It is observed that the memory bandwidth and routing energy bottlenecks the inference performance, and the available compute bottlenecks the training performance. Finally, we perform thermal evaluations to observe the trade-off between peak operating temperature and the throughput across different packaging configurations.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 4","pages":"577-584"},"PeriodicalIF":3.8,"publicationDate":"2025-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145808550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-05DOI: 10.1109/JETCAS.2025.3595909
George Karfakis;Myriam Bouzidi;Yunhyeok Im;Alexander Graening;Suresh K. Sitaraman;Puneet Gupta
This paper investigates thermal management in tightly integrated heterogeneous chiplet systems, focusing on a novel approach using embedded thermal isolators. In many 2.5D systems, such as modern enterprise GPUs, thermally sensitive chiplets like High Bandwidth Memory (HBM) are thermally coupled to high-power compute chiplets, leading to performance degradation. We propose and evaluate the use of thermal isolators embedded within the heat spreader to effectively thermally decouple chiplets. Our thermal simulations of a water-cooled 2.5D integrated GPU system indicate that conventional approaches like thermally-aware floorplanning are less effective due to the dominant heat transfer through the heat spreader. In contrast, our proposed thermal isolators can significantly increase thermal isolation between chiplets (by up to 61%), or even reduce overall average peak chip temperature (by up to 22.5%). We develop a closed-loop workflow incorporating thermal results to quantify performance impacts of thermal-induced throttling, finding that in an example GPU+HBM system, the isolator approach can yield performance gains of up to 37% for memory-bound workloads. These findings open up new avenues for thermal management and thermal-system co-optimization in 2.5D heterogeneous integrated systems, potentially enabling more efficient and higher-performing chiplet-based architectures.
{"title":"Optimizing Thermal Performance in 2.5D Systems Using Embedded Isolators","authors":"George Karfakis;Myriam Bouzidi;Yunhyeok Im;Alexander Graening;Suresh K. Sitaraman;Puneet Gupta","doi":"10.1109/JETCAS.2025.3595909","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3595909","url":null,"abstract":"This paper investigates thermal management in tightly integrated heterogeneous chiplet systems, focusing on a novel approach using embedded thermal isolators. In many 2.5D systems, such as modern enterprise GPUs, thermally sensitive chiplets like High Bandwidth Memory (HBM) are thermally coupled to high-power compute chiplets, leading to performance degradation. We propose and evaluate the use of thermal isolators embedded within the heat spreader to effectively thermally decouple chiplets. Our thermal simulations of a water-cooled 2.5D integrated GPU system indicate that conventional approaches like thermally-aware floorplanning are less effective due to the dominant heat transfer through the heat spreader. In contrast, our proposed thermal isolators can significantly increase thermal isolation between chiplets (by up to 61%), or even reduce overall average peak chip temperature (by up to 22.5%). We develop a closed-loop workflow incorporating thermal results to quantify performance impacts of thermal-induced throttling, finding that in an example GPU+HBM system, the isolator approach can yield performance gains of up to 37% for memory-bound workloads. These findings open up new avenues for thermal management and thermal-system co-optimization in 2.5D heterogeneous integrated systems, potentially enabling more efficient and higher-performing chiplet-based architectures.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"458-468"},"PeriodicalIF":3.8,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-01DOI: 10.1109/JETCAS.2025.3594675
Galib Ibne Haidar;Jingbo Zhou;Md Sami Ul Islam Sami;Mark M. Tehranipoor;Farimah Farahmandi
System-in-Packages (SiPs) are gaining traction due to their enhanced performance, high yield rates, and accelerated time-to-market. However, integrating chiplets from untrusted sources introduces security risks during post-integration testing. Malicious chiplets within the SiP can intercept, modify, or block sensitive test data intended for specific chiplets. This article presents SAFET-HI, a framework designed to ensure a secure testing environment for SiPs. Within this framework, sensitive test data are accessible only to authenticated chiplets. To counter sniffing and spoofing attacks, SAFET-HI encrypts sensitive test patterns while maintaining minimal timing overhead. During post-integration testing, another major threat arises from outsourcing test patterns to untrusted testing facilities, increasing the risk of overproduction and counterfeiting. To address this, SAFET-HI incorporates a functional locking mechanism that prevents unauthorized production and distribution of defective SiPs. Additionally, scan encryption blocks are implemented to stop untrusted test facilities from generating a golden response database. To further enhance security, a watermark bitstream is embedded within the SiP to prevent remarking attacks by untrusted distributors. Simulation results show that SAFET-HI incurs area and timing overheads of only 1.42-4.27% and 13.7%, respectively, demonstrating its effectiveness in securing the SiP testing process.
{"title":"SAFET-HI: Secure Authentication-Based Framework for Encrypted Testing in Heterogeneous Integration","authors":"Galib Ibne Haidar;Jingbo Zhou;Md Sami Ul Islam Sami;Mark M. Tehranipoor;Farimah Farahmandi","doi":"10.1109/JETCAS.2025.3594675","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3594675","url":null,"abstract":"System-in-Packages (SiPs) are gaining traction due to their enhanced performance, high yield rates, and accelerated time-to-market. However, integrating chiplets from untrusted sources introduces security risks during post-integration testing. Malicious chiplets within the SiP can intercept, modify, or block sensitive test data intended for specific chiplets. This article presents SAFET-HI, a framework designed to ensure a secure testing environment for SiPs. Within this framework, sensitive test data are accessible only to authenticated chiplets. To counter sniffing and spoofing attacks, SAFET-HI encrypts sensitive test patterns while maintaining minimal timing overhead. During post-integration testing, another major threat arises from outsourcing test patterns to untrusted testing facilities, increasing the risk of overproduction and counterfeiting. To address this, SAFET-HI incorporates a functional locking mechanism that prevents unauthorized production and distribution of defective SiPs. Additionally, scan encryption blocks are implemented to stop untrusted test facilities from generating a golden response database. To further enhance security, a watermark bitstream is embedded within the SiP to prevent remarking attacks by untrusted distributors. Simulation results show that SAFET-HI incurs area and timing overheads of only 1.42-4.27% and 13.7%, respectively, demonstrating its effectiveness in securing the SiP testing process.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"478-492"},"PeriodicalIF":3.8,"publicationDate":"2025-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents the Embedded Multi-die Active Bridge (EMAB) chip, a programmable bridge for cost-effective 2.5D/3.5D packaging technologies. The EMAB chip features a reconfigurable switch array to establish flexible I/O links for connecting multiple chiplets, forming an EMAB chipset based on user needs. It integrates low-dropout regulators (LDOs) for in-package voltage regulation and supports various transmission interfaces, including checkerboard I/Os (50 Mbps–1 Gbps) and MUX I/Os (up to 8 Gbps). Moreover, multiple EMAB chips can be interconnected in a daisy-chain configuration, enabling easy expansion of the EMAB chipset. Additionally, the EMAB chip eliminates TSVs in silicon interposer-based 2.5D packaging technologies and reduces redistribution layer (RDL) complexity through flexible I/O links established within the EMAB chip. Furthermore, EMAB chip can be pre-manufactured as a precast supporting layer (known good die, KGD), which shortens the product development cycle and enhance integration yield. Overall, the EMAB chip offers a miniaturized, low-cost, fast time-to-market and scalable solution for advanced 2.5D/3.5D packaging.
本文介绍了嵌入式多模有源桥接（EMAB）芯片，这是一种可编程桥接，用于经济高效的2.5D/3.5D封装技术。EMAB芯片采用可重新配置的开关阵列，建立灵活的I/O链路，用于连接多个小芯片，根据用户需求组成EMAB芯片组。它集成了用于封装内电压调节的低差稳压器（ldo），并支持各种传输接口，包括棋盘I/ o （50 Mbps-1 Gbps）和MUX I/ o（高达8 Gbps）。此外，多个EMAB芯片可以在菊花链配置中互连，使EMAB芯片组易于扩展。此外，EMAB芯片消除了基于硅介层的2.5D封装技术中的tsv，并通过在EMAB芯片内建立灵活的I/O链路降低了再分配层（RDL）的复杂性。此外，EMAB芯片可以作为预制支撑层（称为good die， KGD）进行预制造，缩短了产品开发周期，提高了成品率。总体而言，EMAB芯片为先进的2.5D/3.5D封装提供了小型化、低成本、快速上市和可扩展的解决方案。
{"title":"Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset","authors":"Wei Lu;Jie Zhang;Yi-Hui Wei;Hsu-Ming Hsiao;Sih-Han Li;Chao-Kai Hsu;Chih-Cheng Hsiao;Feng-Hsiang Lo;Shyh-Shyuan Sheu;Chin-Hung Wang;Ching-Iang Li;Yung-Sheng Chang;Ming-Ji Dai;Wei-Chung Lo;Shih-Chieh Chang;Hung-Ming Chen;Kuan-Neng Chen;Po-Tsang Huang","doi":"10.1109/JETCAS.2025.3594169","DOIUrl":"https://doi.org/10.1109/JETCAS.2025.3594169","url":null,"abstract":"This paper presents the Embedded Multi-die Active Bridge (EMAB) chip, a programmable bridge for cost-effective 2.5D/3.5D packaging technologies. The EMAB chip features a reconfigurable switch array to establish flexible I/O links for connecting multiple chiplets, forming an EMAB chipset based on user needs. It integrates low-dropout regulators (LDOs) for in-package voltage regulation and supports various transmission interfaces, including checkerboard I/Os (50 Mbps–1 Gbps) and MUX I/Os (up to 8 Gbps). Moreover, multiple EMAB chips can be interconnected in a daisy-chain configuration, enabling easy expansion of the EMAB chipset. Additionally, the EMAB chip eliminates TSVs in silicon interposer-based 2.5D packaging technologies and reduces redistribution layer (RDL) complexity through flexible I/O links established within the EMAB chip. Furthermore, EMAB chip can be pre-manufactured as a precast supporting layer (known good die, KGD), which shortens the product development cycle and enhance integration yield. Overall, the EMAB chip offers a miniaturized, low-cost, fast time-to-market and scalable solution for advanced 2.5D/3.5D packaging.","PeriodicalId":48827,"journal":{"name":"IEEE Journal on Emerging and Selected Topics in Circuits and Systems","volume":"15 3","pages":"379-391"},"PeriodicalIF":3.8,"publicationDate":"2025-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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