Microprocessors and Microsystems最新文献

Nanotechnology has made the circuits more susceptible to errors. It takes a lot of space and power to make sequential reversible circuits testable using one of the conventional methods (such as cascading gates with the original circuit). I suggest a superior testing strategy for sequential circuits based on conservative logic. The primary goal of this effort is to create a testable sequential circuit that is compact in terms of circuit area and other cost parameters. My method does not require changing the original circuit. So, incorporating testable features using the proposed method does not affect the complexity of the overall circuit. In this work, stuck-at-fault modeling for external unwanted energy or internal cell defect in low-power molecular QCA is also derived. The reversible double-edge triggered (DET) flip-flop is tested using the suggested approach. The proposed methodology can still be applied to achieve 100% fault coverage for unidirectional stuck-at-fault in quantum cellular automata (QCA) designs. The design is assigned into practice using a layered technique since it is more reliable and economical.

Physical attacks are powerful threats that can cause changes in the execution behavior of a program. Control-Flow Integrity (CFI) is used to check the program’s flow execution, ensuring that it remains unaltered by these attacks. The RISC-V Trace Encoder (TE) provides valuable information about the user program’s execution path, and is used as part of a CFI solution. An enhanced version of the TE specifications permits detecting intricate fault models such as the corruption of any discontinuity instruction, using an additional Trace Verifier (TV) hardware module. In this paper, we present a buffer overflow software attack simulation and experimental ElectroMagnetic Fault Injection (EMFI) attacks conducted on an Field Programmable Gate Array (FPGA) board that implements a RISC-V core linked to the enhanced TE and TV modules. Unlike existing CFI solutions, our proposed approach does not require modifications to the RISC-V compiler, user application code or the RISC-V core. The average overhead of our solution in terms of hardware area, memory and power consumption are equal to 13.6%, 3.5% and 9% respectively.

The Electronic Healthcare (eHealth) systems are competent to ensure effective care engineering and intensified healthcare quality which are user-friendly cache and administration, in Electronic Health Records (EHRs). For secure EHRs of Mobile Cloud-based eHealth systems, ensuring high security and data privacy, Interplanetary File System in healthcare has traditionally been concentrated. However, there has been a recent push towards achieving high quality of e-health services because blockchain-based health care applications require QoS guarantees in terms of requirements such as network latency and end-to-end delay. In this work, an Extended Validation Certification-based Fischer Neural Network Optimization (EVC-FNNO) method for secured Mobile Cloud-based E-Health Systems is proposed. With the identity being the digital certificate, the EVC is provided with the identity to the mobile cloud user who will transact in the network. In this way, the mobile cloud user is being ensured to access the ledger for the transaction. Therefore, both data privacy and security is said to be provided. Next, with Fischer Neural Network Optimization (FNNO), every authenticated mobile cloud user via EVC then possess a copy of shared ledger, therefore resolving data acquisition in cloud server and hence solving network latency. The proposed method is verified by some demonstrative examples in addressing QoS. The empirical results show that the EVC-FNNO method provides an efficient solution by validating the mobile cloud user sensitive health information with digital certificate. Security analysis proves that the EVC-FNNO method is secure. We also conduct comprehensive performance evaluations that demonstrate the high efficiency of the EVC-FNNO method in terms of end-to-end delay, network latency and data privacy, compared to the existing data sharing methods.

Hardware Trojans that have the capability to change the computed functional output in intellectual property (IP) cores, integrated into computing systems can be a vital reliability concern in the context of correct system operation. Therefore, determining an optimal Trojan-resistant hardware design architecture that considers multi-objective orthogonal parameters such as area and delay is crucial. This paper presents a novel exploration of optimal hardware IP core design methodology with Trojan defense capability (i.e., detection and isolation) during high level synthesis (HLS) that provides isolation of functional Trojan in a system design to ensure reliable and correct functional behavior. The proposed methodology is robust and provides the capability to yield the correct output value using HLS-based triple modular redundancy (TMR) logic and a distinct multivendor allocation policy. Therefore, the proposed HLS methodology can generate an optimal hardware IP core/system-on-chip (SoC) design with functional Trojan defense capability. The paper presents an overall flow of the proposed methodology along with a demonstrative case study on designing optimal Trojan resistant finite impulse response filter (FIR) hardware SoC design. Results of the proposed approach are evaluated in terms of design cost, convergence time, security and optimality analysis, and comparison with prior works. The proposed approach is able to generate fully functional Trojan-resistant optimal SoC designs with minimum overhead, as evident from optimality analysis and design cost.

Robotics increasingly provides practical applications for society, such as manufacturing, autonomous driving, robot vacuum cleaners, robots in logistics, drones for inspection, etc. Typical requirements in this field are fast response time, low power consumption, parallelism, and flexibility. According to these features, FPGAs are a suitable computing substrate for robots. A few vendors have dominated the FPGA market with their proprietary tools and hardware devices, resulting in fragmented ecosystems with few standards and little interoperation. New and complete open toolchains for FPGAs are emerging from the open-source community. This article presents an open-source library of Verilog modules useful for vision-based robots, including reusable image processing blocks for perception and reactive control blocks. This library has been developed using open tools, but its Verilog modules are fully compatible with any proprietary toolchain. In addition, three applications with a real robot and open FPGAs have been developed for experimental validation using this library. In the last application, the mobile robot successfully follows a colored object using two low-cost cameras (to increase the robot’s field of view) and includes a third camera on top of a servo-driven turret for tracking a second independent object while following the first one in parallel. Resource consumption of all applications has been measured and compared with state-of-the-art proprietary toolchains, revealing that reconfigurable computing with open FPGAs using open tools is now an attractive alternative to designing and creating intelligent vision-based robotic applications using vendor-dependent proprietary tools and FPGAs.

Network on Chip (NoC) is an interesting technology that benefits from several processing elements and the necessary communication facilities, to provide an answer to the ever-growing need for more processing power. Metaheuristic algorithms are important tools that have been used for dealing with various NP-hard problems in different domains. Such algorithms are also widely used in the NoC context by many frameworks for optimizing various characteristics of the NoC environments. Nonetheless, there is a lack of a comprehensive survey to put forward a thorough study of such schemes. To fill this gap, this article presents a comprehensive survey and classification of the metaheuristic-based schemes designed for various NoC topologies. For this purpose, first, some background knowledge is provided which helps to understand the studied schemes. Then, a taxonomy of the investigated approaches based on their applied metaheuristic algorithms is presented and in each category, schemes are studied and their main contributions and properties as well as their limitations are discussed. At last, a comparison of the techniques, tools, and methods that have been used in the studied schemes are provided along with the concluding remarks and future research directions.

Software systems are often built in increments with additional features or enhancements on top of existing products. This incremental development may result in the deterioration of certain quality aspects. In other words, the software can be considered an evolving entity emanating different quality characteristics as it gets updated over time with new features or deployed in different operational environments. Approaching software development with this mindset and awareness regarding quality evolution over time can be a key factor for the long-term success of a company in today’s highly competitive market of industrial software-intensive products. Therefore, it is important to be able to accurately analyze and determine the quality implications of each change and increment to a software system. To address this challenge, the multinational SmartDelta project develops automated solutions for the quality assessment of product deltas in a continuous engineering environment. The project provides smart analytics from development artifacts and system executions, offering insights into quality degradation or improvements across different product versions, and providing recommendations for the next builds. This paper presents the challenges in incremental software development tackled in the scope of the SmartDelta project, and the solutions that are produced and planned in the project, along with the industrial impact of the project for software-intensive industrial systems.