Microprocessors and Microsystems最新文献

With the development of automobile industry technology, vehicles have greatly affected everyday life, work and other aspects. With the continuous innovation of sensor technology, computer technology, wireless communication technology, and GPS technology, the concept of Inter of Vehicles (IoV) has been widely regarded as the core technology to solve a series of problems. However, as a complexity network with multiple elements including people, vehicle, base-station and so on, IoV is confronted with security threatened. In this paper, secure data exchange has been considered for two authenticated On Board Units (OBUs) with help of Road Side Unit (RSU). Blockchain based authentication and physical layer security have been applied into IoV for wiretap resisting and privacy preserving data exchange. For wiretap resisting, two synchronized transmitted signals from OBUs act as artificial noise at eavesdropper. In addition, for privacy preserving, summed codeword is formed at RSU which cannot be recovered individually. Finally, simulation results have been conducted to demonstrate that the proposed protocol can achieve transmission efficiency as well as informatics security.

Hardware implementations of Transactional Memory (HTM) are designed to facilitate efficient thread synchronization in parallel programs, encouraging the use of larger critical sections. By employing optimistic concurrency control to execute transactions speculatively, HTM systems promise to deliver the performance benefits typically associated with fine-grained locks. In doing so, HTM systems must deal with transaction aborts. While under certain conditions aborts may be caused by the inherent limitations of hardware structures employed to implement TM (e.g., caches), conflicting concurrent accesses to shared memory locations are generally the prevailing cause for squashing the work done by a transaction

In this study, we present what we believe to be, to the best of our knowledge, the first characterization of how the aggressiveness of processor cores, particularly their ability to exploit instruction-level parallelism (ILP), interacts with the support for optimistic thread-level speculation offered by HTM systems. We have observed that by adjusting the size of structures that facilitate out-of-order and speculative execution, the number of aborts in the execution of transactional workloads can be altered in best-effort HTM implementations. Our findings indicate that in scenarios with high contention, a smaller number of powerful cores is more suitable, whereas in low contention scenarios, using a larger number of less aggressive cores is preferable. In addition, HTM systems that employ lazy detection and those employing eager detection with requester-stalls resolution, benefit from using simpler cores. In conclusion, abort ratios can be reduced with a careful choice of both processor aggressiveness and design aspects for each application depending on its contention.

Nanotechnology has made the circuits more susceptible to errors. It takes a lot of space and power to make sequential reversible circuits testable using one of the conventional methods (such as cascading gates with the original circuit). I suggest a superior testing strategy for sequential circuits based on conservative logic. The primary goal of this effort is to create a testable sequential circuit that is compact in terms of circuit area and other cost parameters. My method does not require changing the original circuit. So, incorporating testable features using the proposed method does not affect the complexity of the overall circuit. In this work, stuck-at-fault modeling for external unwanted energy or internal cell defect in low-power molecular QCA is also derived. The reversible double-edge triggered (DET) flip-flop is tested using the suggested approach. The proposed methodology can still be applied to achieve 100% fault coverage for unidirectional stuck-at-fault in quantum cellular automata (QCA) designs. The design is assigned into practice using a layered technique since it is more reliable and economical.

Hardware Trojans that have the capability to change the computed functional output in intellectual property (IP) cores, integrated into computing systems can be a vital reliability concern in the context of correct system operation. Therefore, determining an optimal Trojan-resistant hardware design architecture that considers multi-objective orthogonal parameters such as area and delay is crucial. This paper presents a novel exploration of optimal hardware IP core design methodology with Trojan defense capability (i.e., detection and isolation) during high level synthesis (HLS) that provides isolation of functional Trojan in a system design to ensure reliable and correct functional behavior. The proposed methodology is robust and provides the capability to yield the correct output value using HLS-based triple modular redundancy (TMR) logic and a distinct multivendor allocation policy. Therefore, the proposed HLS methodology can generate an optimal hardware IP core/system-on-chip (SoC) design with functional Trojan defense capability. The paper presents an overall flow of the proposed methodology along with a demonstrative case study on designing optimal Trojan resistant finite impulse response filter (FIR) hardware SoC design. Results of the proposed approach are evaluated in terms of design cost, convergence time, security and optimality analysis, and comparison with prior works. The proposed approach is able to generate fully functional Trojan-resistant optimal SoC designs with minimum overhead, as evident from optimality analysis and design cost.

Physical attacks are powerful threats that can cause changes in the execution behavior of a program. Control-Flow Integrity (CFI) is used to check the program’s flow execution, ensuring that it remains unaltered by these attacks. The RISC-V Trace Encoder (TE) provides valuable information about the user program’s execution path, and is used as part of a CFI solution. An enhanced version of the TE specifications permits detecting intricate fault models such as the corruption of any discontinuity instruction, using an additional Trace Verifier (TV) hardware module. In this paper, we present a buffer overflow software attack simulation and experimental ElectroMagnetic Fault Injection (EMFI) attacks conducted on an Field Programmable Gate Array (FPGA) board that implements a RISC-V core linked to the enhanced TE and TV modules. Unlike existing CFI solutions, our proposed approach does not require modifications to the RISC-V compiler, user application code or the RISC-V core. The average overhead of our solution in terms of hardware area, memory and power consumption are equal to 13.6%, 3.5% and 9% respectively.

The Electronic Healthcare (eHealth) systems are competent to ensure effective care engineering and intensified healthcare quality which are user-friendly cache and administration, in Electronic Health Records (EHRs). For secure EHRs of Mobile Cloud-based eHealth systems, ensuring high security and data privacy, Interplanetary File System in healthcare has traditionally been concentrated. However, there has been a recent push towards achieving high quality of e-health services because blockchain-based health care applications require QoS guarantees in terms of requirements such as network latency and end-to-end delay. In this work, an Extended Validation Certification-based Fischer Neural Network Optimization (EVC-FNNO) method for secured Mobile Cloud-based E-Health Systems is proposed. With the identity being the digital certificate, the EVC is provided with the identity to the mobile cloud user who will transact in the network. In this way, the mobile cloud user is being ensured to access the ledger for the transaction. Therefore, both data privacy and security is said to be provided. Next, with Fischer Neural Network Optimization (FNNO), every authenticated mobile cloud user via EVC then possess a copy of shared ledger, therefore resolving data acquisition in cloud server and hence solving network latency. The proposed method is verified by some demonstrative examples in addressing QoS. The empirical results show that the EVC-FNNO method provides an efficient solution by validating the mobile cloud user sensitive health information with digital certificate. Security analysis proves that the EVC-FNNO method is secure. We also conduct comprehensive performance evaluations that demonstrate the high efficiency of the EVC-FNNO method in terms of end-to-end delay, network latency and data privacy, compared to the existing data sharing methods.

Robotics increasingly provides practical applications for society, such as manufacturing, autonomous driving, robot vacuum cleaners, robots in logistics, drones for inspection, etc. Typical requirements in this field are fast response time, low power consumption, parallelism, and flexibility. According to these features, FPGAs are a suitable computing substrate for robots. A few vendors have dominated the FPGA market with their proprietary tools and hardware devices, resulting in fragmented ecosystems with few standards and little interoperation. New and complete open toolchains for FPGAs are emerging from the open-source community. This article presents an open-source library of Verilog modules useful for vision-based robots, including reusable image processing blocks for perception and reactive control blocks. This library has been developed using open tools, but its Verilog modules are fully compatible with any proprietary toolchain. In addition, three applications with a real robot and open FPGAs have been developed for experimental validation using this library. In the last application, the mobile robot successfully follows a colored object using two low-cost cameras (to increase the robot’s field of view) and includes a third camera on top of a servo-driven turret for tracking a second independent object while following the first one in parallel. Resource consumption of all applications has been measured and compared with state-of-the-art proprietary toolchains, revealing that reconfigurable computing with open FPGAs using open tools is now an attractive alternative to designing and creating intelligent vision-based robotic applications using vendor-dependent proprietary tools and FPGAs.