Purpose Internet of things (IoT) is essential in technical, social and economic domains, but there are many challenges that researchers are continuously trying to solve. Traditional resource allocation methods in IoT focused on the optimal resource selection process, but the energy consumption for allocating resources is not considered sufficiently. This paper aims to propose a resource allocation technique aiming at energy and delay reduction in resource allocation. Because of the non-deterministic polynomial-time hard nature of the resource allocation issue and the forest optimization algorithm’s success in complex problems, the authors used this algorithm to allocate resources in IoT. Design/methodology/approach For the vast majority of IoT applications, energy-efficient communications, sustainable energy supply and reduction of latency have been major goals in resource allocation, making operating systems and applications more efficient. One of the most critical challenges in this field is efficient resource allocation. This paper has provided a new technique to solve the mentioned problem using the forest optimization algorithm. To simulate and analyze the proposed technique, the MATLAB software environment has been used. The results obtained from implementing the proposed method have been compared to the particle swarm optimization (PSO), genetic algorithm (GA) and distance-based algorithm. Findings Simulation results show that the proper performance of the proposed technique. The proposed method, in terms of “energy” and “delay,” is better than other ones (GA, PSO and distance-based algorithm). Practical implications The paper presents a useful method for improving resource allocation methods. The proposed method has higher efficiency compared to the previous methods. The MATLAB-based simulation results have indicated that energy consumption and delay have been improved compared to other algorithms, which causes the high application of this method in practical projects. In the future, the focus will be on resource failure and reducing the service level agreement violation rate concerning the number of resources. Originality/value The proposed technique can solve the mentioned problem in the IoT with the best resource utilization, low delay and reduced energy consumption. The proposed forest optimization-based algorithm is a promising technique to help enterprises participate in IoT initiatives and develop their business.
{"title":"An energy-aware approach for resources allocating in the internet of things using a forest optimization algorithm","authors":"Min-Ning Wu, Feng Zhang, X. Rui","doi":"10.1108/cw-02-2020-0017","DOIUrl":"https://doi.org/10.1108/cw-02-2020-0017","url":null,"abstract":"\u0000Purpose\u0000Internet of things (IoT) is essential in technical, social and economic domains, but there are many challenges that researchers are continuously trying to solve. Traditional resource allocation methods in IoT focused on the optimal resource selection process, but the energy consumption for allocating resources is not considered sufficiently. This paper aims to propose a resource allocation technique aiming at energy and delay reduction in resource allocation. Because of the non-deterministic polynomial-time hard nature of the resource allocation issue and the forest optimization algorithm’s success in complex problems, the authors used this algorithm to allocate resources in IoT.\u0000\u0000\u0000Design/methodology/approach\u0000For the vast majority of IoT applications, energy-efficient communications, sustainable energy supply and reduction of latency have been major goals in resource allocation, making operating systems and applications more efficient. One of the most critical challenges in this field is efficient resource allocation. This paper has provided a new technique to solve the mentioned problem using the forest optimization algorithm. To simulate and analyze the proposed technique, the MATLAB software environment has been used. The results obtained from implementing the proposed method have been compared to the particle swarm optimization (PSO), genetic algorithm (GA) and distance-based algorithm.\u0000\u0000\u0000Findings\u0000Simulation results show that the proper performance of the proposed technique. The proposed method, in terms of “energy” and “delay,” is better than other ones (GA, PSO and distance-based algorithm).\u0000\u0000\u0000Practical implications\u0000The paper presents a useful method for improving resource allocation methods. The proposed method has higher efficiency compared to the previous methods. The MATLAB-based simulation results have indicated that energy consumption and delay have been improved compared to other algorithms, which causes the high application of this method in practical projects. In the future, the focus will be on resource failure and reducing the service level agreement violation rate concerning the number of resources.\u0000\u0000\u0000Originality/value\u0000The proposed technique can solve the mentioned problem in the IoT with the best resource utilization, low delay and reduced energy consumption. The proposed forest optimization-based algorithm is a promising technique to help enterprises participate in IoT initiatives and develop their business.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42438678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper aims to obtain a symmetrical step-down topology with lower equivalent capacity and wider step-down range under the condition of the same output. Two new symmetrical step-down topologies of star-connected autotransformers are proposed in this paper. Taking the equivalent capacity as the main parameter, the obtained topologies are modeled and analyzed in detail. Design/methodology/approach This paper adopts the research methods of design, modeling, analysis and simulation verification. First, the star-connected autotransformer is redesigned according to the design objective of symmetrical step-down topology. In addition, the mathematical model of two topologies is established and a detailed theoretical analysis is carried out. Finally, the theoretical results are verified by simulation. Findings Two symmetrical star-connected autotransformer step-down topologies are designed, the winding configurations of the corresponding topology are presented, the step-down ranges of these three topologies are calculated and the influence of step-down ratio on the equivalent capacity of autotransformer are analyzed. Through analysis, the target step-down topologies are obtained when the step-down ratio is [1.1, 5.4] and [1.1, 1.9] respectively. Research limitations/implications Because the selected research object is only a star-connected autotransformer, the research results may lack generality. Therefore, researchers are encouraged to further study the topologies of other autotransformers. Practical implications This paper includes the implications of the step-down ratio on the equivalent capacity of autotransformers and the configuration of transformer windings. Originality/value The topologies designed in this paper enable star-connected autotransformer in the 12-pulse rectifier to be applied in step-down circumstances rather than situations of harmonic reduction only. At the same time, this paper provides a way that can be used to redesign the autotransformer in other multi-pulse rectifier systems, so that those transformers can be used in voltage regulation.
{"title":"Novel step-down topologies of star-connected autotransformer","authors":"Jiarong Wang, Bo He, Xiaoqiang Chen","doi":"10.1108/cw-11-2019-0159","DOIUrl":"https://doi.org/10.1108/cw-11-2019-0159","url":null,"abstract":"\u0000Purpose\u0000This paper aims to obtain a symmetrical step-down topology with lower equivalent capacity and wider step-down range under the condition of the same output. Two new symmetrical step-down topologies of star-connected autotransformers are proposed in this paper. Taking the equivalent capacity as the main parameter, the obtained topologies are modeled and analyzed in detail.\u0000\u0000\u0000Design/methodology/approach\u0000This paper adopts the research methods of design, modeling, analysis and simulation verification. First, the star-connected autotransformer is redesigned according to the design objective of symmetrical step-down topology. In addition, the mathematical model of two topologies is established and a detailed theoretical analysis is carried out. Finally, the theoretical results are verified by simulation.\u0000\u0000\u0000Findings\u0000Two symmetrical star-connected autotransformer step-down topologies are designed, the winding configurations of the corresponding topology are presented, the step-down ranges of these three topologies are calculated and the influence of step-down ratio on the equivalent capacity of autotransformer are analyzed. Through analysis, the target step-down topologies are obtained when the step-down ratio is [1.1, 5.4] and [1.1, 1.9] respectively.\u0000\u0000\u0000Research limitations/implications\u0000Because the selected research object is only a star-connected autotransformer, the research results may lack generality. Therefore, researchers are encouraged to further study the topologies of other autotransformers.\u0000\u0000\u0000Practical implications\u0000This paper includes the implications of the step-down ratio on the equivalent capacity of autotransformers and the configuration of transformer windings.\u0000\u0000\u0000Originality/value\u0000The topologies designed in this paper enable star-connected autotransformer in the 12-pulse rectifier to be applied in step-down circumstances rather than situations of harmonic reduction only. At the same time, this paper provides a way that can be used to redesign the autotransformer in other multi-pulse rectifier systems, so that those transformers can be used in voltage regulation.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43267613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jitendra B. Zalke, Sandeepkumar R. Pandey, Ruchir V. Nandanwar, Atharva Sandeep Pande, Pravin Balu Nikam
Purpose The purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed gyrator-induced voltage flip technique (GIVFT) does not require bulky components such as physical inductors, it is easily realizable in small integrated circuits (IC) package thereby offering performance benefits, reducing area overhead and providing cost benefits for constrained self-powered autonomous Internet-of-Things (IoT) applications. Design/methodology/approach This paper presents an inductorless interface circuit for PEH. The proposed technique is called GIVFT and is demonstrated using active elements. The authors use gyrator to induce voltage flip at the output side of PEH to enhance the charge extraction from PEH. The proposed technique uses the current-voltage (I-V) relationship of gyrator to get appropriate phasor response necessary to induce the voltage flip at the output of PEH to gain power transfer enhancement at the load. Findings The experimental results show the efficacy of the GIVFT realization for enhanced power extraction. The authors have compared their proposed design with popular earlier reported interface circuits. Experimentally measured performance improvement is 1.86×higher than the baseline comparison of full-wave bridge rectifier circuit. The authors demonstrated a voltage flip using GIVFT to gain power transfer improvement in piezoelectric energy harvesting. Originality/value To the best of the authors’ knowledge, pertaining to the field of PEH, this is the first reported GIVFT based on the I-V relationship of the gyrator. The proposed approach could be useful for constrained self-powered autonomous IoT applications, and it could be of importance in guiding the design of new interface circuits for PEH.
{"title":"An inductorless piezoelectric energy harvesting interface circuit using gyrator induced voltage flip technique","authors":"Jitendra B. Zalke, Sandeepkumar R. Pandey, Ruchir V. Nandanwar, Atharva Sandeep Pande, Pravin Balu Nikam","doi":"10.1108/cw-08-2020-0188","DOIUrl":"https://doi.org/10.1108/cw-08-2020-0188","url":null,"abstract":"\u0000Purpose\u0000The purpose of this research paper is to explore the possibility to enhance the power transfer from piezoelectric energy harvester (PEH) source to the load. As the proposed gyrator-induced voltage flip technique (GIVFT) does not require bulky components such as physical inductors, it is easily realizable in small integrated circuits (IC) package thereby offering performance benefits, reducing area overhead and providing cost benefits for constrained self-powered autonomous Internet-of-Things (IoT) applications.\u0000\u0000\u0000Design/methodology/approach\u0000This paper presents an inductorless interface circuit for PEH. The proposed technique is called GIVFT and is demonstrated using active elements. The authors use gyrator to induce voltage flip at the output side of PEH to enhance the charge extraction from PEH. The proposed technique uses the current-voltage (I-V) relationship of gyrator to get appropriate phasor response necessary to induce the voltage flip at the output of PEH to gain power transfer enhancement at the load.\u0000\u0000\u0000Findings\u0000The experimental results show the efficacy of the GIVFT realization for enhanced power extraction. The authors have compared their proposed design with popular earlier reported interface circuits. Experimentally measured performance improvement is 1.86×higher than the baseline comparison of full-wave bridge rectifier circuit. The authors demonstrated a voltage flip using GIVFT to gain power transfer improvement in piezoelectric energy harvesting.\u0000\u0000\u0000Originality/value\u0000To the best of the authors’ knowledge, pertaining to the field of PEH, this is the first reported GIVFT based on the I-V relationship of the gyrator. The proposed approach could be useful for constrained self-powered autonomous IoT applications, and it could be of importance in guiding the design of new interface circuits for PEH.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46258543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image. Design/methodology/approach The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block. Findings Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs. Originality/value The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.
{"title":"Efficient partial product reduction for image processing application using approximate 4:2 compressor","authors":"Naresh Kattekola, A. Jawale, P. Nath, S. Majumdar","doi":"10.1108/cw-09-2020-0220","DOIUrl":"https://doi.org/10.1108/cw-09-2020-0220","url":null,"abstract":"\u0000Purpose\u0000This paper aims to improve the performance of approximate multiplier in terms of peak signal to noise ratio (PSNR) and quality of the image.\u0000\u0000\u0000Design/methodology/approach\u0000The paper proposes an approximate circuit for 4:2 compressor, which shows a significant amount of improvement in performance metrics than that of the existing designs. This paper also reports a hybrid architecture for the Dadda multiplier, which incorporates proposed 4:2 compressor circuit as a basic building block.\u0000\u0000\u0000Findings\u0000Hybrid Dadda multiplier architecture is used in a median filter for image de-noising application and achieved 20% more PSNR than that of the best available designs.\u0000\u0000\u0000Originality/value\u0000The proposed 4:2 compressor improves the error metrics of a Hybrid Dadda multiplier.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48720284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Iyappan Gunasekaran, Govindaraj Rajamanickam, Santhosh Narendiran, R. Perumalsamy, Kiruthika Ramany, R. Sankararajan
Purpose Various approaches have been made to alter the vibration sensing properties of zinc oxide (ZnO) films to achieve high sensitivity. This paper aims to report the experimental study of the fabrication of precursor molar ratio concentration varied ZnO nanostructures grown on rigid substrates using the refresh hydrothermal method. The effect of these fabricated ZnO nanostructures-based vibration sensors was experimentally investigated using a vibration sensing setup. Design/methodology/approach ZnO nanostructures have been grown using low temperature assisted refresh hydrothermal method with different precursor molar concentrations 0.025 M (R1), 0.075 M (R2) and 0.125 M (R3). Poly 3,4-ethylenedioxythiophene polystyrene sulfonate, a p-type material is spun coated on the grown ZnO nanostructures. Structural analysis reveals the increased intensity of the (002) plane and better c-axis orientation of the R2 and R3 sample comparatively. Morphological examination shows the changes in the grown nanostructures upon increasing the precursor molar concentration. The optical band gap value decreases from 3.11 eV to 3.08 eV as the precursor molar concentration is increased. Photoconductivity study confirms the formation of a p-n junction with less turn-on voltage for all the fabricated devices. A less internal resistance of 0.37 kΩ was obtained from Nyquist analysis for R2 compared with the other two fabricated samples. Vibration testing experimentation showed an improved output voltage of the R2 sample (2.61 V at 9 Hz resonant frequency and 2.90 V for 1 g acceleration) comparatively. This also gave an increased sensitivity of 4.68 V/g confirming its better performance when compared to the other fabricated two samples. Findings Photoconductivity study confirms the formation of a p-n junction with less turn-on voltage for all the fabricated devices. A less internal resistance of 0.37 kΩ was calculated from the Nyquist plot. Vibration testing experimentation proves an increased sensitivity of 4.68 V/g confirming its better performance when compared to the other fabricated two samples. Originality/value Vibration testing experimentation proves an increased sensitivity of 4.68 V/g for R2 confirming its better performance when compared to the other fabricated two samples.
目的采用多种方法改变氧化锌薄膜的振动传感性能，以获得高灵敏度。本文报道了用刷新水热法在刚性衬底上制备前驱体摩尔比浓度变化的ZnO纳米结构的实验研究。利用振动传感装置实验研究了这些制备的ZnO纳米结构振动传感器的效果。采用低温辅助刷新水热法制备zno纳米结构，前驱体摩尔浓度分别为0.025 M (R1)、0.075 M (R2)和0.125 M (R3)。将p型材料聚3,4-乙烯二氧噻吩-聚苯乙烯磺酸盐包覆在生长的ZnO纳米结构上。结构分析表明，相对而言，R2和R3样品的(002)面强度增加，c轴取向更好。形态学检查表明，随着前驱体摩尔浓度的增加，生长的纳米结构发生了变化。随着前驱体摩尔浓度的增加，光学带隙值从3.11 eV减小到3.08 eV。光电导率研究证实了所有制备的器件都能形成具有较低导通电压的pn结。与其他两种制备样品相比，Nyquist R2分析获得的内阻较小，为0.37 kΩ。振动测试实验表明，R2样品在9 Hz谐振频率下输出电压为2.61 V，加速度为1 g时输出电压为2.90 V。这也增加了4.68 V/g的灵敏度，与其他制备的两个样品相比，证实了其更好的性能。光电导率研究证实了所有制造的器件都能形成具有较低导通电压的pn结。根据奈奎斯特图计算出较小的内阻0.37 kΩ。振动测试实验证明其灵敏度提高了4.68 V/g，证实了其性能优于其他制备的两种样品。独创性/价值振动测试实验证明，R2的灵敏度提高了4.68 V/g，与其他制备的两个样品相比，证实了其更好的性能。
{"title":"Fabrication of vibration sensors using precursor molar concentration varied ZnO nanostructures grown by refresh hydrothermal method","authors":"Iyappan Gunasekaran, Govindaraj Rajamanickam, Santhosh Narendiran, R. Perumalsamy, Kiruthika Ramany, R. Sankararajan","doi":"10.1108/cw-08-2020-0183","DOIUrl":"https://doi.org/10.1108/cw-08-2020-0183","url":null,"abstract":"Purpose Various approaches have been made to alter the vibration sensing properties of zinc oxide (ZnO) films to achieve high sensitivity. This paper aims to report the experimental study of the fabrication of precursor molar ratio concentration varied ZnO nanostructures grown on rigid substrates using the refresh hydrothermal method. The effect of these fabricated ZnO nanostructures-based vibration sensors was experimentally investigated using a vibration sensing setup. Design/methodology/approach ZnO nanostructures have been grown using low temperature assisted refresh hydrothermal method with different precursor molar concentrations 0.025 M (R1), 0.075 M (R2) and 0.125 M (R3). Poly 3,4-ethylenedioxythiophene polystyrene sulfonate, a p-type material is spun coated on the grown ZnO nanostructures. Structural analysis reveals the increased intensity of the (002) plane and better c-axis orientation of the R2 and R3 sample comparatively. Morphological examination shows the changes in the grown nanostructures upon increasing the precursor molar concentration. The optical band gap value decreases from 3.11 eV to 3.08 eV as the precursor molar concentration is increased. Photoconductivity study confirms the formation of a p-n junction with less turn-on voltage for all the fabricated devices. A less internal resistance of 0.37 kΩ was obtained from Nyquist analysis for R2 compared with the other two fabricated samples. Vibration testing experimentation showed an improved output voltage of the R2 sample (2.61 V at 9 Hz resonant frequency and 2.90 V for 1 g acceleration) comparatively. This also gave an increased sensitivity of 4.68 V/g confirming its better performance when compared to the other fabricated two samples. Findings Photoconductivity study confirms the formation of a p-n junction with less turn-on voltage for all the fabricated devices. A less internal resistance of 0.37 kΩ was calculated from the Nyquist plot. Vibration testing experimentation proves an increased sensitivity of 4.68 V/g confirming its better performance when compared to the other fabricated two samples. Originality/value Vibration testing experimentation proves an increased sensitivity of 4.68 V/g for R2 confirming its better performance when compared to the other fabricated two samples.","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44309618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chun Hei Edmund Sek, M. Z. Abdullah, Kok Hwa Yu, Shaw Fong Wong
Purpose This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes. Design/methodology/approach This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results. Findings Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature. Research limitations/implications The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials. Practical implications This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process. Social implications The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment. Originality/value The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.
{"title":"Dynamic warpage simulation of molded PCB under reflow process","authors":"Chun Hei Edmund Sek, M. Z. Abdullah, Kok Hwa Yu, Shaw Fong Wong","doi":"10.1108/cw-02-2021-0061","DOIUrl":"https://doi.org/10.1108/cw-02-2021-0061","url":null,"abstract":"\u0000Purpose\u0000This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes.\u0000\u0000\u0000Design/methodology/approach\u0000This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results.\u0000\u0000\u0000Findings\u0000Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature.\u0000\u0000\u0000Research limitations/implications\u0000The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials.\u0000\u0000\u0000Practical implications\u0000This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process.\u0000\u0000\u0000Social implications\u0000The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment.\u0000\u0000\u0000Originality/value\u0000The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43439458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper aims to propose the reversible Feynman and double Feynman gates using quantum-dot cellular automata (QCA) nanotechnology with minimum QCA cells and latency which minimizes the circuit area with the more energy efficiency. Design/methodology/approach The core aim of the QCA nanotechnology is to build the high-speed, energy efficient and as much smaller devices as possible. This brings a challenge for the designers to construct the designs that fulfill the requirements as demanded. This paper proposed a new exclusive-OR (XOR) gate which is then used to implement the logical operations of the reversible Feynman and double Feynman gates using QCA nanotechnology. Findings QCA designer-E has been used for the QCA designs and the simulation results. The proposed QCA designs have less latency, occupy less area and have lesser cell count as compared to the existing ones. Originality/value The latencies of the proposed gates are 0.25 which are improved by 50% as compared to the best available design as reported in the literature. The cell count in the proposed XOR gate is 11, while it is 14 in Feynman gate and 27 in double Feynman gate. The cell count for the proposed designs is minimum as compared to the best available designs.
{"title":"Design of reversible Feynman and double Feynman gates in quantum-dot cellular automata nanotechnology","authors":"Sadat Riyaz, V. Sharma","doi":"10.1108/cw-08-2020-0199","DOIUrl":"https://doi.org/10.1108/cw-08-2020-0199","url":null,"abstract":"\u0000Purpose\u0000This paper aims to propose the reversible Feynman and double Feynman gates using quantum-dot cellular automata (QCA) nanotechnology with minimum QCA cells and latency which minimizes the circuit area with the more energy efficiency.\u0000\u0000\u0000Design/methodology/approach\u0000The core aim of the QCA nanotechnology is to build the high-speed, energy efficient and as much smaller devices as possible. This brings a challenge for the designers to construct the designs that fulfill the requirements as demanded. This paper proposed a new exclusive-OR (XOR) gate which is then used to implement the logical operations of the reversible Feynman and double Feynman gates using QCA nanotechnology.\u0000\u0000\u0000Findings\u0000QCA designer-E has been used for the QCA designs and the simulation results. The proposed QCA designs have less latency, occupy less area and have lesser cell count as compared to the existing ones.\u0000\u0000\u0000Originality/value\u0000The latencies of the proposed gates are 0.25 which are improved by 50% as compared to the best available design as reported in the literature. The cell count in the proposed XOR gate is 11, while it is 14 in Feynman gate and 27 in double Feynman gate. The cell count for the proposed designs is minimum as compared to the best available designs.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46421906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hongyu Du, Rongbo Yang, T. Gu, Xiang Zhou, Samar S. Yazdani, E. Sambatra, F. Wan, S. Lalléchère, B. Ravelo
Purpose The purpose of this paper is to introduce an innovative theoretical, numerical and experimental investigations on the HP NGD function. The identified HP NGD topology under study is constituted by first order passive RC-network. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about -1 ns and cut-off frequencies of about 20 MHz are obtained. Design/methodology/approach The identified HP NGD topology understudy is constituted by a first-order passive Resistor-capacitor RC network. An innovative approach to HP NGD analysis is developed. The analytical investigation from the voltage transfer function showing the meaning of HP properties is established. Findings This paper introduces innovative theoretical, numerical and experimental investigations on the HP NGD function. Originality/value The NGD characterization as a function of the resistance and capacitance parameters is investigated. The feasibility of the HP NGD function is verified with proofs of concept constituted of lumped surface mounted components on printed circuit boards. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about −1 ns and cut-off frequencies of about 20 MHz are obtained.
{"title":"Analysis, design and experimentation of high-pass negative group delay lumped circuit","authors":"Hongyu Du, Rongbo Yang, T. Gu, Xiang Zhou, Samar S. Yazdani, E. Sambatra, F. Wan, S. Lalléchère, B. Ravelo","doi":"10.1108/cw-07-2020-0131","DOIUrl":"https://doi.org/10.1108/cw-07-2020-0131","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to introduce an innovative theoretical, numerical and experimental investigations on the HP NGD function. The identified HP NGD topology under study is constituted by first order passive RC-network. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about -1 ns and cut-off frequencies of about 20 MHz are obtained.\u0000\u0000\u0000Design/methodology/approach\u0000The identified HP NGD topology understudy is constituted by a first-order passive Resistor-capacitor RC network. An innovative approach to HP NGD analysis is developed. The analytical investigation from the voltage transfer function showing the meaning of HP properties is established.\u0000\u0000\u0000Findings\u0000This paper introduces innovative theoretical, numerical and experimental investigations on the HP NGD function.\u0000\u0000\u0000Originality/value\u0000The NGD characterization as a function of the resistance and capacitance parameters is investigated. The feasibility of the HP NGD function is verified with proofs of concept constituted of lumped surface mounted components on printed circuit boards. The simulations and measurements confirm in very good agreement the HP NGD behaviors of the tested circuits. NGD responses with optimal values of about −1 ns and cut-off frequencies of about 20 MHz are obtained.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48463617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Multilevel inverters (MLIs) have been studied widely over the past two decades because of their inherent advantages and interesting features. However, most of the newly introduced structures suffer from the increased standing voltage of the switches, which is defined as the maximum off-state voltage on the switches, losing modularity and increased number of direct current (DC) voltage sources. The purpose of this study is to propose a new hybrid MLI topology to alleviate the mentioned problems. Design/methodology/approach The proposed approach in this study includes using the advantage of two different topologies and combine them in a way that the advantages of both of the topologies are achieved. Therefore, the approach is to design a hybrid topology from two existing topologies so that a new topology has resulted. Findings This paper proposes a new hybrid MLI with lower power electronic switches and lowers DC voltage sources in comparison with the classic structures. The proposed MLIs maintain a balance between the number of switches, the standing voltage on the switches and the number of DC sources. The topology description, modulation method and comparative study have been presented. Also, another more reduced structure is presented for higher power factor operation. The MATLAB simulation and experimental results of a nine-level inverter have been presented to verify its operation. Originality/value The hybrid topology has a new structure that has not been presented before. It is important to emphasize that the topology combination and achieving the hybrid topology is wisely accomplished to improve some features of the MLI.
{"title":"Extended hybrid cross-switched multilevel inverter circuit topology","authors":"S. Alizadeh, M. Farhadi‐Kangarlu, B. Tousi","doi":"10.1108/cw-03-2021-0067","DOIUrl":"https://doi.org/10.1108/cw-03-2021-0067","url":null,"abstract":"\u0000Purpose\u0000Multilevel inverters (MLIs) have been studied widely over the past two decades because of their inherent advantages and interesting features. However, most of the newly introduced structures suffer from the increased standing voltage of the switches, which is defined as the maximum off-state voltage on the switches, losing modularity and increased number of direct current (DC) voltage sources. The purpose of this study is to propose a new hybrid MLI topology to alleviate the mentioned problems.\u0000\u0000\u0000Design/methodology/approach\u0000The proposed approach in this study includes using the advantage of two different topologies and combine them in a way that the advantages of both of the topologies are achieved. Therefore, the approach is to design a hybrid topology from two existing topologies so that a new topology has resulted.\u0000\u0000\u0000Findings\u0000This paper proposes a new hybrid MLI with lower power electronic switches and lowers DC voltage sources in comparison with the classic structures. The proposed MLIs maintain a balance between the number of switches, the standing voltage on the switches and the number of DC sources. The topology description, modulation method and comparative study have been presented. Also, another more reduced structure is presented for higher power factor operation. The MATLAB simulation and experimental results of a nine-level inverter have been presented to verify its operation.\u0000\u0000\u0000Originality/value\u0000The hybrid topology has a new structure that has not been presented before. It is important to emphasize that the topology combination and achieving the hybrid topology is wisely accomplished to improve some features of the MLI.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49472572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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