Aeu-International Journal of Electronics and Communications最新文献

This work presents a 60 GHz continuously adjustable mm-wave cross-coupled voltage − controlled oscillator (VCO) utilizing an innovative frequency doubling technique in 40 nm CMOS technology. The extraction of the second harmonic is performed through a transformer from the tail of the 30 GHz fundamental VCO. The primary side of the transformer serves a dual purpose, functioning both as a filter for the second harmonic and as a balun simultaneously. The circuit incorporates a MOS varactor along with a four-bit binary weighed capacitor bank to achieve coarse and fine frequency tuning respectively. Post Layout simulation results indicate that the VCO spans a broad tuning range of 12.3 GHz, covering frequencies from 52.7 to 64.98 GHz. Phase noise (PN) remains below −96.3 dBc/Hz at a 1 MHz frequency offset within all bands Power consumption, including the output stage, is 21.8 mW from a 1.1-Volt supply. The VCO provides more than −13 dBm output power in all frequency bands and occupies a chip area of 0.53 $m{m}^2$.

This study investigates the sum secrecy rate $\left(S{R}_{sum}\right)$ of a simultaneous transmission and reflection reconfigurable intelligent surface (STAR-RIS)-enabled multiple input single-output (MISO) non-orthogonal multiple access (NOMA) downlink network with non-ideal hardware defects (HWDs) at the transceivers. Earlier STAR-RIS studies assumed an ideal phase shift model, with each element reflect and transmit the signal without regard to its phase shift. The proposed practical phase shift model accounts for the phase-dependent amplitude variation in the reflection and transmission (RAT) coefficients. The goal is to maximize the $S{R}_{sum}$ through an alternating optimization (AO) iterative algorithm, leverages a classical semidefinite relaxation (SDR) for beamformer vector design (BVD), and employs an interior point method (IPM) to calculate NOMA power allocation factors $\left({\alpha }_t,{\alpha }_r\right)$. The analysis focuses on the evaluation of the $S{R}_{sum}$ in scenarios with eavesdroppers, under the consideration of both ideal and practical phase shift cases. The study examines the impact of different non-ideal HWDs on the $S{R}_{sum}$ of the system and provides insights into vulnerabilities and limitations arising from these effects.

The advent of 5G networks has introduced new challenges for network operators, particularly in terms of coverage, capacity, and service quality. Consequently, it is crucial to monitor and assess network performance to detect irregularities and enhance functionality and deployment efficiency. This is especially important for Non-Standalone (NSA) 5G networks, which rely on existing 4G infrastructure and may not fully utilize the advanced capabilities of 5G technology. This study evaluates wireless system/network performance, focusing on key quality indicators and data throughput within typical town settings featuring various operational scenarios. To achieve this, portable smartphone devices were employed to simultaneously measure real-world data from all 5G and 4G networks, providing a comparative analysis across all (three) cellular network providers in the area.

Results highlight differing 5G rollout strategies and performance across operators, revealing that broad coverage may struggle with congestion issues, while a tailored deployment approach could yield better results. Additionally, the analysis pinpoints performance challenges related to coverage, throughput, resource utilization, and interference, thus guiding enhancements in 5G network deployments and establishing a baseline for tracking the evolution of 5G performance.

A compact wideband bandpass filter (BPF) based on capacitor-loaded parallel coupled-lines and open/short stubs is presented in this brief. The proposed BPF contains four lumped capacitors that can reduce the circuit size, which are connected in series or parallel with the coupled microstrip lines and open/short stubs. Owing to the symmetry of the circuit topology structure, odd- and even-mode methods are used for analysis, then the 3-dB fractional bandwidth (FBW) and return loss (RL) can be calculated by MATLAB using impedance deduction of each branch circuit. To demonstrate the feasibility of the proposed design, a wideband BPF prototype with a center frequency of 0.23 GHz and a 3-dB FBW of 117.8 % is fabricated and measured, which exhibits a miniaturized size of 0.026λg × 0.079λg (λg: guided wavelength at the center frequency). The results of experiment are very consistent with theoretical calculations, circuit and electromagnetic simulations, validating the concept of the proposed technique.

In this article, we propose a substrate-integrated suspended line (SISL) vertical transition for chip packaging. The transition structure supports both counter-directional and co-directional modes for single-module packaging and vertical integration, respectively. Furthermore, the incorporation of an electromagnetic band gap (EBG) reduces the demands on substrate electrical contact and simplifies the assembly process. A transition structure was designed to convert SISL to a grounded coplanar waveguide (GCPW) to facilitate measurement. The overall structure can be implemented using cost-effective printed circuit board (PCB) technology. Two prototypes of this transition were designed and fabricated. In the frequency range of 12–18 GHz, corresponding to a fractional bandwidth of 40%, the measured return loss is better than 12 dB, while the insertion loss remains consistently below 2.2 dB.

In conjunction with an algebraic, exponential, complementary error function, and a generalized Q-function, this paper provides analytical solutions for the integral of the bivariate Fox H-function (BFHF). The paper also includes derivative identities related to function arguments. The proposed formulations are then applied for analyzing the performance of point-to-point wireless communication subjected to fading, the characterization of which involves the bivariate Fox H-function, and additive white generalized Gaussian noise. Novel expressions are presented for evaluating the average symbol error probability performance considering different noise distributions, such as Gamma, Gaussian, and Laplacian. An asymptotic analysis is also conducted to determine the system’s potential diversity order. Finally, the accuracy of the analytical findings is confirmed via comparisons of numerical results with Monte-Carlo simulations.

A high-speed dynamic comparator with preamplifier and automatic dc offset calibration in all stages is proposed in this paper. The offset compensation is applied in two stages, following a two-part sequential loop training topology, offering significant reduction of the dc offset in each stage. The final resolution is improved with a final value less than 800 μV operating at 7.5 GHz clock speed. The dynamic comparator stage is a double-tail topology while the calibration topology is based on a current injection technique, instead of the commonly used capacitive calibration which can reduce the operating speed. Designed in a CMOS 65 nm technology node, the circuit operates with 1 V supply voltage. Results of PVT Monte Carlo post-layout simulations verify the operation of the proposed topology.

This paper proposes a high-precision Sigma Delta ADC for automotive electronic sensors and delves into methods for optimizing quantizers and filters, with a focus on DPOQ quantizers and hybrid CIC filters. This ADC features a Dual-path One-bit Quantization (DPOQ) System, which improves the accuracy of Sigma-Delta ADCs while reducing hardware consumption. Meanwhile, this paper presents a new multistage digital filter. The filter uses a cascade of multiple filters, including cosine-like (CL), cascaded integral comb (CIC), interpolated second-order polynomial (ISOP), and half-band (HB) filters, to enhance the ADC’s accuracy. The filter are designed using canonical signed digit (CSD) and common subexpression (CSE) optimized the design algorithm of the filter, to reduce hardware resource consumption and improve computational performance. The ADC is synthesized using 180 nm CMOS technology, achieving an output SNDR of 96.26 dB, ENOB of 15.73 bits, and total power of 518.35 uW.

This paper introduces an innovative design of a substrate-integrated waveguide (SIW)-based self-heptaplexing antenna (SHA). The proposed structure is implemented using a combination of circular and rectangular HM-SIW cavities. Furthermore, the antenna contains seven individual patches on top of the SIW cavity to operate at seven distinct frequencies. The microstrip feeding technique has been used to activate seven distinct ports. All patches are excited through 50-ohm feedlines. The antenna operation is elucidated using an equivalent LC model. To demonstrate its operating principles a self-heptaplexing antenna has been designed to work at 2.45, 3, 3.58, 4, 4.45, 5.2, and 5.88 GHz. The measured realized gain of the proposed antenna at the respective bands is 3.2, 3.85, 3.1, 3.245, 4, 2.98, and 4.5 dBi. The isolation exceeds 20 dB over the entire working bands. The EM-simulated and measured characteristics are in good agreement. Although the suggested antenna has been designed for seven ports and lower frequencies, it has a relatively compact size of 0.28 ${\lambda }_g^2$. The major advantages of the proposed self-heptaplexing antenna include excellent isolation, an ultra-compact design, and good radiation characteristics. The proposed antenna offers a high degree of flexibility. It allows for independent frequency tuning, which makes it suitable for IoT, wireless communication systems, and diverse sub-6 GHz band applications.