Aeu-International Journal of Electronics and Communications最新文献

This article presents a compact microstrip low-pass filter (LPF) with a sharp roll-off rate (ROR) and an ultra-wide stopband for modern telecommunication applications. To achieve a relatively sharp transition band (−3 dB and −40 dB at the cut-off frequencies of 1.3 GHz and 1.57 GHz, respectively), a modified fifth-order circuit has been presented as the primary resonator. The frequency response of the primary filter is then enhanced by incorporating a few stubs in the primary resonator structure, which act as harmonic suppressors and help create a wide stopband. Simulation results show that the proposed LPF has a wide stopband width of approximately 28.43 GHz (from 1.57 to 30 GHz). The proposed LPF is fabricated on Rogers substrate with a total footprint of 35.3 mm × 15.9 mm. The measured values of ROR, suppression factor (SF), relative stopband band (RSB), and figure of merit (FOM) (137 dB/GHz, 2.2, 1.92, and 54,082, respectively) present the proposed LPF as a suitable choice for state-of-the-art communication circuits.

In this study, a static-RAM cell using the Gnr-GDI method is proposed as a weak-type physical unclonable function (PUF) circuit to generate a unique and stable binary output for secure IoT devices. Regarding the memory level, a suitable combination of dynamic body bias, stacked networks, and multi-V_th techniques has been used in the architecture of asymmetric cell-structure inverters as a latch section to reduce power consumption and improve hardware efficiency. In addition, the logic styles of virtual ground and power gating based on word and BL data lines and a tri-state buffer structure have been used to extend the write VTC and improve read stability, respectively. From the perspective of PUF performance, the body of the latch section can form skewed VTCs based on the setting of critical parameters in GnrFET technology to achieve an efficient PUF circuit design.

At the memory performance level, the Monte Carlo (MC) method-based results confirm the reasonable performance of the proposed structure in terms of static noise margin (SNM) and hardware efficiency, such as 53 % delay and 72 % energy-delay product (EDP) parameters, compared with the 6 T SRAM structure in a similar 16 nm GnrFET technology. In addition, in terms of the performance as a PUF circuit, the simulation results demonstrate the superiority of the proposed cell in terms of energy consumption, BER, response time, uniqueness, and stability under non-technological variation conditions of temperature and supply voltage. The outstanding performance results of the figure of merits (FoMs), CEQM, and UR², which are composed of variability, energy, reliability, and layout-level factors, indicate the suitability of the proposed memory architecture for use in both the memory and PUF modes.

Furthermore, to investigate the application level, memory structure has been used to store fingerprint images as PUF data using a hardware algorithm. The results of the proposed comprehensive FoM, which is based on the simultaneous consideration of circuit level and quality parameters, indicate that the proposed memory scheme in a bit-interleaved architecture-compatible design can be introduced as a high-performance candidate for generating and storing unique binary data in PUF-based IoT platforms.

Since multiplication is a complex and resource-consuming operation, it is very effective on the speed performance of a processor. In this regard, fast multiplication unit design is important in digital system architectures. FPGA hardware, which is efficient for the implementation and rapid prototyping of today’s digital system architectures, is becoming widespread. Therefore, in this study it aimed to design a fast radix-16 Booth multiplier based on the FPGA architecture. Booth multiplier implementation is preferred because it is relatively simple and efficient. The sizes of the multiplexers, which have an impact on the operating period in the encoder part of the proposed multiplier, reduced in the designed architecture by using a simple algorithm. To increase the speed performance of the system, the pipeline technique is used and parallelization is preferred in the tree structure in addition of the partial products. The effects of different multiplexer sizes, bit lengths and pipeline stages on the operating period of the system and other performance metrics examined. Different designs and the results obtained presented. According to the results, the multiplier hardware architectures designed in this study exhibit effective results in terms of speed performance.

A novel S/Ka dual-band dual-circularly polarized (CP) shared-aperture antenna is proposed in this paper. In the Ka-band, the reflectarray adopts two distinct CP elements, both of which achieve 360° phase shift and linear phase response in the wideband. In the S-band, the radiation array adopts a 4 × 4 units cut-corner square patch to achieve CP performance. Additionally, a steerable beam is achieved through a phase shift feeding network. To effectively improve the antenna aperture utilization and efficiency, the S-band radiator is reused as a part of the Ka-band reflecting ground to realize the aperture-sharing. Experimental results demonstrate that the S-band operating bandwidth covers 2.35–2.7 GHz, achieving a peak gain of 18.6 dBic and an aperture efficiency of 89.2 %. Furthermore, the S-band enables ± 30° beam steering. In the Ka-band, the operating bandwidth covers 28–32 GHz, with a measured 2-dB axial ratio bandwidth is 10.3 %, a peak gain of 37.5 dBic, and an aperture efficiency of 48.1 %. Therefore, a dual-band dual-CP shared-aperture antenna with high aperture efficiency is realized. The antenna offers beam steering in the S-band and wideband capabilities in the Ka-band, making it a valuable candidate for satellite communication systems.

In this paper, a compact wideband bandpass filter with multiple transmission zeros and a wide upper stopband is proposed based on the transversal signal-interaction concept. The filter has two transmission paths for signals to travel from the input port to the output port. The wideband bandpass filter is designed with a center frequency of 4.29 GHz (f₀) and a 3-dB fractional bandwidth of 71.3 %. Six transmission zeros from 0 GHz to 4.2 f₀ can be achieved due to the superposition of signals of the two transmission paths and the virtual short effect of open stub. The designed and fabricated wideband bandpass filter is of minimum insertion loss of 0.3 dB, group delay in the passband below 1.1 ns, and upper-sideband rejection up to 18 GHz (4.2 f₀). Additionally, the proposed filter possesses compact size, and the overall circuit only occupies 0.23 λ_g × 0.15 λ_g (λ_g is the guide wave length of 50 Ohm microstrip line at 4.29 GHz). Measurement and simulation results are in good agreement.

Digital pre-distortion (DPD) technology is currently the dominant technology employed to compensate for the nonlinearity of power amplifiers (PAs). Recently, PA modeling methods based on machine learning have attracted much attention. However, the traditional model still suffers from the defects of long modeling time or insufficiently high modeling accuracy. To solve this problem, the global representative point selection (GRPS) algorithm and the randomized SVD (RSVD) algorithm based on the least squares twin support vector regression (LSTSVR) model are introduced. The GRPS algorithm is first used to select a specific number of globally representative points from all the data to construct the support vector set. Then the RSVD algorithm is used to perform a low-rank approximation to the target kernel matrix. The modeling performance of the proposed approach is compared with the existing model using different communication signals, and the results show that the proposed model can improve the modeling accuracy and reduce the modeling time. Further, a pre-distortion experimental platform is established, and the proposed model is used to pre-distort the Class F PA and the Doherty PA respectively, which proves that the proposed model has a good nonlinear correction effect.

Composite right/left-handed transmission line leakywave metamaterial antenna with ability of space scan by changing frequency and at a fixed frequency with lumped element is designed in this study. Considering the ability to rotate antenna beam by changing the frequency of the leakywave antenna, the rotation of the desired antenna pattern was evaluated by changing the frequency. The introduced antenna can scan a wide spatial area from ${-15}^{°}$ to ${+42}^{°}$ by changing the frequency in the 2.5 GHz bandwidth (from 9 to 11.5 GHz) without a stop band and with maximum gain of 15 dB. In the second part, by placement three Lumped elements (capacitors) in each unit cell of mentioned CRLH-TL leakywave antenna that has the ability to scan the space in several fixed frequencies (9.6–10-10.4–11 GHz) has been designed. In this case, the antenna can scan from ${-5}^{°}$ to ${+12}^{°}$ at 9.6 GHz and from ${+15}^{°}$ to ${+46}^{°}$ at 11 GHz with an average gain of 11 dB. For wider scanning in negative and positive angles, it is suggested to use a double-port switch to feed from both inputs of the CRLH-TL leakywave antenna to increase the overall space scanning angle.

In this paper, a balanced bandpass filter (BPF) with common-mode reflectionless and linear-phase characteristics is proposed, which consists of a balanced 3-order bandpass filtering network and two common-mode absorptive networks to obtain the common-mode reflectionless and suppression performance. The negative group delay circuits are loaded on the proposed balanced BPF to realize the full-passband linear-phase filtering performance. The flatter the group delay of the BPF (the fluctuation of the group delay within the passband tends to 0), the better the phase-frequency linearity, which will realize the undistortion transmission of the communication systems. For demonstration, a balanced linear-phase BPF prototype operating at 1.5 GHz is designed, simulated, and manufactured. The results demonstrate that the group delay fluctuation is reduced from 1.20 ns to 0.11 ns by 90.8 %, the differential-mode insertion loss is 1.04 dB, the minimum common-mode suppression is 59.3 dB within the passband and the common-mode reflectionless band is 1.22–1.91 GHz. The developed topology requires high precision in the processing, and the proposed balanced BPF can be applied to digital microwave communication systems to improve the transmission quality and reduce the bit error rate.

This paper presents novel high speed low power comparator that can further be used in analog to digital converter (ADC) circuits for Internet of Things (IoT) applications. Both circuits employ self cascode technique in preamplifier stage of conventional comparator. The proposed comparator 1 uses a static latch in second stage whilst dynamic latch is used as second stage in proposed comparator 2 to take advantage of low power. Simulations are carried out at 90 nm CMOS technology node in Cadence Virtuoso environment. Self cascode preamplifier stage shows better gain (40 %) than conventional counterpart leading to improvement of 45 % in power with 65 % lesser delay. The mathematical formulation of the delay of proposed comparators is also put forward. Post layout simulation results for delay, power, energy and area of proposed comparator 1 are observed to be 110 ps, 65uW 78fJ/conversion energy and 151um² respectively. The corresponding data for proposed comparator 2 is 81 ps, 61uW, 56 fJ/conversion energy and 137um². These results are found to be in much better proposition than other state-of-the-art works. Additionally, the performance of conventional and proposed comparators is examined using Monte-Carlo simulations and corner analysis. The proposed comparators outperform under these analyses also.

A broadband slot antenna array based on metasurface with gain stability is proposed for the 5 GHz wireless local area network (WLAN) band in this paper. Firstly, multi-mode resonant theory is used to widen the bandwidth of the slot antenna. Then, a non-uniform rhombic metasurface is placed above the slot antenna to expand the bandwidth of the antenna further while increasing the gain. Finally, nine rectangular patches are placed at the non-uniform rhombic metasurface. And the current in the high-frequency is amplified which leads to the maximum gain variation of only 1.7 dBi across the entire operating frequency range (4.7–7.7 GHz). To verify the design, a 2 × 2 antenna array is fabricated. The antenna array achieved a bandwidth of 47.6 % (4.8–7.8 GHz) and a maximum gain of 15.2 dBi within the operating band. The 1 dBi gain bandwidth is 2.1 GHz (4.7–6.8 GHz).