Aeu-International Journal of Electronics and Communications最新文献

This article explores different techniques to improve the impedance bandwidth of on-chip dipole antennas in the sub-THz frequency range. Increasing the area of the dipole antenna has shown considerable improvement in bandwidth. However, this violates the design rule checks (DRC) of the foundry. Various topologies, such as squared-slotted dipole, meandered-slotted dipole, and straight-slotted dipole antennas, are introduced and implemented to increase the width of the on-chip antennas and thus the impedance bandwidth while meeting the DRC rules. All three topologies show better performance in terms of providing improved bandwidth. The straight-slotted technique is adopted as it offers less complexity and flexibility. The behavior of the impedances for different widths implemented by the straight-slotted topology has been analyzed in detail. A 6-strip straight-slotted dipole antenna results in an ultra-wide impedance bandwidth ranging from 76–262 GHz with a fractional bandwidth of 110% and a gain of −0.6 dBi at 159 GHz, while occupying a small silicon area of $567\mu m\times 112\mu m$. To the best of the authors’ knowledge, this is the highest fractional bandwidth that is reported to date at these frequencies.

This work presents an Exponential Variation based Particle Swarm Optimization (EV-PSO) algorithm to improve the convergence rate and find an optimal solution to analog circuit optimization problems in a constrained-driven environment. Existing evolutionary algorithms have a lower convergence rate leading to higher design time. This work introduces two novel parameters, ${\zeta }_1$ and ${\zeta }_2$, into the velocity update equation. These parameters dynamically vary with the number of iterations. The algorithm was implemented on the Python platform. The results have shown that, in comparison to the considered existing methods, the exponential variation of the parameters ${\zeta }_1$ and ${\zeta }_2$ in the proposed algorithms have a larger rate of convergence. The proposed EV-PSO has a convergence rate of 27 iterations, which is 57.8%, 65.38%, and 59.1% better than the conventional PSO, differential evolution (DE) and genetic algorithm (GA) respectively. The typical design obtained from the optimal solution is verified through the simulation using 45-nm CMOS technology. The optimal solution presented in this work meets the desired input specifications within the specified constrained environment.

This paper presents a high-performance integrated monolithic ceramic dielectric waveguide (DW) filter featuring isosceles right-angled triangular (IRAT) resonators. The fabrication process of the filter involves embedding a specific number of blind holes (BHs) or through holes/slots (THs/TSs) in a hexagonal ceramic dielectric block, fully metallizing the dielectric surface, and forming a monolithic ceramic DW filter. To achieve magnetic coupling, four THs and a BH are introduced in the oblique edges of two IRAT resonators; alternatively, a TS and BH are introduced in their right-angled edges. Electrical coupling is realized through a deep BH on the right-angle side of the resonators. Two non-adjacent resonators initiate weak cross-coupling by cascading a T-shaped rectangular TS, shallow BHs, and deep BH, creating two transmission zeros (TZs) outside the band. The filter was fabricated to ensure theoretical correctness and process reliability. The measured results show an insertion loss between 0.5 – 1 dB and a return loss greater than 18 dB at a bandwidth of 3.4 – 3.6 GHz. Two steep out-of-band TZs occur at 3.26 GHz and 3.72 GHz, aligning with simulation results. Therefore, the filter not only exhibits excellent performance but is also convenient for mass production and manufacturing, offering significant potential for future applications in 5G / 6G communication base stations.

This paper presents an inverted F-shaped slotted broadband metasurface (MS)-based circularly polarized (CP) microstrip patch antenna. The host antenna comprises a truncated corner square patch with an inverted F-shaped slot, positioned on a 1.6 mm thick FR-4 substrate backed by ground plane. Concurrently, the MS layer is composed of a 4 × 4 square ring array, constructed on a separate 1.6 mm thick FR-4 substrate with net compact dimensions 0.54λ_o × 0.54λ_o × 0.027λ_o at 5.13 GHz, serving as a superstrate layer. The proposed antenna exhibits impressive performance, including a −10-dB impedance bandwidth from 4.40 GHz to 7.38 GHz as well as a 3-dB axial ratio (AR) bandwidth from 4.74 GHz to 5.52 GHz. Furthermore, at 5.13 GHz, it achieves a notable maximum radiation efficiency and realized gain of 85 % and 6.95 dBic respectively. Moreover, polarization of the antenna is observed as left-handed circularly polarized (LHCP). To validate the impedance response, the antenna’s equivalent circuit model has been sequentially developed, followed by the fabrication of a prototype. The measured results closely resemble with the simulated responses, indicating strong consistency between theory and experimental results. With its overall compact dimension of 0.65λ_o × 0.65λ_o × 0.027λ_o at 5.13 GHz, the proposed CP antenna is well-suited for 5G application.

This paper proposes a Doherty power amplifier (DPA) design method based on harmonic tuning and output combining network (OCN) optimization to extend the power back-off (PBO) range. Firstly, based on the optimal harmonic load impedance, a harmonic tuning optimization method is used to design the harmonic tuning network of the amplifiers, effectively improving the efficiency at saturation and PBO. Secondly, the fundamental output matching network and the post-matching network are considered as an OCN. The S-parameters of the OCN are calculated and utilized in the DPA design. To further expand the PBO range, the carrier load impedance at PBO is determined by considering the relationship between PBO range and reflection coefficient. Finally, a multi-objective evolutionary algorithm combined with the theory of solution set is used to optimize the OCN design, simplifying the design process of the output matching network. For verification, a high-efficiency DPA operating at 1.68 GHz with a large PBO range of 9.5 dB is designed and measured. Results indicate that the proposed DPA achieves a saturated output power greater than 44 dBm, with a peak efficiency of up to 75.2%. The efficiencies are 68.5% and 61.0% at 6 and 9.5 dB back-off powers, respectively.

Autonomous driving systems consist of vehicles that are able to communicate not only with other vehicles but also with entities in their environment, forming vehicle-to-everything (V2X) communication. However, the V2X applications have intense requirements posing a significant challenge to the telecommunication infrastructure. In this work, we consider two types of transmission, i.e. direct and indirect, and we utilize analytical traffic-engineering models with a view to conduct a performance analysis of a vehicular network that enables V2X communication. We additionally propose two resource management strategies in order to decrease the request rejection probability and consequently ensure enhanced communication conditions. The results reveal that the proposed resource management strategies constitute a strong asset for improving the system’s service provisioning capability.

This communication describes the development and assessment of the genuine Antipodal Vivaldi MIMO antenna operating in the ultra-wideband spectrum. FR4 dielectric material, which is widely used in antenna designs and has characteristic features, is selected and used as a dielectric. The single antenna component has two asymmetric flares obtained with different parameters, and it also has a rectangular ground plane combined with a bottom flare. In the MIMO configuration, the single-antenna is built in a rotationally orthogonal way to generate a four-port system with the dimensions of 45 × 45 × 1 mm³. The vertical and horizontal stubs are added to the ground flare to obtain a common ground structure and increase the performance of the novel antenna design. It has a bandwidth of approximately 9 GHz, which starts from 2.85 GHz and ends at 11.8 GHz. The antenna has reasonable gain values and a high isolation value between the elements in the operation range. In this context, it is foreseen that the developed structure can be utilized in distinct multiport UWB applications.

A reconfigurable ultra-wideband multimode terahertz OAM antenna array based on graphene and vanadium dioxide (VO₂) is presented in this paper. The uniform circular array (UCA) composed of circularly polarized (CP) antennas, which include a ring radiation patch, a parasitic patch, a perovskite substrate and an irregular VO₂ ground plane. The radiation patch is covered with a layer of graphene, by changing the chemical potential of graphene, the working bandwidth and axial ratio bandwidth of the antenna can be changed. By changing the phase state of VO₂ (metal state / insulation state) to control the working state of the antenna. The impedance bandwidth (IBW) of the CP antenna proposed is 115.09% (1.73–6.42 THz), the axial ratio bandwidth (ARBW) is 43.97% (2.36–3.69 THz). Using the CP antenna unit can simplify the complex feed network, and only feeding the equal amplitude and equal phase excitation can realize the vortex wave. Changing the number and rotation angle of the antenna unit can realize multimode vortex waves with the l= 0, ±1, ±2, ±3, the purity is approximately 1, respectively. The proposed UCA has excellent application prospect in the 6G communication.

This work presents an innovative Ultra-Wideband (UWB) antenna design inspired by metamaterials. The antenna features spatial and polarization diversity, operating efficiently over a broad frequency range of 3.3 to 13.84 GHz. The design consists of four orthogonally arranged monopoles in a co-planar setup, meticulously engineered with ground plane slots to mitigate mutual coupling effects. The antenna demonstrates resilient performance, maintaining mutual coupling isolation exceeding 14 dB between its radiating elements for most of the operating band.

Due to the rise in data-intensive applications, the von Neumann bottleneck is increasingly restricting modern computer architectures, resulting to latency and energy consumption. Addressing this challenge necessitates a CMOS-compatible solution with high energy efficiency and significant parallelism. Utilizing resistive switching components within a 1T1R crossbar array and the application of Stanford RRAM model, this paper suggests an original method for in-memory computing. Moreover, this work shows a new way to advance the popular RISC-V architecture by including memristive crossbar array. It does this by adding a custom instruction set, special hardware blocks, and the Scouting Logic Scheme. These modifications serve both as a comprehensive testbed for the memory system and a proof of concept for the future integration of memristors in computing architectures. The proposed design undergoes extensive testing and power analysis to validate its functionality and performance under various conditions. The results demonstrate significant improvements in computational efficiency and energy savings, highlighting the potential of memristor-based in-memory computing systems to overcome current architectural limitations.