This paper proposes high-performance, low-power Phase-Locked Loop (PLL) architecture designed using transmission-gate-based Phase Frequency Detector (PFD) and 12-transistor-based MOS Charge Pump (CP) implemented using the SCL 180 nm CMOS process and simulated in Cadence Virtuoso environment. The proposed PFD eliminate blind zones and reduces dead zone to 4 ps through direct reset mechanism, operating over 1–6.5 GHz frequency range using only eight transistors, resulting in a low power consumption of 171.2 W and phase noise of –156.4 dBc/Hz at 1 MHz offset. The proposed CP achieves minimal current mismatch of 0.33 % while consuming 181.8 W. The proposed PFD-CP is integrated with a conventional loop filter, voltage-controlled oscillator and frequency divider to design a 2.5 GHz PLL, which achieves lock time below 20 ns and spur-to-floor delta of 72.07 dB. The compact core area of 0.0014 mm and power consumption of 338.8 W are achieved. It demonstrates that approximately 80%–85% smaller area and 75%–90% lower power consumption compared to recent state-of-the-art, along with 10 dB improvement in spur suppression and two-times faster locking response, highlighting its efficiency and scalability for high-speed, low-spur, low-jitter Serializer–Deserializer (SERDES) and clock recovery systems. The Monte Carlo simulation and Process, Voltage, Temperature (PVT) analyses confirm robust performance of the design.
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