Aeu-International Journal of Electronics and Communications最新文献

In this paper, highly selective dual-mode microstrip bandpass filters (BPFs) are presented utilizing novel square patch resonator loaded with short via and periodic metallic vias array. Characteristics of the patch resonator are studied, and a new nondegenerate dual-mode patch resonator operating with the second and third higher-order modes is proposed. A two-pole BPF based on one dual-mode patch cavity is analyzed, and two transmission zeros (TZs) are produced. To realize higher-order filtering responses, four-pole BPFs with two cascaded dual-mode patch resonators are proposed, and different cascaded methods of two dual-mode patch resonators by a λ_g/4 microstrip connecting line (MCL) are analyzed and compared to maintain high selectivity and small size. For the demonstration, two four-pole filters with the center frequency at 3.3 GHz and five transmission zeros is designed, fabricated and measured.

This paper presents a novel multi-core multi-mode electric-magnetic (E-M) mixed-coupling voltage-controlled oscillator (VCO), achieving wide tuning range and phase noise optimization simultaneously through a multi-core structure. A symmetric multi-mode resonator is proposed to address the issue of differential signal mismatch caused by transformer asymmetry. An inductor ring is used to balance the inductance of each mode and its effect in each mode is analyzed in detail. A symmetrical switch network is employed for mode switching, offering advantages such as reduced parasitics and mismatch. The utilization of a varactor combined with a fixed capacitor enables electrical coupling, ensuring overlapping frequency bands even with variations in process, voltage, and temperature (PVT), and extending the tuning range. Furthermore, a switched resistor array is employed to bias the negative resistance pair and minimize the contribution of 1/f noise upconversion to the phase noise. Designed in a 40-nm complementary metal–oxide–semiconductor (CMOS) technology with a core area of 0.16 mm², the VCO achieves a simulated continuous tuning range of 81.5%, spanning from 11.1 to 26.4 GHz. Operating at a 1.1 V supply with a power consumption of 16 mW, the phase noise at 12.15 GHz is −118.6 dBc/Hz at a 1 MHz offset, corresponding to a figure-of-merit (FoM) of 188.3 dBc/Hz and a FoM_T of −206.3 dBc/Hz.

In the context of next-generation 5G and beyond communication networks, integrating Unmanned Aerial Vehicles (UAVs) with Mobile Edge Computing (MEC) is crucial. Hybrid Non-orthogonal Multiple Access (H-NOMA) has been recognized as a prominent technique for reducing energy consumption during data offloading. However, the literature assumes that all users in the cluster have latency requirements and interference levels such that implementing H-NOMA is optimal, overlooking other scenarios. Furthermore, the position of UAV-hosted MEC is not optimized. To address these constraints, we propose an adaptive offloading method where users can utilize either H-NOMA or OMA for data offloading in designated time slots based on their conditions. We substantiate this proposal through a comparative analysis of energy consumption between H-NOMA and OMA. Additionally, we introduce a novel Maximum Latency Difference Clustering and Power Allocation (MLDC & PA) algorithm for organizing smart terminals (STs) and allocating power. Furthermore, we propose a heuristic-based optimization approach for UAV positioning to minimize offloading energy and enhance network efficiency. Simulation results confirm that the proposed approach has superior energy consumption reduction capabilities compared to state-of-the-art techniques.

In sonar detection, underwater recognition, and similar fields, the challenge of using small-scale arrays is frequently encountered. With small-scale arrays, the degrees of freedom (DOFs) and accuracy of direction of arrival (DOA) estimation decrease significantly. Moreover, existing algorithms are less robust in complex environments and typically require substantial computing resources to ensure accurate estimation. To overcome these problems, this paper proposes a high-resolution DOA estimation via Random Forest virtual array extension (RFVAE). The algorithm first trains the random forest (RF) network using real array element data, and thus proposes a virtual covariance reconstruction technique. This technique allows for a substantial increase in the number of virtual array elements. Then, based on the virtual covariance reconstruction technique, a high resolution estimation network technique is proposed, which can increase the accuracy and DOFs of DOA estimation. Experimental results show that the proposed algorithm reduces error by 30% to 80% compared to recent technologies and can provide up to twice as many virtual elements. Additionally, the estimation speed can be increased by 3 to 1000 times, and it has significantly stronger robustness, functioning normally at signal-to-noise ratios 10 dB lower than the conditions under which other algorithms fail.

In recent times, there has been a significant focus on creating prosthetics and medical interventions to aid in the treatment of diseases, recovery, and the improvement of biological functions. Researchers have particularly directed their attention toward developing hardware models for delicate biological parts such as the brain, heart, nervous system, and. One area of particular interest is the retina, which is the thinnest and innermost layer of the eye. This research paper focuses on the development of a high-speed and low-error hardware implementation for retinal cone and rod cells. Current mathematical models often use multiple nonlinear functions to describe the behavior of these cells. However, these nonlinear functions can sometimes be limiting in terms of speed. In this study, we explore the use of trigonometric functions to approximate the non-linear properties of retinal cone and rod cells, allowing for improved performance. The results of the simulation show that the suggested model is in line with the functioning of primary cone and rod cells, particularly in relation to time characteristics, dynamic response, and margin of error. By implementing the proposed model in Large-Scale (300 cell) on a Virtex-5 Field Programmable Gate Array (FPGA) board, notable benefits were observed. One of these advantages includes increasing the synthesis frequency of the proposed model by 3.35 and 3.44 times faster than the original model for the cone cell and rod cell, respectively. Another advantage is the ability to implement 300 cells of the proposed models on the FPGA, compared to the implementation of a single cell of the original models, with only a two-fold increase in the amount of hardware resources used. The proposed framework is legitimate and features a compact hardware size and suitable network frequency, as demonstrated by the outcomes from implementing the hardware on the Virtex-5 reconfigurable board (FPGA).

This paper presents a reconfigurable buck-boost Charge Pump (CP) based on the cross-coupled topology. The proposed CP is a switched capacitor (SC) converter merging different ratios and operation modes in one topology. The converter is able to step-up or step-down the input voltage at the output only by controlling the external connections of the circuit. By achieving various conversion ratios and operation modes, higher efficiency levels are performed maximizing the power that is delivered to the load. The reconfigurable buck-boost CP has been designed in 65 nm TSMC CMOS technology and covers an input voltage range from 1.6 V to 3.2 V and an output voltage range also from 1.6 V to 3.2 V in the boost mode and an input voltage range from 2.6 V to 3.6 V and an output voltage range from 1.4 to 1.8 V in the buck mode. In addition, efficiency estimation analysis is presented and proves how parasitic capacitances of flying capacitors affect the overall efficiency of a multi-ratio converter. The converter indicates peak efficiency equal to 77 % and delivers up to 4 mA load current.

This article presents a simple and effective method for designing a dual-band power amplifier (PA). A microstrip coupled-line bandstop filter (BSF) is cascaded with a broadband PA, thus a notched band can be obtained in the wide operating band, realizing a dual-band characteristic of the PA. The simplified real frequency technique (SRFT) is employed to derive a broadband input matching networks covering the requisite frequency band. Appropriate fundamental impedance and second harmonic impedance matching are achieved at the ideal region of the Smith chart. For validation, an experimental prototype is fabricated and tested using a commercial GaN transistor Cree’s CGH40010F. The proposed dual-band PA is operated at 1.95–2.4 GHz and 2.65–3.1 GHz, with 61%–71% measured power-added efficiency (PAE) and 40.5–41.5 dBm of measured output power.

The design, fabrication, and testing of a conformal Frequency Selective Rasorber (FSR) operating at A-T-A mode is designed for RADAR warfare systems. In the design of a miniaturized single-layer FSR element, multiple parameters influencing the absorption and transmission characteristics need to be optimized. This simulation using conventional methods consumes more simulation time. Thus, the geometrical parameters are optimized and predicted using supervised machine learning (ML) techniques to expedite the process. The multiple output regression neural network (MORNN) is used to generate multiple input and output features from the dataset. The ML algorithm is trained using the datasets generated from the electromagnetic solver using which a scalable FSR is synthesized. The reflection coefficient, (|S₁₁|), and transmission coefficient (|S₂₁|) are used as input data, and the dimension of the FSR unit cell for the user input frequency requirements are derived as output data. The extracted dimensions of the FSR offered a small mean square error (MSE) of 0.02 between the desired and observed results. The designed FSR offers absorption at 11.5 GHz and 18.9 GHz while the transmission window extends from 15.02 GHz to 16.09 GHz. The neural network results are endorsed using the EM simulation tool and validated by experimental measurements.

A method of designing beam-steerable patch antennas with wide stopband suppression is proposed in this article. The wide stopband suppression characteristic is realized by designing suitable parallel coupled lines and open-circuited stubs. The beam steering characteristic is achieved by using a driven patch and two pairs of metal walls vertically placed on both sides of the driven antenna. By controlling the different states of the switching PIN diodes loaded between metal walls, the stable beam steering characteristic can be obtained over the entire operating bandwidth. An experimental antenna is designed and manufactured to validate the approach. The beam steering angles of the simulation and measurement results are ±30°. Moreover, in the three proposed operating states, the out-of-band suppression from 2.6 GHz to 10 GHz is more than 16 dB. The proposed antenna can achieve the characteristic of both wide stopband suppression and beam steering. In addition, the proposed antenna is able to maintain good impedance characteristics during beam steering and maintain stable beam over the entire operating bandwidth.

A novel on-chip bandpass filter (BPF) design with controllable transmission zeros (TZs) for high out-of-band rejection is proposed using the hybrid coupling technique. The proposed hybrid coupling filter consists of two symmetrical hybrid coupling spiral structures where the mutual electric and magnetic couplings are introduced to generate two TZs in the high frequency band. The center frequency, bandwidth, and transmission zero position of the proposed filter can be well controlled. To illustrate the principle of this configuration, an equivalent circuit with odd- and even-mode analysis is discussed. Moreover, another transmission zero in the low frequency band can be further generated by loading a quasi-distribution structure. The proposed hybrid coupling filter is fabricated using commercial high resistance silicon technology. The measured results show that the proposed filter can achieve a 3 dB bandwidth from 1.85 to 2.33 GHz, which indicates a fractional bandwidth of about 26 %. In addition, more than 40 dB of suppression is achieved from 3.15 to 5.55 GHz. A return loss of 29 dB and a minimum insertion loss of 2.5 dB are achieved at the center frequency with a minimized size 1.6 mm × 0.8 mm. The simulated and measured results are in good agreement.