Aeu-International Journal of Electronics and Communications最新文献_第7页

Research on joint optimization of rate and energy harvesting in STAR-RIS-empowered SWIPT system 基于star - ris的SWIPT系统速率与能量收集联合优化研究

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-12-02 DOI: 10.1016/j.aeue.2025.156165

Xiaojuan Bai, Caixia Liang, Tianxiang Liu, Ao Gao

In this paper, we investigate a simultaneously transmitting and reflecting reconfigurable intelligent surface (STAR-RIS)-assisted downlink multi-user (MU) simultaneous wireless information and power transfer (SWIPT) system to overcome the performance limitations of SWIPT system caused by environmental factors and the deployment constraints of traditional RIS. We adopt a practical non-linear energy harvesting (EH) model and design a resource allocation algorithm for SWIPT systems. By applying the energy splitting (ES) protocol of STAR-RIS, we aim to improve both the transmission rate and EH. Therefore, we formulate a multi-objective optimization problem (MOOP) to simultaneously maximize both the weighted sum rate and EH, by jointly optimizing the base station (BS) beamforming, STAR-RIS coefficient matrices, and power splitting (PS) ratio. To address the non-convexity and variable coupling, an efficient alternating optimization (AO) algorithm integrating fractional programming (FP) and semidefinite relaxation (SDR) is proposed, which decomposes the original problem into three tractable subproblems solved iteratively. Simulation results indicate favorable convergence behavior of the proposed algorithm and achieve substantial performance gains facilitated by the STAR-RIS. The proposed scheme outperforms benchmark schemes in both sum rate and EH, thereby providing theoretical support for the design of future energy-efficient communication networks.

本文研究了一种同时发射和反射可重构智能表面（STAR-RIS）辅助下行多用户（MU）同步无线信息和电力传输（SWIPT）系统，以克服环境因素和传统RIS部署约束对SWIPT系统性能的限制。采用一种实用的非线性能量收集模型，设计了一种用于SWIPT系统的资源分配算法。采用STAR-RIS的能量分裂（ES）协议，旨在提高传输速率和EH。因此，我们通过联合优化基站（BS）波束形成、STAR-RIS系数矩阵和功率分割（PS）比，制定了同时最大化加权和速率和EH的多目标优化问题（MOOP）。为了解决非凸性和变量耦合问题，提出了一种结合分数规划和半定松弛的交替优化算法，将原问题分解为三个可处理的子问题，迭代求解。仿真结果表明，该算法具有良好的收敛性能，并在STAR-RIS的推动下实现了显著的性能提升。该方案在和速率和EH方面均优于基准方案，为未来节能通信网络的设计提供理论支持。

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引用次数: 0

Design and optimization of a 1–7.8 GHz wideband low noise amplifier with 2 dB noise figure 噪声系数为2 dB的1-7.8 GHz宽带低噪声放大器的设计与优化

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-12-02 DOI: 10.1016/j.aeue.2025.156163

Muhammad Hashim, Zhiqun Li, Qin Li, Weiwen Lin

An ultra-wideband balun low-noise amplifier (LNA) operating from 1 to 7.8 GHz is proposed for multi-standard wireless applications. The architecture integrates a g_m-boosted common-source (CS) amplifier with a common-gate common-source (CG–CS) balun to enable single-to-differential signal conversion. A complementary nMOS-pMOS configuration is employed to enhance transconductance, reduce noise, and improve gain. A cross-coupled balancing circuit (CBC) is incorporated in the load to provide noise cancellation along with gain and phase correction. Wideband input matching is achieved through the combination of a resistive feedback buffer (RFB) and a series on-chip inductor L_g. Theoretical analysis, closed-form expressions, and simulation results demonstrate that the CBC improves the noise figure (NF), while the RFB and L_g enable effective input impedance matching. The LNA was fabricated using the TSMC 40-nm CMOS process, and measured results show a gain of 18.5 dB and an NF ranging from 2 to 3 dB. Additional performance metrics include an input 1-dB compression point (IP1dB) of −17 dBm, an input third-order intercept point (IIP3) of −1 dBm at 4 GHz, and S₁₁ less than −10 dB across the 1–7.8 GHz band. The design consumes 12 mA from a 1.2 V supply and occupies an active chip area of 0.16 mm².

提出了一种工作频率为1 ~ 7.8 GHz的超宽带平衡低噪声放大器（LNA），用于多标准无线应用。该架构集成了一个通用升压共源（CS）放大器和一个共门共源（CG-CS）平衡器，以实现单差分信号转换。采用互补的nMOS-pMOS结构来增强跨导性、降低噪声和提高增益。交叉耦合平衡电路（CBC）集成在负载中，以提供噪声消除以及增益和相位校正。宽带输入匹配是通过电阻反馈缓冲器（RFB）和串联片上电感器Lg的组合实现的。理论分析、封闭表达式和仿真结果表明，CBC提高了噪声系数（NF），而RFB和Lg实现了有效的输入阻抗匹配。LNA采用台积电40纳米CMOS工艺制作，测量结果显示增益为18.5 dB， NF范围为2 ~ 3 dB。其他性能指标包括输入1-dB压缩点（IP1dB）为- 17 dBm，输入三阶截距点（IIP3）为- 1 dBm， 1- 7.8 GHz频段的S11小于- 10 dB。该设计从1.2 V电源消耗12 mA，占用0.16 mm2的有源芯片面积。

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引用次数: 0

A multi-harmonic class-D FSK power and data transmitter with enhanced load power delivery and high data rate to carrier frequency ratio for biomedical implants 一种用于生物医学植入物的多谐波d类FSK功率和数据传输器，具有增强的负载功率传输和高数据速率与载频比

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-12-02 DOI: 10.1016/j.aeue.2025.156161

Akbar Asgharzadeh Bonab , Khashayar Dehghan , Jalil Mazloum

This paper presents a novel wireless power transfer and data telemetry circuit for biomedical implants that enhances both data rate and power delivery to the load. The proposed system employs a multi-coil, single-carrier frequency shift keying (FSK) transmitter architecture, where power and data are simultaneously transmitted via three magnetically coupled resonant links. These links are excited by a class-D amplifier operating at the first, third, and ninth harmonics of a base frequency. Bit encoding is performed by switching between two resonant modes: when the data bit is “0,” the system transmits at the base frequency f₀; when the bit is “1,” it switches to 3f₀. This design leverages first, third, and ninth harmonic resonance to improve power delivered to the load and simplify modulation circuitry. The system has an ability to achieve a data rate equal to f₀, resulting in a data-rate-to-f₀ ratio of 100 %. A proof-of-concept prototype was implemented on a printed circuit board and evaluated at operating frequencies of 298 kHz and 894 kHz. The transmitter delivers 1.1 W to the load with a power transfer efficiency of approximately 42 %, achieving a data rate of 0.298 Mbps and a bit error rate (BER)

5.33 \times 10^{- 6}

.

本文提出了一种新型的无线电力传输和数据遥测电路，用于生物医学植入物，提高了数据速率和向负载的电力输送。所提出的系统采用多线圈、单载波频移键控（FSK）发射机架构，其中功率和数据通过三个磁耦合谐振链路同时传输。这些链路由工作在基频的一、三、九次谐波上的d类放大器激发。位编码通过在两种谐振模式之间切换来实现：当数据位为“0”时，系统以基频f0传输；当位为“1”时，它切换到3f0。该设计利用一、三、九次谐波共振来改善向负载传递的功率，并简化调制电路。该系统能够实现等于f0的数据速率，从而使数据速率与f0的比率达到100%。在印刷电路板上实现了概念验证原型，并在298 kHz和894 kHz的工作频率下进行了评估。发射器向负载输出1.1 W功率，功率传输效率约为42%，数据速率为0.298 Mbps，误码率（BER） 5.33×10-6。

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引用次数: 0

A real-time FPGA-based hardware module for adaptive noise correction in cardiac bioelectronic systems: Toward robust signal conditioning for implantable biosensors 心脏生物电子系统中用于自适应噪声校正的实时fpga硬件模块：面向植入式生物传感器的鲁棒信号调理

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-12-02 DOI: 10.1016/j.aeue.2025.156162

Milad Ghanbarpour , Muhammad Akmal Chaudhary , Maher Assaad , Gilda Ghanbarpour

Cardiovascular diseases are a leading cause of mortality worldwide. Recent efforts focus on hardware-based emulation of cardiac pacemaker cells using differential equation models for the electrophysiological activity of sinoatrial (SA) and Purkinje Fiber (PF) cells. While these models provide high signal fidelity, they assume ideal, noise-free conditions, ignoring the inevitable presence of noise in biological and digital biosensor systems, including implantable bioelectronic platforms. This study presents a hardware module for real-time noise correction in cardiac biosignals, designed for processing data from various sources by identifying disturbances and applying corrective algorithms. It examines noise correction using two filtering algorithms: Least Mean Squares (LMS) and Unscented Kalman Filter (UKF), highlighting the specific advantages and applications of each. Additionally, the impact of several optimization techniques on the results of the hardware implementation, including accuracy, power consumption, resource usage, and frequency, is analyzed. This work can serve as an initial step toward integrating adaptive noise correction methods into future implantable or diagnostic cardiac biosensing systems, enhancing the robustness and reliability of next-generation bioelectronic interfaces.

心血管疾病是世界范围内导致死亡的主要原因。最近的研究主要集中在基于硬件的心脏起搏器细胞的模拟上，使用微分方程模型来模拟窦房细胞（SA）和浦肯野纤维细胞（PF）的电生理活动。虽然这些模型提供了高信号保真度，但它们假设理想的无噪声条件，忽略了生物和数字生物传感器系统（包括植入式生物电子平台）中不可避免的噪声存在。本研究提出了一个用于心脏生物信号实时噪声校正的硬件模块，旨在通过识别干扰和应用校正算法来处理来自各种来源的数据。它研究了使用两种滤波算法的噪声校正：最小均方（LMS）和无气味卡尔曼滤波（UKF），突出了每种算法的具体优势和应用。此外，还分析了几种优化技术对硬件实现结果的影响，包括准确性、功耗、资源使用和频率。这项工作可以作为将自适应噪声校正方法集成到未来植入式或诊断性心脏生物传感系统的第一步，增强下一代生物电子接口的鲁棒性和可靠性。

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引用次数: 0

A low-cost dual-band metasurface-based circularly polarized patch antenna with enhanced gain 一种低成本、增益增强的双频超表面圆极化贴片天线

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-11-29 DOI: 10.1016/j.aeue.2025.156159

Deepak Ram, Amit Kumar Singh, Somak Bhattacharyya

This article presents a compact and cost-effective metasurface-loaded microstrip antenna capable of dual-band circular polarization. The design utilizes a corner-trimmed square patch with a cross-shaped slot on an FR-4 substrate (1.6 mm thick) backed by a metallic ground. Performance enhancement is achieved using two metasurface layers: the first consists of sixteen square-ring elements in a 4 × 4 periodic array on an FR-4 sheets, and the second comprises a 4 × 4 array of square elements with hexagonal slots placed 9 mm above the first layer using an air gap. The antenna operates at two frequency bands, offering impedance bandwidths of 6.14 % (4.1–4.36 GHz) and 9.91 % (5.08–5.61 GHz). The axial ratio bandwidths are 3.22 % (4.27–4.41 GHz) and 5.1 % (5.15–5.42 GHz), confirming dual-band circular polarization. It achieves realized gains of 4.83 dBic and 5.74 dBic with efficiencies of 65 % and 61 % at 4.30 and 5.36 GHz, respectively, exhibiting left-handed CP radiation. An equivalent circuit model was developed and validated through simulations and experiments, showing strong agreement. With compact dimensions of 0.54λ₀ × 0.54λ₀ × 0.023λ₀ at 4.30 GHz, the antenna is well-suited for 5G and satellite communication applications.

本文提出了一种结构紧凑、性价比高的双频圆极化超表面负载微带天线。该设计在FR-4基板（1.6 mm厚）上采用带有十字槽的边角方形贴片，背面为金属地面。性能增强是通过使用两个超表面层来实现的：第一个层由16个4 × 4周期阵列的方形环元素组成，在FR-4薄片上，第二个层由4 × 4方形元素阵列组成，其六角形槽放置在第一层上方9毫米处，使用气隙。该天线工作在两个频段，提供6.14% （4.1-4.36 GHz）和9.91% （5.08-5.61 GHz）的阻抗带宽。轴比带宽分别为3.22% （4.27 ~ 4.41 GHz）和5.1% (5.15 ~ 5.42 GHz)，证实了双频圆极化。在4.30 GHz和5.36 GHz频段，实现了4.83 dBic和5.74 dBic的增益，效率分别为65%和61%，表现出左旋CP辐射。建立了等效电路模型，并通过仿真和实验验证了等效电路模型的正确性。该天线尺寸紧凑，在4.30 GHz时为0.54λ0 × 0.54λ0 × 0.023λ0，非常适合5G和卫星通信应用。

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引用次数: 0

A 4T1C Cryogenic Inverse CMOS Memristor Emulator For Quantum Computing Application 用于量子计算的4T1C低温逆CMOS忆阻器仿真器

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-11-29 DOI: 10.1016/j.aeue.2025.156157

Sara Paul, R.K. Kavitha

In this manuscript, a 4T1C cryogenic inverse memristor emulator is proposed which operates at a maximum frequency of 100 MHz. It is able to operate from room temperature (RT) to mid-cryogenic temperature (77 K to 20 K) without much design efforts. The proposed design is implemented in UMC 65 nm technology and analyzed at various frequency and voltage levels, both at RT and cryogenic temperatures. The power consumption of 4T1C inverse memristor emulator is

47 μ

W,

55 μ

W and

75 μ

W at 20 K, 77 K and RT respectively. It exhibits a 48% reduction in power consumption at 20 K and a 34% reduction at 77 K, when compared to RT. The proposed design occupies the least area of

74 μ

m

^{2}

which is 3 to 5 times lesser than other CMOS inverse emulators. Process corner and Monte-carlo simulations are performed to validate the stability and robustness. The potential practical applications are analyzed by implementing both analog and digital circuits. The analog circuits being explored through RC filters and Schmitt triggers, while the digital circuits are analyzed by memristor based NOT and NOR gates. Hence, the proposed inverse memristor emulator circuit offers a low frequency as well as high frequency applications in both room and Cryogenic temperature with least area and power consumption.

在本文中，提出了一种4T1C低温逆忆阻器仿真器，其最大工作频率为100 MHz。它能够从室温（RT）到中低温（77 K至20 K），无需太多的设计工作。所提出的设计在UMC 65nm技术中实现，并在RT和低温下的不同频率和电压水平下进行了分析。4T1C逆忆阻仿真器在20 K、77 K和RT下的功耗分别为47μW、55μW和75μW。与rt相比，它在20k时功耗降低48%，在77k时功耗降低34%。所提出的设计占用的最小面积为74μm2，比其他CMOS逆仿真器小3至5倍。通过过程角和蒙特卡罗仿真验证了算法的稳定性和鲁棒性。通过实现模拟电路和数字电路，分析了其潜在的实际应用。模拟电路通过RC滤波器和施密特触发器进行探索，而数字电路则通过基于非门和NOR门的忆阻器进行分析。因此，所提出的逆忆阻器仿真电路在室温和低温下都能提供低频和高频应用，且面积和功耗最小。

{"title":"A 4T1C Cryogenic Inverse CMOS Memristor Emulator For Quantum Computing Application","authors":"Sara Paul, R.K. Kavitha","doi":"10.1016/j.aeue.2025.156157","DOIUrl":"10.1016/j.aeue.2025.156157","url":null,"abstract":"<div><div>In this manuscript, a 4T1C cryogenic inverse memristor emulator is proposed which operates at a maximum frequency of 100 MHz. It is able to operate from room temperature (RT) to mid-cryogenic temperature (77 K to 20 K) without much design efforts. The proposed design is implemented in UMC 65 nm technology and analyzed at various frequency and voltage levels, both at RT and cryogenic temperatures. The power consumption of 4T1C inverse memristor emulator is <span><math><mrow><mn>47</mn><mspace></mspace><mi>μ</mi></mrow></math></span>W, <span><math><mrow><mn>55</mn><mspace></mspace><mi>μ</mi></mrow></math></span>W and <span><math><mrow><mn>75</mn><mspace></mspace><mi>μ</mi></mrow></math></span>W at 20 K, 77 K and RT respectively. It exhibits a 48% reduction in power consumption at 20 K and a 34% reduction at 77 K, when compared to RT. The proposed design occupies the least area of <span><math><mrow><mn>74</mn><mspace></mspace><mi>μ</mi></mrow></math></span>m<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> which is 3 to 5 times lesser than other CMOS inverse emulators. Process corner and Monte-carlo simulations are performed to validate the stability and robustness. The potential practical applications are analyzed by implementing both analog and digital circuits. The analog circuits being explored through RC filters and Schmitt triggers, while the digital circuits are analyzed by memristor based NOT and NOR gates. Hence, the proposed inverse memristor emulator circuit offers a low frequency as well as high frequency applications in both room and Cryogenic temperature with least area and power consumption.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156157"},"PeriodicalIF":3.2,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transmission-gate based Phase Frequency Detector and 0.33% current mismatch MOS charge pump for reference spur reduction in 2.5 GHz PLL 基于传输门的相位频率检测器和0.33%电流失配的MOS电荷泵用于2.5 GHz锁相环的参考杂散抑制

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-11-27 DOI: 10.1016/j.aeue.2025.156156

Sriparna Sarma, Tshering Sangmoo Sherpa, Sanjay Kumar Jana

This paper proposes high-performance, low-power Phase-Locked Loop (PLL) architecture designed using transmission-gate-based Phase Frequency Detector (PFD) and 12-transistor-based MOS Charge Pump (CP) implemented using the SCL 180 nm CMOS process and simulated in Cadence Virtuoso environment. The proposed PFD eliminate blind zones and reduces dead zone to 4 ps through direct reset mechanism, operating over 1–6.5 GHz frequency range using only eight transistors, resulting in a low power consumption of 171.2

μ

W and phase noise of –156.4 dBc/Hz at 1 MHz offset. The proposed CP achieves minimal current mismatch of 0.33 % while consuming 181.8

μ

W. The proposed PFD-CP is integrated with a conventional loop filter, voltage-controlled oscillator and frequency divider to design a 2.5 GHz PLL, which achieves lock time below 20 ns and spur-to-floor delta of 72.07 dB. The compact core area of 0.0014 mm

^{2}

and power consumption of 338.8

μ

W are achieved. It demonstrates that approximately 80%–85% smaller area and 75%–90% lower power consumption compared to recent state-of-the-art, along with 10 dB improvement in spur suppression and two-times faster locking response, highlighting its efficiency and scalability for high-speed, low-spur, low-jitter Serializer–Deserializer (SERDES) and clock recovery systems. The Monte Carlo simulation and Process, Voltage, Temperature (PVT) analyses confirm robust performance of the design.

本文提出了基于传输门的相频检测器（PFD）和基于12晶体管的MOS电荷泵（CP）的高性能、低功耗锁相环（PLL）架构，采用SCL 180 nm CMOS工艺实现，并在Cadence Virtuoso环境中进行了仿真。该PFD通过直接复位机制消除盲区，并将死区降低至4ps，工作频率在1 - 6.5 GHz范围内，仅使用8个晶体管，功耗低至171.2 μ W，相位噪声为-156.4 dBc/Hz。该电路在功耗181.8 μ w的情况下实现了0.33%的最小电流失配。该电路集成了传统环路滤波器、压控振荡器和分频器，设计了一个2.5 GHz锁相环，锁相锁时间低于20 ns，杂散-底差为72.07 dB。实现了紧凑的核心面积为0.0014 mm2，功耗为338.8 μ W。与最新技术相比，它的面积缩小了约80%-85%，功耗降低了75%-90%，同时杂散抑制性能提高了10 dB，锁定响应速度提高了两倍，突出了其在高速、低杂散、低抖动串行反序列化器（SERDES）和时钟恢复系统中的效率和可扩展性。蒙特卡罗仿真和过程、电压、温度（PVT）分析证实了该设计的鲁棒性。

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引用次数: 0

Design of a dual-band co-polarized in-band full-duplex antenna with broadside radiation 一种带宽侧辐射的双频共极化带内全双工天线的设计

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-11-27 DOI: 10.1016/j.aeue.2025.156160

Sandeep Rana , Amit Kumar , Gunjan Srivastava , Akhilesh Mohan

This paper presents a co-linearly polarized shared radiator-based dual-band in-band full duplex antenna. The proposed design integrates the transmitter (Tx) and receiver (Rx) ports into a single microstrip patch antenna (MPA) incorporating shorting vias along its central plane to enable half-mode propagation. The TM_1/2,0 and TM_1/2,1 modes are exploited to realize dual-band operation with broadside radiation in both bands. The capacitive coupling, assisted by auxiliary feeding strips, provides a wide impedance bandwidth. Additionally, to increase the impedance bandwidth of the higher operating band, a half-wavelength slot is etched out from the MPA. Finally, to enhance the inter-port isolation, two judiciously designed square-shaped stubs are attached to the MPA. Furthermore, a prototype is fabricated to validate the proposed concept. The measured results indicate that the proposed design exhibits fractional impedance bandwidths (|S₁₁|, |S₂₂| ≤ −10 dB) of 5 % (2.54–2.67 GHz) and 9.3 % (3.88–4.26 GHz), with inter-port isolations exceeding 23 dB and 17 dB in the lower and higher operating bands, respectively. Due to its significant features in terms of impedance bandwidth and inter-port isolation, the proposed design can be employed for applications in the 5G n41 and n77 bands.

提出了一种基于共线极化共用辐射器的双频带内全双工天线。提出的设计将发射器（Tx）和接收器（Rx）端口集成到单个微带贴片天线（MPA）中，并在其中心平面上采用短通孔，以实现半模式传播。利用TM1/2,0和TM1/2,1模式实现双频工作，两波段均有宽侧辐射。在辅助馈电带的辅助下，电容耦合提供了宽的阻抗带宽。此外，为了增加较高工作频带的阻抗带宽，在MPA上刻蚀出半波长槽。最后，为了增强端口间的隔离，MPA上附加了两个精心设计的方形存根。此外，还制作了一个原型来验证所提出的概念。测量结果表明，所提出的设计具有5% （2.54 ~ 2.67 GHz）和9.3% （3.88 ~ 4.26 GHz）的分数阻抗带宽（|S11|、|S22|≤- 10 dB），在低频段和高频段的端口间隔离度分别超过23 dB和17 dB。由于其在阻抗带宽和端口间隔离方面的显著特性，所提出的设计可用于5G n41和n77频段的应用。

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引用次数: 0

A parallel Class-E power amplifier with doubly-tuned transformer-based load network and high-efficiency cascode in 110-nm CMOS 基于双调谐变压器负载网络和110纳米CMOS高效级联码的并联e类功率放大器

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-11-26 DOI: 10.1016/j.aeue.2025.156117

Kai Yue, Zemeng Huang, Yubing Li, Yujia Chen, Tao Tan, Tao He, Yu Wang, Peng Ke, Xiuping Li

This article presents a doubly tuned (DT) transformer-based parallel Class-E power amplifier (PA). A compact parallel Class-E load network consisting of only one DT transformer and a pair of capacitors is proposed to enhance output power and efficiency. Compared with the traditional DT transformer-based series Class-E load, the proposed DT transformer-based parallel Class-E load can further mitigate the constraints placed on device size and reduce the impedance transformation ratio of the load. Besides, a cascode structure with neutralization and charging acceleration capacitor (

C_{X}

) is used as active core to enhance gain and efficiency. The gain and stability of the active core are quantitatively analyzed based on the transistor small-signal model, and it can be concluded that the gain of the active core exhibits an increasing trend with the growth of

C_{X}

while ensuring stability. As a proof of the design, a 12 GHz Class-E PA is fabricated using 110-nm CMOS process. The measurement results show that the proposed PA realizes a peak power-added-efficiency (PAE) of 30.9%, a maximum saturated output power (P

_{sat}

) of 18.2 dBm and a peak gain of 19.0 dB. The core area of the circuit is only 990

μ

m

\times 260 μ

m.

本文提出了一种基于双调谐（DT）变压器的并联e类功率放大器。为了提高输出功率和效率，提出了一种由一个DT变压器和一对电容器组成的紧凑并联e类负载网络。与传统的基于DT变压器的串联e类负载相比，本文提出的基于DT变压器的并联e类负载可以进一步减轻对器件尺寸的限制，降低负载的阻抗变化率。此外，采用具有中和和充电加速电容（CX）的级联结构作为有源磁芯，提高了增益和效率。基于晶体管小信号模型对有源铁芯的增益和稳定性进行了定量分析，得出有源铁芯的增益在保证稳定性的前提下，随着CX的增长呈增加趋势。为了验证该设计，采用110纳米CMOS工艺制造了一个12 GHz的e级PA。测量结果表明，该放大器的峰值功率增加效率（PAE）为30.9%，最大饱和输出功率（Psat）为18.2 dBm，峰值增益为19.0 dB。电路的核心面积仅为990 μm ×260μm。

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引用次数: 0

A low loss tri-band negative group delay circuit with resistors 带电阻的低损耗三带负群延迟电路

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2025-11-25 DOI: 10.1016/j.aeue.2025.156144

Yuwei Meng, Zhenping Lan

A low loss tri-band negative group delay circuit (NGDC) with resistors is proposed. The proposed NGDC consists of two open-circuited coupled lines connected with two parallel branches and a matching network. The working frequencies can be designed through changing the characteristic impedance of the transmission lines. And the negative group delay (NGD) time is tuned by adjusting the values of the resistors in the parallel branches. To verify the design concept, a tri-band NGDC is simulated, fabricated and measured. The NGD times are –0.80 ns, –1.04 ns, and –0.97 ns at three NGD central frequencies with insertion losses of 11.7 dB, 13.7 dB, and 11.2 dB, respectively. Meanwhile, the input/output return loss is better than 15.8 dB in the three NGD bands along with the variation of insertion loss is less than 2 dB.

提出了一种带电阻的低损耗三带负群延迟电路（NGDC）。所提出的NGDC由两条开路耦合线路和两条平行支路相连的匹配网络组成。通过改变传输线的特性阻抗来设计工作频率。并通过调整并联支路电阻的值来调节负群延时（NGD）。为了验证设计理念，对三波段NGDC进行了仿真、制作和测量。在三个NGD中心频率下，NGD时间分别为-0.80、-1.04和-0.97 ns，插入损失分别为11.7 dB、13.7 dB和11.2 dB。同时，三个NGD频段的输入/输出回波损耗均优于15.8 dB，插入损耗变化小于2 dB。

引用次数: 0