Aeu-International Journal of Electronics and Communications最新文献_第4页

Design and optimization of a low-power dynamic MCML-based phase-frequency detector using Taguchi DoE and ANOVA for frequency synthesizers with fast-locking of 0.5 μs 基于田口DoE和方差分析的低功耗动态mcml相频检测器的设计与优化，频率合成器的快速锁定为0.5 μs

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-17 DOI: 10.1016/j.aeue.2026.156214

Dheeraj Singh Rajput , Bharat Choudhary , Archana Singhal , Dharmendar Boolchandani

This paper introduces a novel Phase Frequency Detector (PFD) based on Dynamic MOS Current Mode Logic (DyCML), designed for low-power, high-speed frequency synthesizers. The proposed PFD eliminates the need for a reset path, thereby removing dead and blind zones and improving output linearity across a full phase range from –π to π. The DyCML approach offers inherent advantages such as low static power dissipation, high-speed switching, and enhanced noise immunity through differential, current-mode operation. Design parameters were optimized using Taguchi Design of Experiments (DoE) and Analysis of Variance (ANOVA) techniques to achieve optimal performance. The optimized PFD achieves a phase noise of –159.41 dBc/Hz, power consumption of 5.822 μW, maximum operating frequency of 6.91 GHz, and a delay of 42.76 ps. The layout area is 793.27 μm², and the design attains a figure-of-merit of –168.55 dBc/Hz. Robustness is validated through Process-Voltage-Temperature and Monte Carlo analysis, showing close agreement between post-layout and pre-layout results. Integrated into a PLL frequency synthesizer, the PFD achieves a lock time of 500 ns at output frequency 3.8 GHz, with low jitter and minimal reference spur. The design is implemented in Cadence Virtuoso using a 0.18 μm SCL CMOS process at a 1.8 V supply.

本文介绍了一种基于动态MOS电流模式逻辑（DyCML）的新型相位频率检测器（PFD），该检测器专为低功耗、高速频率合成器而设计。所提出的PFD消除了重置路径的需要，从而消除了死区和盲区，并改善了从-π到π的整个相位范围内的输出线性度。DyCML方法具有固有的优点，如低静态功耗、高速开关和通过差分、电流模式操作增强的抗噪性。采用田口试验设计（DoE）和方差分析（ANOVA）技术对设计参数进行优化。优化后的PFD相位噪声为-159.41 dBc/Hz，功耗为5.822 μW，最大工作频率为6.91 GHz，延迟为42.76 ps，布局面积为793.27 μm2，性能因数为-168.55 dBc/Hz。通过过程电压温度和蒙特卡罗分析验证了鲁棒性，显示布局后和布局前的结果非常一致。PFD集成到锁相环频率合成器中，在3.8 GHz的输出频率下实现500 ns的锁定时间，具有低抖动和最小的参考杂散。该设计在Cadence Virtuoso中使用1.8 V电源下的0.18 μm SCL CMOS工艺实现。

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引用次数: 0

A high-aperture-efficiency circularly polarized folded transmitarray with ultra-low profile and low design complexity 一种低轮廓、低设计复杂度、高孔径效率的圆极化折叠发射阵列

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-02-07 DOI: 10.1016/j.aeue.2026.156247

Xin-Zhi Bo , Bo-Wen Yuan , Zhen-Guo Liu , Meng-Zi Li , Ming Shen

An ultra-low-profile, low-complexity, circularly polarized folded transmitarray (CPFTA) with high aperture efficiency is proposed. The antenna comprises a bottom metal plate and a top multifunctional metasurface (MFM). A left-hand circularly polarized (LHCP) source is centered on the bottom plate. The top metasurface is constructed with subwavelength spiral microstrip lines in a receiver-transmitter (Rx-Tx) configuration. Anomalous reflection is achieved by tailoring the reflection phase distribution of the top-layer metasurface, thereby constraining the profile height to H = F/4. Ultimately, the antenna's H/D ratio is merely 0.144. Measurements confirm the simulated performance of the proposed FTA, with good agreement observed across the operating band. The measured peak gain values reach 25.5 dBic at 15.1 GHz, corresponding to an aperture efficiency of 43.5%. The proposed CP-FTA achieves an ultra-low profile and high aperture efficiency simultaneously, while maintaining low design complexity and enabling planar integration.

提出了一种超低轮廓、低复杂度、高孔径效率的圆极化折叠发射阵列（CPFTA）。天线包括底部金属板和顶部多功能超表面（MFM）。左圆偏振（LHCP）光源位于底板中心。顶部超表面由接收-发射（Rx-Tx）配置的亚波长螺旋微带线构成。通过调整顶层超表面的反射相位分布来实现异常反射，从而将剖面高度限制在H = F/4。最终，天线的H/D比仅为0.144。测量证实了所提出的FTA的模拟性能，在整个操作波段观察到良好的一致性。在15.1 GHz时，测量到的峰值增益达到25.5 dBic，对应的孔径效率为43.5%。所提出的CP-FTA同时实现了超低轮廓和高孔径效率，同时保持了低设计复杂性和平面集成能力。

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引用次数: 0

A high-efficiency CMOS rectifier with wide dynamic range based on dual dynamic gate-biasing and body self-biasing techniques 基于双动态栅极偏置和本体自偏置技术的高效宽动态范围CMOS整流器

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-28 DOI: 10.1016/j.aeue.2026.156225

Ang Li, Jian Liu, Chen Wang, Di Luo, Rui Wang, Kang Zeng

This paper presents an efficient CMOS rectifier with a wide PDR for radio-frequency energy harvesting (RFEH) applications. The proposed circuit employs a dual dynamic gate-biasing technique to enhance the forward current at low input power levels while suppress the reversed leakage current at high input power levels. Thus, the rectifier’s PDR can be extended. In addition, a body self-biasing technique is developed to reduce the rectifying transistors’ threshold voltage during conduction, which further improves the sensitivity and expands the PDR. For validation, a 200 MHz CMOS rectifier is designed in a 40 nm CMOS process. The rectifier occupies a

69 μ m

×

93 μ m

chip area. The post-simulation results show that the proposed rectifier achieves a 87.5% peak PCE, a -19.4 dBm sensitivity and a 25.2 dB PDR (for PCE

>

40%) with a 100 k

Ω

load.

本文提出了一种适用于射频能量采集（RFEH）应用的具有宽PDR的高效CMOS整流器。该电路采用双动态门偏置技术，在低输入功率时增强正向电流，在高输入功率时抑制反向漏电流。因此，整流器的PDR可以延长。此外，为了降低整流晶体管导通时的阈值电压，提出了一种体自偏置技术，进一步提高了整流晶体管的灵敏度，扩大了PDR。为了验证，在40 nm CMOS工艺中设计了200 MHz CMOS整流器。整流器的芯片面积为69μm × 93μm。后仿真结果表明，该整流器在100 kΩ负载下的峰值PCE为87.5%，灵敏度为-19.4 dBm， PDR为25.2 dB （PCE>40%）。

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引用次数: 0

A wideband endfire 9-port Vivaldi-based MIMO antenna for X-band standardized satellite applications 用于x波段标准化卫星应用的宽带端射9端口vivaldi MIMO天线

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-30 DOI: 10.1016/j.aeue.2026.156234

Rupam Bharati , Anvesh Pandey , Arun Kumar Saurabh , Manoj Kumar Meshram

This paper presents a compact wideband 9-port MIMO antenna designed for X-band standardized satellite communication systems. The proposed configuration employs nine identical Vivaldi elements arranged in a uniform endfire orientation with a shared radiating aperture on a rectangular substrate occupying an electrical area of 1.59λ₀ × 5.3λ₀ (λ₀ calculated at 6.5 GHz). Each Vivaldi element comprises a tapered microstrip feed line, a microstrip-to-slit-line transition, an exponentially tapered radiating aperture, and an oval-shaped parasitic director. A tightly integrated layout is achieved by maintaining an edge-to-edge spacing of only 0.05λ₀ between adjacent elements. The antenna exhibits measured reflection coefficients (|S_ii| < −10 dB) and inter-element isolation (|S_ij| ∈ i ≠ j < −24 dB) over 6.5–12.2 GHz, fully encompassing the standardized X-band uplink (7.9–8.4 GHz) and downlink (7.25–7.75 GHz) frequency allocations. The radiation characteristics remain highly directive and stable across the operating band, yielding peak gain and peak total efficiency of 6.6 dBi and 77.1% for elements 5, respectively. Measured results show excellent agreement with simulations. Comprehensive evaluation of both conventional and diversity metrics confirms robust wideband MIMO performance, highlighting the antenna's suitability for high-gain directional links in satellite communication, remote sensing, and Satcom-on-the-Move (SOTM) platforms.

本文设计了一种用于x波段标准化卫星通信系统的小型宽带9口MIMO天线。所提出的结构采用9个相同的Vivaldi元件，排列在均匀的端射方向上，在矩形衬底上具有共享的辐射孔径，占据1.59λ0 × 5.3λ0 （λ0在6.5 GHz下计算）的电面积。每个Vivaldi元件包括一个锥形微带馈线、一个微带到狭缝线的过渡、一个指数锥形辐射孔径和一个椭圆形寄生导向器。紧密集成的布局是通过保持相邻元素之间的边到边间距仅为0.05λ0来实现的。该天线在6.5-12.2 GHz范围内具有实测反射系数（|Sii| <−10 dB）和元件间隔离度（|Sij|∈i≠j <−24 dB），完全涵盖了标准化的x波段上行（7.9-8.4 GHz）和下行（7.25-7.75 GHz）频率分配。辐射特性在整个工作波段保持高度的指导性和稳定性，元素5的峰值增益和峰值总效率分别为6.6 dBi和77.1%。实测结果与模拟结果吻合良好。对传统和分集指标的综合评估确认了宽带MIMO的强大性能，突出了天线在卫星通信、遥感和移动卫星通信（SOTM）平台中的高增益定向链路的适用性。

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引用次数: 0

A compact memristor emulator for energy efficient neuron application 一个紧凑的忆阻器仿真器，用于节能神经元的应用

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-02-16 DOI: 10.1016/j.aeue.2026.156260

Arun Kalakola , Basit Shafat Makhdoomi , Rahul Ranjan , Rajeev Kumar Ranjan , Shahram Minaei

This article presents a memristor emulator circuit, the first to employ only a single MOSFET and a single capacitor, achieving high frequency operation up to 50 MHz. The MOSFET operates in saturation with its gate and drain shorted, functioning as a current source to charge the capacitor and emulate memristive behavior. The design achieves low transient power consumption of 33

μ

W (NMOS) and 28

μ

W (PMOS) using 180 nm SCL technology in Cadence Virtuoso. Extensive analyses including frequency, transient, non-volatility performance, and process variation studies were performed and validated through pre- and post-layout simulations. Experimental verification using off-the-shelf components confirmed its practicality. As a key application, a spiking neuron circuit utilizing the emulator demonstrated biologically inspired spiking behavior, featuring a compact layout (66.16

μ

m

\times

95.11

μ

m), energy per spike of 4.07 pJ, and power consumption of 7.31

μ

W, underscoring its promise for low power neuromorphic computing.

本文提出了一个忆阻器仿真电路，第一个只使用单个MOSFET和单个电容，实现高达50 MHz的高频工作。MOSFET在饱和状态下工作，其栅极和漏极短路，作为电流源为电容器充电并模拟记忆行为。该设计在Cadence Virtuoso中采用180 nm SCL技术，实现了33 μW （NMOS）和28 μW （PMOS）的低瞬态功耗。进行了广泛的分析，包括频率、瞬态、非挥发性性能和工艺变化研究，并通过布局前后的模拟进行了验证。使用现成元件进行实验验证，证实了其实用性。作为一项关键应用，利用该仿真器的脉冲神经元电路显示了生物启发的脉冲行为，具有紧凑的布局（66.16 μm × 95.11 μm），每个脉冲能量为4.07 pJ，功耗为7.31 μW，强调了其低功耗神经形态计算的前景。

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引用次数: 0

Broadband and compact filtering power divider employing quarter circular/cambered SIW and CPW structures 宽带和紧凑型滤波功率分配器采用四分之一圆/弯曲SIW和CPW结构

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-09 DOI: 10.1016/j.aeue.2026.156196

Ke-Long Sheng, Xiang Wang, Song-Song Qian, Zhi-Yuan Zong, Huangyan Li, Boyu Sima, Wen Wu

This paper proposes a broadband and compact filtering power divider (FPD) based on quarter circular/cambered (QCC) substrate integrated waveguide (SIW) and coplanar waveguide (CPW) resonators. Firstly, the impact of the CPW slot length on the quality factor (Q) of the QCC SIW resonator is analyzed. Subsequently, the CPW resonator is integrated into the QCC SIW to form a third-order bandpass filter (BPF) with a cascaded trisection (CT) topology. A transmission zero is located in the upper stopband. Finally, two third-order hybrid QCC SIW and CPW filtering power dividers (FPDs) with and without isolation resistors are designed. Furthermore, this paper introduces a new method for rapidly determining the quantity and value of isolation resistors. All the designs presented in this paper are simulated, manufactured, and experimentally validated. The measured results indicate that the proposed third-order FPD with isolation resistors operates at a center frequency of 5.08 GHz with a 3-dB FBW of 41.3% (2.1 GHz). The insertion loss (IL) is approximately (3 + 1.1) dB. The isolation between two output ports is better than 16 dB. A transmission zero (TZ) can be observed at 6.75 GHz in the right side of the passband attributing to the cross-coupling scheme, which enhances the out-of-band selectivity. The overall size of the proposed FPD with isolation resistors is 1.71λ_g × 1.49λ_g, and it features advantages of broad operating bandwidth, compact physical size, and low insertion loss.

提出了一种基于四分之一圆/弧面（QCC）衬底集成波导（SIW）和共面波导（CPW）谐振器的宽带紧凑型滤波功率分压器（FPD）。首先，分析了CPW槽长对QCC SIW谐振器质量因子Q的影响。随后，将CPW谐振器集成到QCC SIW中，形成具有级联三分（CT）拓扑结构的三阶带通滤波器（BPF）。传输零点位于上阻带。最后，设计了两种带隔离电阻和不带隔离电阻的三阶混合QCC SIW和CPW滤波功率分压器。此外，本文还介绍了一种快速确定隔离电阻数量和值的新方法。本文提出的所有设计都经过了仿真、制造和实验验证。测量结果表明，采用隔离电阻的三阶FPD工作在5.08 GHz的中心频率，3 db FBW为41.3% （2.1 GHz）。插入损耗（IL）约为（3 + 1.1）dB。两个输出端口之间的隔离度优于16db。由于交叉耦合方案，在6.75 GHz的通带右侧可以观察到传输零（TZ），提高了带外选择性。所提出的带隔离电阻的FPD总体尺寸为1.71λg × 1.49λg，具有工作带宽宽、物理尺寸紧凑、插入损耗低等优点。

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引用次数: 0

CPW feed and stub optimization for Vivaldi antennas in broadband ground-penetrating radar applications 宽带探地雷达中维瓦尔第天线的CPW馈源和存根优化

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-15 DOI: 10.1016/j.aeue.2026.156219

Kurnia Paranita Kartika Riyanti , Eko Setijadi , Gamantyo Hendrantoro , Nurhayati

Vivaldi antennas used in Ground Penetrating Radar (GPR) systems often experience performance degradation at low frequencies due to inefficient radiation and impedance mismatch between the feedline and the tapered slot structure. To address these limitations, this paper presents a compact Vivaldi antenna employing a coplanar waveguide (CPW) feedline integrated with a single-stub matching technique. The stub position is analytically optimized to improve impedance matching over a broad frequency range. The CPW configuration simplifies the antenna structure by placing both the feedline and ground plane on the same substrate layer, resulting in a compact layout and facilitating broadband operation. The proposed antenna is fabricated on an FR-4 substrate with a thickness of

1.6 mm

and a relative permittivity of

ϵ_{r} = 4.3

, with overall dimensions of

80 \times 80 \times 1.635

{mm}^{3}

. The measured results demonstrate broadband operation from 1.13 to 5 GHz. The antenna achieves a peak gain of 10.89 dBi in simulation and 10.36 dBi in measurement at 1.9 GHz, with a measured radiation efficiency of approximately 90.16% at the resonant frequency. The corresponding simulated and measured

S_{11}

values of

- 61.21

dB and

- 39.13

dB indicate effective impedance matching at resonance, with minor discrepancies attributed to fabrication tolerances and measurement conditions. To assess practical feasibility, a preliminary sandbox-based GPR experiment was conducted using a pair of identical antennas in a bistatic configuration. The resulting A-scan response shows a distinct reflection corresponding to a buried metallic target at an estimated depth of 37.7 cm, which agrees well with the actual burial depth. These results indicate that the proposed antenna can support broadband GPR sensing within the investigated frequency range, while further system-level and field validations are recommended.

用于探地雷达（GPR）系统的维瓦尔第天线在低频时，由于馈线和锥形槽结构之间的低效率辐射和阻抗不匹配，经常会出现性能下降。为了解决这些限制，本文提出了一种紧凑的维瓦尔第天线，采用共面波导（CPW）馈线集成了单根匹配技术。短段位置经过分析优化，以改善宽频率范围内的阻抗匹配。CPW配置简化了天线结构，将馈线和地平面放置在同一基板层上，导致布局紧凑，便于宽带操作。该天线采用厚度为1.6mm，相对介电常数为ϵr=4.3的FR-4衬底，整体尺寸为80×80×1.635 mm3。测量结果表明，该系统可以在1.13 ~ 5 GHz范围内运行。该天线在1.9 GHz下的仿真峰值增益为10.89 dBi，测量峰值增益为10.36 dBi，在谐振频率下的实测辐射效率约为90.16%。相应的模拟和测量S11值分别为- 61.21 dB和- 39.13 dB，表明谐振时的有效阻抗匹配，由于制造公差和测量条件的差异较小。为了评估实际可行性，采用双基地配置的一对相同天线进行了基于沙盒的探地雷达初步实验。得到的a扫描响应显示出明显的反射，对应于估计深度为37.7 cm的埋藏金属目标，这与实际埋藏深度吻合良好。这些结果表明，所提出的天线可以在所研究的频率范围内支持宽带GPR传感，但建议进一步进行系统级和现场验证。

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引用次数: 0

Design and implementation of miniaturized DRA for five bands of GNSS GNSS五波段小型化DRA的设计与实现

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-30 DOI: 10.1016/j.aeue.2026.156240

Anup Kumar, Sushmita Bhushan, Rajveer Singh Yaduvanshi

Novelty of the proposed design lies in miniaturization of Rectangular Dielectric Resonator Antenna (RDRA). Secondly, all Global Navigation Satellite System (GNSS) five bands have been accumulated in single structure. Amalgamation of metamaterial (MM) ring resonator, split ring resonators (SRR), modified rectangular slot and Artificial Magnetic Conductor (AMC) backplane structure has been used to design proposed GNSS antenna. The frequency resonances obtained are narrow (large frequency ratio) and highly sensitive, thus impedance is perfectly matched for all five bands. The simulated results are closely matched with the measured results. High front to back ratio (FBR) obtained using novel MM AMC backplane. Gain enhancement of 5dBi obtained in GNSS antenna using AMC backplane structure. DRA miniaturization (98.6%) has been carried out using MM. The antenna results have been measured at L1 (1575.42 MHz/L2(1227.6 MHz)/L3(1381.05 MHz)/L4(1379.913 MHz) and L5 (1176.45 MHz) bands.

该设计的新颖之处在于矩形介质谐振器天线（RDRA）的小型化。其次，全球导航卫星系统（GNSS）的所有五个波段都积累在单一结构中。采用超材料环形谐振器（MM）、劈裂环形谐振器（SRR）、改进矩形槽和人工磁导体（AMC）背板组合结构设计了GNSS天线。获得的频率共振窄（大频率比）和高灵敏度，因此阻抗在所有五个波段都是完美匹配的。模拟结果与实测结果吻合较好。采用新型mmamc背板获得了高前后比（FBR）。采用AMC背板结构实现GNSS天线增益增强5dBi。在L1 (1575.42 MHz/L2(1227.6 MHz)/L3(1381.05 MHz)/L4（1379.913 MHz）和L5 （1176.45 MHz）频段测量了天线结果。

引用次数: 0

Isolation-enhanced dual band MIMO antenna with defective ground structure and stubs as a hybrid decoupling structure for next-generation sub-6 GHz uses 隔离增强双频MIMO天线，具有缺陷的接地结构和stub作为下一代sub-6 GHz应用的混合去耦结构

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-02-14 DOI: 10.1016/j.aeue.2026.156259

Vijaya Kumar Talluri, Lalit Kumar

This article presents a two-element and four-element isolation-enhanced dual-band MIMO antenna operating at 5.03 GHz and 6.02 GHz. With an ultra-compact inter-element spacing of only

0.03 λ_{0}

, mutual coupling becomes a major challenge. To address this issue, a hybrid decoupling (DC) structure integrating a defective ground structure (DGS) and a T-like shaped stub is proposed. This technique efficiently alters the surface current distribution, thereby suppressing mutual coupling and improving isolation. The two-element MIMO antenna with the proposed DC structure achieves an isolation (

| S_{21} |

) of 31 dB at the lower band and 45 dB at the upper band, with a peak gain of 6 dBi over both frequencies. In the four-element configuration, a maximum isolation of 15 dB at 5.03 GHz and 20 dB at 6.02 GHz is obtained, with corresponding gains of 5.3 dBi and 6.5 dBi, respectively. ECC below 0.0037 and a diversity gain close to 10 dB indicate excellent diversity performance within the antenna’s 10-dB impedance bandwidths of 90 MHz (4.98–5.07 GHz) and 80 MHz (5.98–6.06 GHz).The novelty of this work lies in achieving ultra-compact element spacing combined with remarkably high isolation (up to 45 dB), very low ECC (0.0037), and high radiation efficiency (up to 90%). These benefits make the suggested antenna ideal for tiny sub-6 GHz 5G and WLAN applications that need strong isolation and diversity.

本文介绍了一种工作频率为5.03 GHz和6.02 GHz的双元和四元隔离增强双频MIMO天线。由于元件间距超紧凑，仅为0.03λ0，因此相互耦合成为主要挑战。为了解决这一问题，提出了一种将缺陷接地结构（DGS）和t形存根集成在一起的混合去耦（DC）结构。该技术有效地改变了表面电流分布，从而抑制了相互耦合，提高了隔离度。采用所提出的直流结构的双元MIMO天线在下频段和上频段分别实现了31 dB和45 dB的隔离（|S21|），在两个频率上的峰值增益均为6 dBi。在四元配置下，5.03 GHz和6.02 GHz的最大隔离度分别为15 dB和20 dB，相应的增益分别为5.3 dBi和6.5 dBi。在天线的10db阻抗带宽为90 MHz （4.98-5.07 GHz）和80 MHz （5.98-6.06 GHz）范围内，ECC低于0.0037，分集增益接近10 dB，表明分集性能优异。这项工作的新颖之处在于实现了超紧凑的元件间距，并结合了非常高的隔离度（高达45 dB），非常低的ECC（0.0037）和高辐射效率（高达90%）。这些优点使建议的天线非常适合需要强大隔离和分集的小型6 GHz以下5G和WLAN应用。

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引用次数: 0

Ultra-wideband miniaturized Wilkinson power divider based on rectangular multi-section resonators with neural network-based enhancement 基于矩形多段谐振腔的超宽带小型化威尔金森功率分配器

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-20 DOI: 10.1016/j.aeue.2026.156220

Hesam Ghitasy Sarabi , Gholamreza Karimi , Milad Mohammadi , Derek Abbott

In this study, a novel compact Wilkinson power divider (PD) with high fractional bandwidth (FBW) and excellent isolation is proposed, designed, and experimentally validated. The structure employs rectangular multi-section resonators, replacing conventional transmission lines, achieving a significant size reduction of over 76% compared to traditional designs. Additionally, the multilayer perceptron (MLP) neural network algorithm is used to optimize performance, resulting in a very small mean relative error (MRE) and mean absolute error (MAE), indicating the design's optimality. The fabricated PD eliminates 16 unwanted harmonics with suppression levels below −20 dB across a wide frequency range of 1.152.5 GHz. Fabricated on an RT Duroid 5880 substrate, the measured results show excellent agreement with simulations, validating the design's reliability. Compared to existing Wilkinson power dividers, the proposed solution offers several key advantages: a 76% reduction in size, a FBW of 96%, and the suppression of harmonics up to the 16th order, which significantly enhances signal integrity. Additionally, the design's simplicity and efficiency ensure lower manufacturing costs, making it suitable for high-performance, cost-effective wireless communication systems.

在本研究中，提出、设计并实验验证了一种具有高分数带宽（FBW）和优异隔离性能的新型紧凑型威尔金森功率分压器（PD）。该结构采用矩形多段谐振器，取代了传统的传输线，与传统设计相比，尺寸减小了76%以上。此外，采用多层感知器（MLP）神经网络算法对性能进行优化，得到非常小的平均相对误差（MRE）和平均绝对误差（MAE），表明设计的最优性。制作的PD在1.152.5 GHz的宽频率范围内消除了16个不需要的谐波，抑制水平低于- 20 dB。在RT Duroid 5880衬底上制作的测量结果与仿真结果非常吻合，验证了设计的可靠性。与现有的Wilkinson功率分压器相比，提出的解决方案具有几个关键优势：尺寸减小76%，FBW为96%，谐波抑制高达16阶，显著提高了信号完整性。此外，该设计的简单性和高效率确保了较低的制造成本，使其适用于高性能，具有成本效益的无线通信系统。

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引用次数: 0