Pub Date : 2025-12-04DOI: 10.1016/j.aeue.2025.156164
Weibin Kong , Xiaoyu Zhang , Zhongqing Fang , Weidong Li , Lei Wang , Wenwen Yang , Rugang Wang , Ke Gong
The multilayer broadband radar absorber optimization problem (MBRAOP) is characterized as a mixed-variable multimodal multiobjective optimization problem (MVMMOP) in real-world applications. This paper proposes a novel approach called HEDA-DulMVMO to solve the MBRAOP. The method introduces an enhanced dual-population cooperative evolutionary mechanism to balance convergence and diversity in both the discrete decision space and the objective space. Additionally, the histogram-based estimation of distribution (EoD) model is employed to generate high-quality auxiliary evolutionary populations. The performance of the proposed approach is validated on the designed MVMMOP benchmark problems. Final optimization and evaluation are conducted on the multilayer broadband radar absorber (MBRA) for configurations ranging from 2 to 7 layers, with incident angles from 0°to 75°across five critical frequency bands. Experimental results on both the benchmark problems and the MBRA demonstrate the effectiveness and competitiveness of the proposed approach.
{"title":"Enhanced dual-population collaborative evolutionary mechanism assisted by EoD learning for optimization of MBRA design","authors":"Weibin Kong , Xiaoyu Zhang , Zhongqing Fang , Weidong Li , Lei Wang , Wenwen Yang , Rugang Wang , Ke Gong","doi":"10.1016/j.aeue.2025.156164","DOIUrl":"10.1016/j.aeue.2025.156164","url":null,"abstract":"<div><div>The multilayer broadband radar absorber optimization problem (MBRAOP) is characterized as a mixed-variable multimodal multiobjective optimization problem (MVMMOP) in real-world applications. This paper proposes a novel approach called HEDA-DulMVMO to solve the MBRAOP. The method introduces an enhanced dual-population cooperative evolutionary mechanism to balance convergence and diversity in both the discrete decision space and the objective space. Additionally, the histogram-based estimation of distribution (EoD) model is employed to generate high-quality auxiliary evolutionary populations. The performance of the proposed approach is validated on the designed MVMMOP benchmark problems. Final optimization and evaluation are conducted on the multilayer broadband radar absorber (MBRA) for configurations ranging from 2 to 7 layers, with incident angles from 0°to 75°across five critical frequency bands. Experimental results on both the benchmark problems and the MBRA demonstrate the effectiveness and competitiveness of the proposed approach.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156164"},"PeriodicalIF":3.2,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1016/j.aeue.2025.156158
Yassmeen M. Afify , Ahmed Allam , Haruichi Kanaya , Adel B. Abdelrahman
This paper investigates the impact of antenna gain on RF-to-DC power conversion efficiency (PCE) and sensitivity in a compact, wideband rectenna. We propose an asymmetric-arm I-slot (AAIS) antenna used in two configurations: (1) low-gain standalone, and (2) high-gain with a metallic reflecting surface (MRS) spaced at 0.15λ0 beneath the ground plane. Both configurations use the same single-stage voltage-doubler (VD) rectifier and load, enabling a controlled comparison. The MRS-backed AAIS achieves a peak gain of 9.2 dBi and an 840 MHz (22.2 %) bandwidth (3.36–4.20 GHz) while using a single radiating element. Compared with the low-gain variant, the high-gain rectenna delivers a 20 % absolute PCE improvement (60 % at 2 dBm vs. ∼ 40 % at 4 dBm) and reproduces the low-gain peak PCE at − 11 dBm (15 dB lower). The high-gain design also yields higher and more stable DC output (1.25 V at 0 dBm, 3.6 GHz, ±0.1 V across 3.5–4.0 GHz) and maintains usable DC (>0.5 V) down to − 7.5 dBm. These results demonstrate that a reflector-enhanced, single-element AAIS rectenna achieves simultaneous wideband operation, high efficiency, and improved low-power sensitivity for RF energy harvesting and WPT.
{"title":"Analysis of gain–efficiency relationship in a wideband rectenna for RF-powered IoT devices","authors":"Yassmeen M. Afify , Ahmed Allam , Haruichi Kanaya , Adel B. Abdelrahman","doi":"10.1016/j.aeue.2025.156158","DOIUrl":"10.1016/j.aeue.2025.156158","url":null,"abstract":"<div><div>This paper investigates the impact of antenna gain on RF-to-DC power conversion efficiency (PCE) and sensitivity in a compact, wideband rectenna. We propose an asymmetric-arm I-slot (AAIS) antenna used in two configurations: (1) low-gain standalone, and (2) high-gain with a metallic reflecting surface (MRS) spaced at 0.15λ<sub>0</sub> beneath the ground plane. Both configurations use the same single-stage voltage-doubler (VD) rectifier and load, enabling a controlled comparison. The MRS-backed AAIS achieves a peak gain of 9.2 dBi and an 840 MHz (22.2 %) bandwidth (3.36–4.20 GHz) while using a single radiating element. Compared with the low-gain variant, the high-gain rectenna delivers a 20 % absolute PCE improvement (60 % at 2 dBm vs. ∼ 40 % at 4 dBm) and reproduces the low-gain peak PCE at − 11 dBm (15 dB lower). The high-gain design also yields higher and more stable DC output (1.25 V at 0 dBm, 3.6 GHz, ±0.1 V across 3.5–4.0 GHz) and maintains usable DC (>0.5 V) down to − 7.5 dBm. These results demonstrate that a reflector-enhanced, single-element AAIS rectenna achieves simultaneous wideband operation, high efficiency, and improved low-power sensitivity for RF energy harvesting and WPT.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156158"},"PeriodicalIF":3.2,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-04DOI: 10.1016/j.aeue.2025.156120
Tian-Gui Huang , Sa Yang , Fu-Chang Chen , Kai-Ran Xiang , Ming-Yang Su
This paper presents a novel methodology for designing a two-dimensional (2-D) pattern reconfigurable array. The design integrates a conventional 4 × 4 Butler matrix with a reconfigurable antenna array to achieve two-dimensional beamforming capabilities. Beamforming in one dimension is accomplished via the 4 × 4 Butler matrix, while in the other orthogonal direction, beam steering is achieved through the use of two pairs of metal walls vertically placed on both sides of the driven antenna elements. Each pair of metal walls is loaded with a PIN diode at the center, accompanied by its DC biasing feeding network. By controlling the different states of the switching PIN diodes loaded between the metal walls, the beam steering characteristic can be obtained. An experimental antenna is designed and manufactured to validate this approach. When the antenna is excited from various ports, it yields four distinct radiation orientations within the plane. For each port activation, the antenna exhibits three unique radiation patterns, resulting in three different radiation directions in the plane orthogonal to the plane. This configuration ultimately realizes 2-D beam scanning, encompassing a total of twelve directions.
{"title":"A novel 2-D pattern reconfigurable array using beamforming networks and reconfigurable antenna array","authors":"Tian-Gui Huang , Sa Yang , Fu-Chang Chen , Kai-Ran Xiang , Ming-Yang Su","doi":"10.1016/j.aeue.2025.156120","DOIUrl":"10.1016/j.aeue.2025.156120","url":null,"abstract":"<div><div>This paper presents a novel methodology for designing a two-dimensional (2-D) pattern reconfigurable array. The design integrates a conventional 4 × 4 Butler matrix with a reconfigurable antenna array to achieve two-dimensional beamforming capabilities. Beamforming in one dimension is accomplished via the 4 × 4 Butler matrix, while in the other orthogonal direction, beam steering is achieved through the use of two pairs of metal walls vertically placed on both sides of the driven antenna elements. Each pair of metal walls is loaded with a PIN diode at the center, accompanied by its DC biasing feeding network. By controlling the different states of the switching PIN diodes loaded between the metal walls, the beam steering characteristic can be obtained. An experimental antenna is designed and manufactured to validate this approach. When the antenna is excited from various ports, it yields four distinct radiation orientations within the <span><math><mrow><mi>x</mi><mi>o</mi><mi>z</mi></mrow></math></span> plane. For each port activation, the antenna exhibits three unique radiation patterns, resulting in three different radiation directions in the plane orthogonal to the <span><math><mrow><mi>x</mi><mi>o</mi><mi>z</mi></mrow></math></span> plane. This configuration ultimately realizes 2-D beam scanning, encompassing a total of twelve directions.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156120"},"PeriodicalIF":3.2,"publicationDate":"2025-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.aeue.2025.156165
Xiaojuan Bai, Caixia Liang, Tianxiang Liu, Ao Gao
In this paper, we investigate a simultaneously transmitting and reflecting reconfigurable intelligent surface (STAR-RIS)-assisted downlink multi-user (MU) simultaneous wireless information and power transfer (SWIPT) system to overcome the performance limitations of SWIPT system caused by environmental factors and the deployment constraints of traditional RIS. We adopt a practical non-linear energy harvesting (EH) model and design a resource allocation algorithm for SWIPT systems. By applying the energy splitting (ES) protocol of STAR-RIS, we aim to improve both the transmission rate and EH. Therefore, we formulate a multi-objective optimization problem (MOOP) to simultaneously maximize both the weighted sum rate and EH, by jointly optimizing the base station (BS) beamforming, STAR-RIS coefficient matrices, and power splitting (PS) ratio. To address the non-convexity and variable coupling, an efficient alternating optimization (AO) algorithm integrating fractional programming (FP) and semidefinite relaxation (SDR) is proposed, which decomposes the original problem into three tractable subproblems solved iteratively. Simulation results indicate favorable convergence behavior of the proposed algorithm and achieve substantial performance gains facilitated by the STAR-RIS. The proposed scheme outperforms benchmark schemes in both sum rate and EH, thereby providing theoretical support for the design of future energy-efficient communication networks.
{"title":"Research on joint optimization of rate and energy harvesting in STAR-RIS-empowered SWIPT system","authors":"Xiaojuan Bai, Caixia Liang, Tianxiang Liu, Ao Gao","doi":"10.1016/j.aeue.2025.156165","DOIUrl":"10.1016/j.aeue.2025.156165","url":null,"abstract":"<div><div>In this paper, we investigate a simultaneously transmitting and reflecting reconfigurable intelligent surface (STAR-RIS)-assisted downlink multi-user (MU) simultaneous wireless information and power transfer (SWIPT) system to overcome the performance limitations of SWIPT system caused by environmental factors and the deployment constraints of traditional RIS. We adopt a practical non-linear energy harvesting (EH) model and design a resource allocation algorithm for SWIPT systems. By applying the energy splitting (ES) protocol of STAR-RIS, we aim to improve both the transmission rate and EH. Therefore, we formulate a multi-objective optimization problem (MOOP) to simultaneously maximize both the weighted sum rate and EH, by jointly optimizing the base station (BS) beamforming, STAR-RIS coefficient matrices, and power splitting (PS) ratio. To address the non-convexity and variable coupling, an efficient alternating optimization (AO) algorithm integrating fractional programming (FP) and semidefinite relaxation (SDR) is proposed, which decomposes the original problem into three tractable subproblems solved iteratively. Simulation results indicate favorable convergence behavior of the proposed algorithm and achieve substantial performance gains facilitated by the STAR-RIS. The proposed scheme outperforms benchmark schemes in both sum rate and EH, thereby providing theoretical support for the design of future energy-efficient communication networks.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156165"},"PeriodicalIF":3.2,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.aeue.2025.156161
Akbar Asgharzadeh Bonab , Khashayar Dehghan , Jalil Mazloum
This paper presents a novel wireless power transfer and data telemetry circuit for biomedical implants that enhances both data rate and power delivery to the load. The proposed system employs a multi-coil, single-carrier frequency shift keying (FSK) transmitter architecture, where power and data are simultaneously transmitted via three magnetically coupled resonant links. These links are excited by a class-D amplifier operating at the first, third, and ninth harmonics of a base frequency. Bit encoding is performed by switching between two resonant modes: when the data bit is “0,” the system transmits at the base frequency f0; when the bit is “1,” it switches to 3f0. This design leverages first, third, and ninth harmonic resonance to improve power delivered to the load and simplify modulation circuitry. The system has an ability to achieve a data rate equal to f0, resulting in a data-rate-to-f0 ratio of 100 %. A proof-of-concept prototype was implemented on a printed circuit board and evaluated at operating frequencies of 298 kHz and 894 kHz. The transmitter delivers 1.1 W to the load with a power transfer efficiency of approximately 42 %, achieving a data rate of 0.298 Mbps and a bit error rate (BER) .
{"title":"A multi-harmonic class-D FSK power and data transmitter with enhanced load power delivery and high data rate to carrier frequency ratio for biomedical implants","authors":"Akbar Asgharzadeh Bonab , Khashayar Dehghan , Jalil Mazloum","doi":"10.1016/j.aeue.2025.156161","DOIUrl":"10.1016/j.aeue.2025.156161","url":null,"abstract":"<div><div>This paper presents a novel wireless power transfer and data telemetry circuit for biomedical implants that enhances both data rate and power delivery to the load. The proposed system employs a multi-coil, single-carrier frequency shift keying (FSK) transmitter architecture, where power and data are simultaneously transmitted via three magnetically coupled resonant links. These links are excited by a class-D amplifier operating at the first, third, and ninth harmonics of a base frequency. Bit encoding is performed by switching between two resonant modes: when the data bit is “0,” the system transmits at the base frequency f<sub>0</sub>; when the bit is “1,” it switches to 3f<sub>0</sub>. This design leverages first, third, and ninth harmonic resonance to improve power delivered to the load and simplify modulation circuitry. The system has an ability to achieve a data rate equal to f<sub>0</sub>, resulting in a data-rate-to-f<sub>0</sub> ratio of 100 %. A proof-of-concept prototype was implemented on a printed circuit board and evaluated at operating frequencies of 298 kHz and 894 kHz. The transmitter delivers 1.1 W to the load with a power transfer efficiency of approximately 42 %, achieving a data rate of 0.298 Mbps and a bit error rate (BER) <span><math><mrow><mn>5.33</mn><mo>×</mo><msup><mrow><mn>10</mn></mrow><mrow><mo>-</mo><mn>6</mn></mrow></msup></mrow></math></span>.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156161"},"PeriodicalIF":3.2,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-12-02DOI: 10.1016/j.aeue.2025.156163
Muhammad Hashim, Zhiqun Li, Qin Li, Weiwen Lin
An ultra-wideband balun low-noise amplifier (LNA) operating from 1 to 7.8 GHz is proposed for multi-standard wireless applications. The architecture integrates a gm-boosted common-source (CS) amplifier with a common-gate common-source (CG–CS) balun to enable single-to-differential signal conversion. A complementary nMOS-pMOS configuration is employed to enhance transconductance, reduce noise, and improve gain. A cross-coupled balancing circuit (CBC) is incorporated in the load to provide noise cancellation along with gain and phase correction. Wideband input matching is achieved through the combination of a resistive feedback buffer (RFB) and a series on-chip inductor Lg. Theoretical analysis, closed-form expressions, and simulation results demonstrate that the CBC improves the noise figure (NF), while the RFB and Lg enable effective input impedance matching. The LNA was fabricated using the TSMC 40-nm CMOS process, and measured results show a gain of 18.5 dB and an NF ranging from 2 to 3 dB. Additional performance metrics include an input 1-dB compression point (IP1dB) of −17 dBm, an input third-order intercept point (IIP3) of −1 dBm at 4 GHz, and S11 less than −10 dB across the 1–7.8 GHz band. The design consumes 12 mA from a 1.2 V supply and occupies an active chip area of 0.16 mm2.
{"title":"Design and optimization of a 1–7.8 GHz wideband low noise amplifier with 2 dB noise figure","authors":"Muhammad Hashim, Zhiqun Li, Qin Li, Weiwen Lin","doi":"10.1016/j.aeue.2025.156163","DOIUrl":"10.1016/j.aeue.2025.156163","url":null,"abstract":"<div><div>An ultra-wideband balun low-noise amplifier (LNA) operating from 1 to 7.8 GHz is proposed for multi-standard wireless applications. The architecture integrates a <em>g<sub>m</sub></em>-boosted common-source (CS) amplifier with a common-gate common-source (CG–CS) balun to enable single-to-differential signal conversion. A complementary nMOS-pMOS configuration is employed to enhance transconductance, reduce noise, and improve gain. A cross-coupled balancing circuit (CBC) is incorporated in the load to provide noise cancellation along with gain and phase correction. Wideband input matching is achieved through the combination of a resistive feedback buffer (RFB) and a series on-chip inductor <em>L<sub>g</sub></em>. Theoretical analysis, closed-form expressions, and simulation results demonstrate that the CBC improves the noise figure (NF), while the RFB and <em>L<sub>g</sub></em> enable effective input impedance matching. The LNA was fabricated using the TSMC 40-nm CMOS process, and measured results show a gain of 18.5 dB and an NF ranging from 2 to 3 dB. Additional performance metrics include an input 1-dB compression point (IP1dB) of −17 dBm, an input third-order intercept point (IIP3) of −1 dBm at 4 GHz, and S<sub>11</sub> less than −10 dB across the 1–7.8 GHz band. The design consumes 12 mA from a 1.2 V supply and occupies an active chip area of 0.16 mm<sup>2</sup>.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156163"},"PeriodicalIF":3.2,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145736900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cardiovascular diseases are a leading cause of mortality worldwide. Recent efforts focus on hardware-based emulation of cardiac pacemaker cells using differential equation models for the electrophysiological activity of sinoatrial (SA) and Purkinje Fiber (PF) cells. While these models provide high signal fidelity, they assume ideal, noise-free conditions, ignoring the inevitable presence of noise in biological and digital biosensor systems, including implantable bioelectronic platforms. This study presents a hardware module for real-time noise correction in cardiac biosignals, designed for processing data from various sources by identifying disturbances and applying corrective algorithms. It examines noise correction using two filtering algorithms: Least Mean Squares (LMS) and Unscented Kalman Filter (UKF), highlighting the specific advantages and applications of each. Additionally, the impact of several optimization techniques on the results of the hardware implementation, including accuracy, power consumption, resource usage, and frequency, is analyzed. This work can serve as an initial step toward integrating adaptive noise correction methods into future implantable or diagnostic cardiac biosensing systems, enhancing the robustness and reliability of next-generation bioelectronic interfaces.
{"title":"A real-time FPGA-based hardware module for adaptive noise correction in cardiac bioelectronic systems: Toward robust signal conditioning for implantable biosensors","authors":"Milad Ghanbarpour , Muhammad Akmal Chaudhary , Maher Assaad , Gilda Ghanbarpour","doi":"10.1016/j.aeue.2025.156162","DOIUrl":"10.1016/j.aeue.2025.156162","url":null,"abstract":"<div><div>Cardiovascular diseases are a leading cause of mortality worldwide. Recent efforts focus on hardware-based emulation of cardiac pacemaker cells using differential equation models for the electrophysiological activity of sinoatrial (SA) and Purkinje Fiber (PF) cells. While these models provide high signal fidelity, they assume ideal, noise-free conditions, ignoring the inevitable presence of noise in biological and digital biosensor systems, including implantable bioelectronic platforms. This study presents a hardware module for real-time noise correction in cardiac biosignals, designed for processing data from various sources by identifying disturbances and applying corrective algorithms. It examines noise correction using two filtering algorithms: Least Mean Squares (LMS) and Unscented Kalman Filter (UKF), highlighting the specific advantages and applications of each. Additionally, the impact of several optimization techniques on the results of the hardware implementation, including accuracy, power consumption, resource usage, and frequency, is analyzed. This work can serve as an initial step toward integrating adaptive noise correction methods into future implantable or diagnostic cardiac biosensing systems, enhancing the robustness and reliability of next-generation bioelectronic interfaces.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156162"},"PeriodicalIF":3.2,"publicationDate":"2025-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-29DOI: 10.1016/j.aeue.2025.156159
Deepak Ram, Amit Kumar Singh, Somak Bhattacharyya
This article presents a compact and cost-effective metasurface-loaded microstrip antenna capable of dual-band circular polarization. The design utilizes a corner-trimmed square patch with a cross-shaped slot on an FR-4 substrate (1.6 mm thick) backed by a metallic ground. Performance enhancement is achieved using two metasurface layers: the first consists of sixteen square-ring elements in a 4 × 4 periodic array on an FR-4 sheets, and the second comprises a 4 × 4 array of square elements with hexagonal slots placed 9 mm above the first layer using an air gap. The antenna operates at two frequency bands, offering impedance bandwidths of 6.14 % (4.1–4.36 GHz) and 9.91 % (5.08–5.61 GHz). The axial ratio bandwidths are 3.22 % (4.27–4.41 GHz) and 5.1 % (5.15–5.42 GHz), confirming dual-band circular polarization. It achieves realized gains of 4.83 dBic and 5.74 dBic with efficiencies of 65 % and 61 % at 4.30 and 5.36 GHz, respectively, exhibiting left-handed CP radiation. An equivalent circuit model was developed and validated through simulations and experiments, showing strong agreement. With compact dimensions of 0.54λ0 × 0.54λ0 × 0.023λ0 at 4.30 GHz, the antenna is well-suited for 5G and satellite communication applications.
{"title":"A low-cost dual-band metasurface-based circularly polarized patch antenna with enhanced gain","authors":"Deepak Ram, Amit Kumar Singh, Somak Bhattacharyya","doi":"10.1016/j.aeue.2025.156159","DOIUrl":"10.1016/j.aeue.2025.156159","url":null,"abstract":"<div><div>This article presents a compact and cost-effective metasurface-loaded microstrip antenna capable of dual-band circular polarization. The design utilizes a corner-trimmed square patch with a cross-shaped slot on an FR-4 substrate (1.6 mm thick) backed by a metallic ground. Performance enhancement is achieved using two metasurface layers: the first consists of sixteen square-ring elements in a 4 × 4 periodic array on an FR-4 sheets, and the second comprises a 4 × 4 array of square elements with hexagonal slots placed 9 mm above the first layer using an air gap. The antenna operates at two frequency bands, offering impedance bandwidths of 6.14 % (4.1–4.36 GHz) and 9.91 % (5.08–5.61 GHz). The axial ratio bandwidths are 3.22 % (4.27–4.41 GHz) and 5.1 % (5.15–5.42 GHz), confirming dual-band circular polarization. It achieves realized gains of 4.83 dBic and 5.74 dBic with efficiencies of 65 % and 61 % at 4.30 and 5.36 GHz, respectively, exhibiting left-handed CP radiation. An equivalent circuit model was developed and validated through simulations and experiments, showing strong agreement. With compact dimensions of 0.54λ<sub>0</sub> × 0.54λ<sub>0</sub> × 0.023λ<sub>0</sub> at 4.30 GHz, the antenna is well-suited for 5G and satellite communication applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156159"},"PeriodicalIF":3.2,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-29DOI: 10.1016/j.aeue.2025.156157
Sara Paul, R.K. Kavitha
In this manuscript, a 4T1C cryogenic inverse memristor emulator is proposed which operates at a maximum frequency of 100 MHz. It is able to operate from room temperature (RT) to mid-cryogenic temperature (77 K to 20 K) without much design efforts. The proposed design is implemented in UMC 65 nm technology and analyzed at various frequency and voltage levels, both at RT and cryogenic temperatures. The power consumption of 4T1C inverse memristor emulator is W, W and W at 20 K, 77 K and RT respectively. It exhibits a 48% reduction in power consumption at 20 K and a 34% reduction at 77 K, when compared to RT. The proposed design occupies the least area of m which is 3 to 5 times lesser than other CMOS inverse emulators. Process corner and Monte-carlo simulations are performed to validate the stability and robustness. The potential practical applications are analyzed by implementing both analog and digital circuits. The analog circuits being explored through RC filters and Schmitt triggers, while the digital circuits are analyzed by memristor based NOT and NOR gates. Hence, the proposed inverse memristor emulator circuit offers a low frequency as well as high frequency applications in both room and Cryogenic temperature with least area and power consumption.
{"title":"A 4T1C Cryogenic Inverse CMOS Memristor Emulator For Quantum Computing Application","authors":"Sara Paul, R.K. Kavitha","doi":"10.1016/j.aeue.2025.156157","DOIUrl":"10.1016/j.aeue.2025.156157","url":null,"abstract":"<div><div>In this manuscript, a 4T1C cryogenic inverse memristor emulator is proposed which operates at a maximum frequency of 100 MHz. It is able to operate from room temperature (RT) to mid-cryogenic temperature (77 K to 20 K) without much design efforts. The proposed design is implemented in UMC 65 nm technology and analyzed at various frequency and voltage levels, both at RT and cryogenic temperatures. The power consumption of 4T1C inverse memristor emulator is <span><math><mrow><mn>47</mn><mspace></mspace><mi>μ</mi></mrow></math></span>W, <span><math><mrow><mn>55</mn><mspace></mspace><mi>μ</mi></mrow></math></span>W and <span><math><mrow><mn>75</mn><mspace></mspace><mi>μ</mi></mrow></math></span>W at 20 K, 77 K and RT respectively. It exhibits a 48% reduction in power consumption at 20 K and a 34% reduction at 77 K, when compared to RT. The proposed design occupies the least area of <span><math><mrow><mn>74</mn><mspace></mspace><mi>μ</mi></mrow></math></span>m<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> which is 3 to 5 times lesser than other CMOS inverse emulators. Process corner and Monte-carlo simulations are performed to validate the stability and robustness. The potential practical applications are analyzed by implementing both analog and digital circuits. The analog circuits being explored through RC filters and Schmitt triggers, while the digital circuits are analyzed by memristor based NOT and NOR gates. Hence, the proposed inverse memristor emulator circuit offers a low frequency as well as high frequency applications in both room and Cryogenic temperature with least area and power consumption.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156157"},"PeriodicalIF":3.2,"publicationDate":"2025-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145684730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-27DOI: 10.1016/j.aeue.2025.156156
Sriparna Sarma, Tshering Sangmoo Sherpa, Sanjay Kumar Jana
This paper proposes high-performance, low-power Phase-Locked Loop (PLL) architecture designed using transmission-gate-based Phase Frequency Detector (PFD) and 12-transistor-based MOS Charge Pump (CP) implemented using the SCL 180 nm CMOS process and simulated in Cadence Virtuoso environment. The proposed PFD eliminate blind zones and reduces dead zone to 4 ps through direct reset mechanism, operating over 1–6.5 GHz frequency range using only eight transistors, resulting in a low power consumption of 171.2 W and phase noise of –156.4 dBc/Hz at 1 MHz offset. The proposed CP achieves minimal current mismatch of 0.33 % while consuming 181.8 W. The proposed PFD-CP is integrated with a conventional loop filter, voltage-controlled oscillator and frequency divider to design a 2.5 GHz PLL, which achieves lock time below 20 ns and spur-to-floor delta of 72.07 dB. The compact core area of 0.0014 mm and power consumption of 338.8 W are achieved. It demonstrates that approximately 80%–85% smaller area and 75%–90% lower power consumption compared to recent state-of-the-art, along with 10 dB improvement in spur suppression and two-times faster locking response, highlighting its efficiency and scalability for high-speed, low-spur, low-jitter Serializer–Deserializer (SERDES) and clock recovery systems. The Monte Carlo simulation and Process, Voltage, Temperature (PVT) analyses confirm robust performance of the design.
{"title":"Transmission-gate based Phase Frequency Detector and 0.33% current mismatch MOS charge pump for reference spur reduction in 2.5 GHz PLL","authors":"Sriparna Sarma, Tshering Sangmoo Sherpa, Sanjay Kumar Jana","doi":"10.1016/j.aeue.2025.156156","DOIUrl":"10.1016/j.aeue.2025.156156","url":null,"abstract":"<div><div>This paper proposes high-performance, low-power Phase-Locked Loop (PLL) architecture designed using transmission-gate-based Phase Frequency Detector (PFD) and 12-transistor-based MOS Charge Pump (CP) implemented using the SCL 180 nm CMOS process and simulated in Cadence Virtuoso environment. The proposed PFD eliminate blind zones and reduces dead zone to 4 ps through direct reset mechanism, operating over 1–6.5 GHz frequency range using only eight transistors, resulting in a low power consumption of 171.2 <span><math><mi>μ</mi></math></span> W and phase noise of –156.4 dBc/Hz at 1 MHz offset. The proposed CP achieves minimal current mismatch of 0.33 % while consuming 181.8 <span><math><mi>μ</mi></math></span> W. The proposed PFD-CP is integrated with a conventional loop filter, voltage-controlled oscillator and frequency divider to design a 2.5 GHz PLL, which achieves lock time below 20 ns and spur-to-floor delta of 72.07 dB. The compact core area of 0.0014 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> and power consumption of 338.8 <span><math><mi>μ</mi></math></span> W are achieved. It demonstrates that approximately 80%–85% smaller area and 75%–90% lower power consumption compared to recent state-of-the-art, along with 10 dB improvement in spur suppression and two-times faster locking response, highlighting its efficiency and scalability for high-speed, low-spur, low-jitter Serializer–Deserializer (SERDES) and clock recovery systems. The Monte Carlo simulation and Process, Voltage, Temperature (PVT) analyses confirm robust performance of the design.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"205 ","pages":"Article 156156"},"PeriodicalIF":3.2,"publicationDate":"2025-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145617914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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