Aeu-International Journal of Electronics and Communications最新文献_第3页

Creative and accurate method for optimal hardware implementation of neurons and biological cells: Application in FPGA-based implementation of cardiac pacemaker cell 创造性地采用精确方法优化神经元和生物细胞的硬件实现：在基于 FPGA 的心脏起搏器细胞实现中的应用

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-19 DOI: 10.1016/j.aeue.2024.155561

Gilda Ghanbarpour , Milad Ghanbarpour , Pourya Spari

The sinoatrial (SA) node cells play a vital role as the principal pacemaker in mammalian hearts, generating regular and spontaneous action potentials to regulate the heart’s rhythm. Comprehending the intricate activity of the SA node’s operation necessitates a collection of differential formulas that tackle non-linear functions. The study presents a new technique to improve the digital representation of the SA node cell model, offering benefits such as decreased hardware needs, enhanced processing speed and accuracy, and reduced implementation expenses by transforming the original model’s differential equations into a unified trigonometric function. This transformation significantly simplifies the computational complexity by eliminating the need for multipliers, resulting in a streamlined set of mathematical expressions. The digital implementation of this novel method can be efficiently realized using the Coordinate Rotation Digital Computer (CORDIC) algorithm, which circumvents the necessity for cumbersome mathematical operations. To demonstrate the viability of this approach, the proposed model is successfully synthesized and implemented on a Field-Programmable Gate Array (FPGA). The results of the implementation demonstrate a significant rise in the operating frequency, which is approximately 6.14 times greater than that of the original model. Furthermore, there is a notable 45 percent decrease in power usage. The lowered hardware needs make significant scalability possible, thus allowing for the inclusion of approximately 12 times as many SA node cells on a sole FPGA board in comparison to the original design.

中房（SA）结细胞作为哺乳动物心脏的主要起搏器发挥着至关重要的作用，它产生有规律的自发动作电位来调节心脏节律。要理解 SA 节点错综复杂的运行活动，就必须收集处理非线性函数的微分公式。这项研究提出了一种改进 SA 节点细胞模型数字表示的新技术，通过将原始模型的微分方程转换为统一的三角函数，提供了减少硬件需求、提高处理速度和准确性以及减少实施费用等好处。这种转换无需使用乘法器，从而大大简化了计算的复杂性，使数学表达式更加精简。使用坐标旋转数字计算机（CORDIC）算法可以有效地实现这种新方法的数字化，从而避免了繁琐的数学运算。为了证明这种方法的可行性，我们成功地在现场可编程门阵列（FPGA）上合成并实现了所提出的模型。实施结果表明，工作频率显著提高，约为原始模型的 6.14 倍。此外，功耗显著降低了 45%。硬件需求的降低使可扩展性成为可能，因此，在一块 FPGA 板上安装的 SA 节点单元数量大约是原始设计的 12 倍。

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引用次数: 0

A low-power quadrature voltage-controlled oscillators with LC emitter degeneration phase shift technique 采用 LC 发射极退化相移技术的低功耗正交压控振荡器

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-18 DOI: 10.1016/j.aeue.2024.155557

Jianxing Lin , Jinghu Li , Zhicong Luo , Mingyan Yu

This paper introduces a novel phase-shifting technique for quadrature voltage-controlled oscillators (QVCOs) utilizing an LC emitter degeneration architecture. The proposed technique enables a phase shift of up to ±90°in the transconductance of the coupling path while also generating a negative input resistance. This innovative approach avoids phase ambiguity, mitigates the trade-off between phase noise and phase error, and substantially reduces QVCO power consumption. Moreover, compared to conventional capacitance emitter degeneration methods, the LC emitter degeneration structure has a lower equivalent input capacitance, expanding the QVCO’s frequency tuning range. The designed QVCO is implemented using a 180 nm SiGe BiCMOS technology, occupying a compact area of 0.037 mm

^{2}

. Post-layout simulation evaluations under various process, voltage, and temperature (PVT) conditions validate the robustness and reliability of the design. Results indicate a phase noise of 102.7 dBc/Hz at a 1 MHz offset from a 22.1 GHz carrier, a frequency tuning range of 25.2%, a phase error of 0.9°, and a power consumption of 12 mW from a 1.1 V supply, achieving a figure of merit (FoM) of 178.8 dBc/Hz.

本文介绍了一种利用 LC 发射极退化结构的正交压控振荡器 (QVCO) 新型移相技术。所提出的技术可在耦合路径的跨导中实现高达 ±90° 的相移，同时还能产生负输入电阻。这种创新方法避免了相位模糊，减轻了相位噪声和相位误差之间的权衡，并大幅降低了 QVCO 功耗。此外，与传统的电容发射极退化方法相比，LC 发射极退化结构具有更低的等效输入电容，从而扩大了 QVCO 的频率调谐范围。所设计的 QVCO 采用 180 nm SiGe BiCMOS 技术实现，占地面积仅为 0.037 mm2。在各种工艺、电压和温度 (PVT) 条件下进行的布局后仿真评估验证了设计的稳健性和可靠性。结果表明，从 22.1 GHz 载波偏移 1 MHz 时的相位噪声为 102.7 dBc/Hz，频率调整范围为 25.2%，相位误差为 0.9°，1.1 V 电源功耗为 12 mW，优点系数 (FoM) 为 178.8 dBc/Hz。

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引用次数: 0

Data-adaptive hybrid control for power quality improvement using H-bridge circuit 利用 H 桥电路改善电能质量的数据自适应混合控制

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-18 DOI: 10.1016/j.aeue.2024.155560

Ravi Kumar Majji , Tirumalasetty Chiranjeevi , Radha Kumari N , G krishnaveni

The extraction of fundamental current and controlling the H-bridge circuit, called shunt active power filter (SAPF), for power quality support have always been major research concerns. The effectiveness of a SAPF depends on its fundamental component estimation. In this context, empirical mode decomposition (EMD) is applied to SAPF operations due to its effectiveness in complex signal analysis. Being a data-driven, adaptive tool, EMD decomposes the distorted nonlinear signal into signal- and noise-dominated signals, called intrinsic mode functions (IMFs). However, its exploitation has been hindered by its mode mixing issue. As a remedy, a second-order generalized integrator (SOGI) is integrated with the EMD approach to extract the required fundamental active component of distorted load current. Thus, this work investigates the effect of an EMD-based SOGI hybrid control approach in extracting the fundamental active component of distorted load current. The MATLAB/Simulink results demonstrate the effectiveness of the proposed hybrid control strategy for nonlinear load current generated by the diode bridge rectifier. Furthermore, the simulated results are validated through a real-time simulation result using the OPAL-RT OP4510 test bench. Results are analyzed under sinusoidal and distorted voltage scenarios at the point of common coupling. The simulation results showed that the proposed hybrid control approach provides better active filtering efficiency, support for reactive power, and improved total harmonic distortion, which meets the IEEE 1547-2018 standard.

提取基波电流和控制 H 桥电路（称为并联有源电力滤波器（SAPF））以支持电能质量一直是研究的主要关注点。SAPF 的有效性取决于其基波分量的估计。在这种情况下，经验模式分解（EMD）因其在复杂信号分析中的有效性而被应用于 SAPF 操作。作为一种数据驱动的自适应工具，EMD 将畸变的非线性信号分解为以信号和噪声为主的信号，称为本征模式函数（IMF）。然而，模式混合问题阻碍了 EMD 的应用。作为一种补救措施，二阶广义积分器 (SOGI) 与 EMD 方法相结合，提取出所需的畸变负载电流基波有功分量。因此，这项工作研究了基于 EMD 的 SOGI 混合控制方法在提取畸变负载电流基波有功分量方面的效果。MATLAB/Simulink 结果表明，针对二极管桥整流器产生的非线性负载电流，所提出的混合控制策略非常有效。此外，模拟结果还通过 OPAL-RT OP4510 测试台的实时模拟结果进行了验证。在共耦合点的正弦和畸变电压情况下对结果进行了分析。仿真结果表明，所提出的混合控制方法提供了更好的有源滤波效率，支持无功功率，并改善了总谐波失真，符合 IEEE 1547-2018 标准。

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引用次数: 0

Charge pump-based PVT-resilient 45 nm CMOS dynamic comparator leveraging high speed and power efficiency 基于电荷泵的抗 PVT 45 纳米 CMOS 动态比较器，实现高速度和高能效

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-16 DOI: 10.1016/j.aeue.2024.155550

K. Brindha, J. Manjula

High-speed, low-power consumption, compact area, and high resolution are critical for analog/mixed signal applications. This article presents a novel design for a dynamic latch comparator that achieves exceptional speed, minimal power consumption, and a significantly reduced die area. The innovative comparator leverages a novel charge shared logic-based reset technique, which enables unparalleled speed and power efficiency. Rigorous simulations and analyses confirm that the delay time is drastically reduced compared to traditional dynamic latched comparators. The results clearly indicate that the proposed design exhibits high tolerance to PVT (process, voltage, and temperature) variations, making it highly suitable for mixed-signal applications. Designed and simulated using advanced 45 nm CMOS technology, the proposed circuit achieves an impressive delay of 18.5 ps and a remarkably low power consumption of 3.66 μW at a 1 V supply voltage and 1 GHz clock frequency.

高速、低功耗、小面积和高分辨率对于模拟/混合信号应用至关重要。本文介绍了一种新颖的动态锁存器比较器设计，该比较器速度极快、功耗极低、芯片面积显著减小。这种创新型比较器采用了基于电荷共享逻辑的新型复位技术，从而实现了无与伦比的速度和能效。严格的仿真和分析证实，与传统的动态锁存比较器相比，延迟时间大大缩短。结果清楚地表明，所提出的设计对 PVT（工艺、电压和温度）变化具有很高的耐受性，因此非常适合混合信号应用。该电路采用先进的 45 纳米 CMOS 技术进行设计和仿真，在 1 V 电源电压和 1 GHz 时钟频率条件下，实现了 18.5 ps 的惊人延迟和 3.66 μW 的显著低功耗。

引用次数: 0

A novel semi-angle-based index modulation scheme for MIMO visible light communication 用于多输入多输出可见光通信的新型半角度指数调制方案

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-15 DOI: 10.1016/j.aeue.2024.155555

Manh Le-Tran , Thai-Hoc Vu

Visible light communication (VLC) with the use of multiple light-emitting diodes (LEDs) has recently offered extensive indoor coverage for both communication and illumination purposes. Meanwhile, index modulation refers to modulation techniques that use the indices of certain mediums to transmit additional information. The medium can be a time slot, frequency carrier, or especially antenna activation index. In this paper, we present the first attempt at semi-angle-based index modulation for a visible light communication (VLC) system by using LED with different semi-angle values. Instead of using identical semi-angle LEDs, multiple LEDs are divided into several clusters and all LEDs in each cluster have different semi-angle values. Moreover, at any time of transmission, only some clusters are active, and only a single LED of each active cluster is used to convey the pulse amplitude modulation (PAM) signal. We also proposed a minimum mean-squared error (MMSE) based maximum likelihood (ML) detector that performs ML detection on some candidates based on an initial MMSE solution. The simulation results show that the proposed scheme significantly improves the symbol error rate (SER) compared to conventional schemes. Finally, the proposed detector also proves to approach the ML detector performance while still maintaining acceptable complexity cost.

最近，使用多个发光二极管（LED）的可见光通信（VLC）已在室内广泛应用，既可用于通信，也可用于照明。同时，指数调制是指利用某些介质的指数来传输附加信息的调制技术。介质可以是时隙、频率载波，特别是天线激活指数。在本文中，我们首次尝试在可见光通信（VLC）系统中使用基于半角的指数调制，即使用不同半角值的 LED。我们没有使用完全相同的半角 LED，而是将多个 LED 分成若干个簇，每个簇中的所有 LED 都具有不同的半角值。此外，在任何传输时间，只有部分簇处于活动状态，每个活动簇中只有一个 LED 用来传输脉冲幅度调制（PAM）信号。我们还提出了一种基于最小均方误差（MMSE）的最大似然（ML）检测器，该检测器根据初始 MMSE 解法对一些候选信号执行 ML 检测。仿真结果表明，与传统方案相比，拟议方案显著提高了符号错误率（SER）。最后，所提出的检测器还能在保持可接受的复杂度成本的同时，接近 ML 检测器的性能。

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引用次数: 0

A simple picowatt 7.6 ppm/°C, 0.029 %/V line sensitivity fully-CMOS voltage reference with DIBL cancelation 一款简单的皮瓦 7.6 ppm/°C、0.029 %/V 线路灵敏度全 CMOS 电压基准，具有 DIBL 取消功能

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-12 DOI: 10.1016/j.aeue.2024.155558

Ali Esmailpoor, Emad Ebrahimi

In this paper, a 4-transistor sub-one-volt voltage reference with picowatt power consumption is presented. To achieve ultra-low power consumption and low-voltage operation, all transistors are designed to operate in subthreshold region. By proper design of the circuit, DIBL effect is also compensated to enhance temperature coefficient of the circuit and line sensitivity. The proposed circuit consists of only four different transistors (i.e. thick oxide, native V_TH, medium V_TH) in a self-biased scheme such that eliminates the need for any start-up circuit. A prototype of the proposed circuit that generates a 341-mV voltage reference is designed and simulated in a standard 0.18-µm CMOS technology. The proposed reference circuit exhibits an average temperature coefficient of 7.6 ppm/°C across all process corners while the total power consumption is as low as 249 picowatt. The average line sensitivity of the circuit is 0.029 %/V within a wide supply range of 0.6 to 3.3 V. Ultra-low power consumption and line sensitivity, and excellent thermal stability render it ideal for integration into RFID and IoT applications.

本文介绍了一种具有皮瓦功耗的 4 晶体管亚 1 伏电压基准。为了实现超低功耗和低压工作，所有晶体管都设计为在亚阈值区工作。通过适当的电路设计，DIBL 效应也得到了补偿，从而提高了电路的温度系数和线路灵敏度。拟议电路仅由四个不同的晶体管（即厚氧化物、原生 VTH、中等 VTH）组成，采用自偏压方案，因此无需任何启动电路。在标准 0.18µm CMOS 技术中设计并模拟了可产生 341-mV 电压基准的原型电路。所提出的基准电路在所有工艺角上的平均温度系数为 7.6 ppm/°C，而总功耗却低至 249 皮瓦。在 0.6 至 3.3 V 的宽电源范围内，电路的平均线路灵敏度为 0.029 %/V。超低功耗、线路灵敏度和出色的热稳定性使其非常适合集成到 RFID 和物联网应用中。

{"title":"A simple picowatt 7.6 ppm/°C, 0.029 %/V line sensitivity fully-CMOS voltage reference with DIBL cancelation","authors":"Ali Esmailpoor, Emad Ebrahimi","doi":"10.1016/j.aeue.2024.155558","DOIUrl":"10.1016/j.aeue.2024.155558","url":null,"abstract":"<div><div>In this paper, a 4-transistor sub-one-volt voltage reference with picowatt power consumption is presented. To achieve ultra-low power consumption and low-voltage operation, all transistors are designed to operate in subthreshold region. By proper design of the circuit, DIBL effect is also compensated to enhance temperature coefficient of the circuit and line sensitivity. The proposed circuit consists of only four different transistors (i.e. thick oxide, native V<sub>TH</sub>, medium V<sub>TH</sub>) in a self-biased scheme such that eliminates the need for any start-up circuit. A prototype of the proposed circuit that generates a 341-mV voltage reference is designed and simulated in a standard 0.18-µm CMOS technology. The proposed reference circuit exhibits an average temperature coefficient of 7.6 ppm/°C across all process corners while the total power consumption is as low as 249 picowatt. The average line sensitivity of the circuit is 0.029 %/V within a wide supply range of 0.6 to 3.3 V. Ultra-low power consumption and line sensitivity, and excellent thermal stability render it ideal for integration into RFID and IoT applications.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"187 ","pages":"Article 155558"},"PeriodicalIF":3.0,"publicationDate":"2024-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reconfigurable dielectric resonator antenna and array with frequency and polarization flexibility 具有频率和极化灵活性的可重构介质谐振器天线和阵列

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-11 DOI: 10.1016/j.aeue.2024.155549

Haoran Xing , Chaoyi Ma , Yue Wu , Mengjun Wang , Chao Fan , Hongxing Zheng , Erping Li

To implement frequency and polarization hybrid reconfiguration, a 4 × 4 array has been investigated. The radiation elements of the antenna array consist of cylindrical dielectric resonators, Wilkinson power divider, PIN diode, and dielectric substrate. The PIN diode controls the states of each branch in the Wilkinson power divider to achieve frequency and polarization reconfigurability. To verify the feasibility of the design, a fabricated sample of the proposed antenna array has been measured. The results demonstrate that the antenna array can be switched freely between its operating frequencies and polarizations. It operates within a bandwidth of 1.93 to 4.6 GHz for frequency reconfiguration, and three common polarization states—linear polarization, left-handed circular polarization, and right-handed circular polarization—can be continuously tuned from 2.96 to 3.39 GHz.

为了实现频率和极化混合重配置，研究人员对 4 × 4 阵列进行了研究。天线阵列的辐射元件由圆柱形介质谐振器、威尔金森功率分压器、PIN 二极管和介质基板组成。PIN 二极管控制威尔金森功率分配器中每个分支的状态，以实现频率和极化的可重构性。为了验证设计的可行性，我们测量了所建议的天线阵列的制造样品。结果表明，天线阵列可以在工作频率和极化之间自由切换。它可在 1.93 至 4.6 千兆赫的带宽内进行频率重配置，并可在 2.96 至 3.39 千兆赫范围内连续调谐线性极化、左手圆极化和右手圆极化三种常见极化状态。

引用次数: 0

A FinFET Based Low-Power Write Enhanced SRAM Cell With Improved Stability 基于 FinFET 的低功耗写入增强型 SRAM 单元，具有更高的稳定性

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-11 DOI: 10.1016/j.aeue.2024.155556

Atharv Sharma , Kulbhushan Sharma , V.K. Tomar , Ashish Sachdeva

This work introduces a FinFet based low-power 11T SRAM cell with write enhanced feature, which is considered to meet modern technology requirements due to its distinctive features and performance. The proposed 11T SRAM cell is designed in such a way, so that it reduces the overall power consumption, improving access time, and static noise margin (SNM), especially during the write operation. The proposed 11T SRAM cell is compared with other SRAM cells, including conventional 6T (conv6T), dual pull-up transistor 10T (DPUT10T), dual pull-down transistor 10T (DPDT10T), dual transmission gate 9T (DTG9T), and dual transmission gate 10T (DTG10T), at an equitable standard. The results obtained at the supply voltage of 0.5 V @ 27 °C shows the reduction in leakage power during hold 1 operation by 1.61

\times

/1.33

\times

/1.44

\times

/1.63

\times

/1.46

\times

, and reduction in power consumption during read operation by 1.02

\times

/1.55

\times

/ 1.01

\times

/1.81

\times

/1.97

\times

in comparison with conv6T/DPUT10T/ DPDT10T/DTG9T/DTG10T, respectively. Write access time is also improved by a factor of 1.67

\times

/1.71

\times

/2.59

\times

/1.45

\times

/1.97

\times

, respectively. Additionally, read static noise margin (RSNM) and write static noise margin (WSNM) are improved by 2.03

\times

/1.01

\times

/1.65

\times

/1.54

\times

/1.43

\times

, and 1.42

\times

/1.33

\times

/1.41

\times

/1.02

\times

/1.62

\times

, respectively. This demonstrates why the proposed low-power 11T SRAM cell is desirable, especially when compared to the other cells under consideration.

本作品介绍了一种基于 FinFet 的低功耗 11T SRAM 单元，该单元具有写入增强功能，因其独特的特性和性能而被认为符合现代技术要求。所提出的 11T SRAM 单元的设计方式降低了整体功耗，改善了存取时间和静态噪声裕量（SNM），尤其是在写操作期间。在同等标准下，将所提出的 11T SRAM 单元与其他 SRAM 单元进行了比较，包括传统 6T (conv6T)、双上拉晶体管 10T (DPUT10T)、双下拉晶体管 10T (DPDT10T)、双传输门 9T (DTG9T) 和双传输门 10T (DTG10T)。与 conv6T/DPUT10T/ DPDT10T/DTG9T/DTG10T 相比，在 0.5 V @ 27 °C 的电源电压下获得的结果显示，保持 1 操作期间的漏电功率降低了 1.61×/1.33×/1.44×/1.63×/1.46×，读操作期间的功耗降低了 1.02×/1.55×/1.01×/1.81×/1.97×。写入访问时间也分别缩短了 1.67×/1.71×/2.59×/1.45×/1.97× 倍。此外，读静态噪声裕量（RSNM）和写静态噪声裕量（WSNM）分别提高了 2.03×/1.01×/1.65×/1.54×/1.43× 和 1.42×/1.33×/1.41×/1.02×/1.62×。这说明了为什么所提出的低功耗 11T SRAM 单元是可取的，尤其是与所考虑的其他单元相比。

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引用次数: 0

An 11 nW, ＋0.34 °C/−0.38 °C inaccuracy self-biased CMOS temperature sensor at sub-thermal drain voltage 一种 11 nW、＋0.34 °C/-0.38 °C、精度为亚热漏极电压的自偏压 CMOS 温度传感器

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-10 DOI: 10.1016/j.aeue.2024.155554

Bincheng Lei, Yanhan Zeng

This paper presents a low-power, high-accuracy self-biased full CMOS temperature sensor based on sub-threshold currents at sub-thermal drain voltage. The sensor achieves high accuracy and minimal corner dependence by generating sub-threshold current ratios using NMOS transistors of different sizes operating at sub-thermal drain voltage. The proposed self-biased all-CMOS temperature sensing architecture enhances sensitivity by up to seven times and improves linearity. The overall stability under temperature fluctuations is significantly enhanced by utilizing a substrate diode structure that maintains constant current variation. Additionally, a high-threshold comparator with a fast response compresses the oscillator reset voltage difference, enabling ultra-low power operation. Timing logic control is employed to discard unstable cycle outputs, thereby reducing errors and achieving high-accuracy outputs. Operating at 1 V, the circuit consumes only 11 nW at 27 °C in a 180 nm CMOS process. It achieves a peak-to-peak inaccuracy of ＋0.34 °C/−0.38 °C from −10 to 100 °C after two-point calibration, with a resolution of 40 mK and a resolution FoM as low as 3.7

pJ K^{2}

.

本文介绍了一种基于亚热漏极电压下亚阈值电流的低功耗、高精度自偏压全 CMOS 温度传感器。该传感器利用不同尺寸的 NMOS 晶体管在热漏极下电压下工作时产生的亚阈值电流比，实现了高精度和最小角依赖性。所提出的自偏压全 CMOS 温度传感架构将灵敏度提高了七倍，并改善了线性度。通过采用能保持恒定电流变化的基底二极管结构，温度波动下的整体稳定性显著增强。此外，快速响应的高阈值比较器可压缩振荡器复位电压差，从而实现超低功耗运行。定时逻辑控制用于摒弃不稳定的周期输出，从而减少误差并实现高精度输出。电路工作电压为 1 V，在 27 °C、180 纳米 CMOS 工艺条件下功耗仅为 11 nW。经过两点校准后，它在 -10 至 100 °C 范围内的峰峰误差为＋0.34 °C/-0.38 °C，分辨率为 40 mK，分辨率 FoM 低至 3.7 pJK2。

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引用次数: 0

Impact of hardware impairments and BS antenna tilt on 3D drone localization and tracking 硬件损伤和 BS 天线倾斜对 3D 无人机定位和跟踪的影响

IF 3 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2024-10-09 DOI: 10.1016/j.aeue.2024.155543

Mehari Meles, Akash Rajasekaran, Estifanos Yohannes Menta, Lauri Mela, Riku Jäntti

Today, GPS-free drone localization is increasingly gaining attention in various applications, but it faces significant accuracy challenges in three-dimensional (3D) space due to various impairments. This study investigates the effects of carrier frequency offset (CFO), phase noise (PN), and down-tilted base station (BS) antennas on drone positioning and tracking. Additionally, we explore the impact of inter-site distance (ISD) and BS density on drone position estimation accuracy. In our methodology, we consider a flying drone equipped with a single transmission antenna and BSs configured with 4 × 4 antennas under specific impairments. We first analyze the effects of these impairments on the signal’s covariance matrix. Then, using the MUSIC algorithm, we estimate the azimuth and elevation angles, which serve as the basis for drone localization using the Least Squares (LS) method across all BSs. Finally, the estimated positions feed into an Extended Kalman Filter (EKF) for tracking. Our results present a sequential analysis of the impact of all impairments on the off-diagonal covariance matrix, on the Angle of Arrival (AOA) estimation and 3D drone localization. We use simulations to demonstrate how hardware impairments affect 3D drone localization accuracy under varying ISD and BS densities.

如今，无 GPS 无人机定位在各种应用中日益受到关注，但由于各种干扰，它在三维（3D）空间中面临着巨大的精度挑战。本研究探讨了载波频率偏移（CFO）、相位噪声（PN）和下倾基站（BS）天线对无人机定位和跟踪的影响。此外，我们还探讨了站点间距离（ISD）和基站密度对无人机位置估计精度的影响。在我们的研究方法中，我们考虑了在特定干扰条件下，无人机配备单根发射天线和配置 4 × 4 天线的 BS。我们首先分析了这些干扰对信号协方差矩阵的影响。然后，我们使用 MUSIC 算法估计方位角和仰角，并以此为基础，使用最小二乘法（LS）对所有 BS 进行无人机定位。最后，估算出的位置进入扩展卡尔曼滤波器（EKF）进行跟踪。我们的研究结果按顺序分析了所有损伤对非对角线协方差矩阵、到达角（AOA）估计和 3D 无人机定位的影响。我们利用仿真演示了在不同的 ISD 和 BS 密度下，硬件损伤对 3D 无人机定位精度的影响。

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引用次数: 0