Aeu-International Journal of Electronics and Communications最新文献_第3页

A dual-source energy harvester for battery-less agricultural IoT-sensor networks 用于无电池农业物联网传感器网络的双源能量采集器

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-02-04 DOI: 10.1016/j.aeue.2026.156243

Satendra Pathak , D. Venkata Sai Reddy , Anil Kumar Gautam , Tushar Goel

A dual-source Solar-RF Energy Harvesting (DS-S-RFEH) system is designed and developed to offer battery-free power solutions for IoT-based sensor networks in agricultural applications. This article demonstrates a transparent, omnidirectional antenna-based Radio Frequency Energy harvesting system (RF-EHS) designed to be integrated onto a thin-film solar panel. The suggested technique enables battery-free operation of low-power electronic devices and sensors by concurrently converting renewable solar and RF radiation into usable DC power, for ensuring continuous, round-the-clock operation across diverse application domains. The RF-EHS consists of a single diode rectifier circuit (SDRC) featuring an SMS7630 Schottky diode, an omnidirectional fractal antenna that supports LTE, WLAN/Wi-Fi, and Bluetooth frequency bands, and a matching network that couples the rectifier circuit and receiving antenna to match their impedances for maximum power transmission. The performance of the proposed system was evaluated, and the simulated outcomes were physically verified using FR-4 and ITO-coated PET+ acrylic as transparent and opaque substrate materials. The system produces an average peak voltage of 1.15 V and a matching DC power rating of 0.58 mW at 10 dBm input power, resulting in an RF–DC conversion efficiency greater than 67%, according to the results of the experiment. For the FR-4 and ITO-coated PET substrates, the suggested receiving antennas show achieved gains of 4.82 dBi and 5.02 dBi, respectively. The ITO-coated PET substrate provides over 75% optical transparency and flexibility, which allows for smooth integration into thin-film solar panels without losing their photovoltaic efficiency, according to experimental results.

设计和开发的双源太阳能-射频能量收集（DS-S-RFEH）系统为农业应用中基于物联网的传感器网络提供无电池电源解决方案。本文演示了一种透明的、基于全向天线的射频能量收集系统（RF-EHS），该系统旨在集成到薄膜太阳能电池板上。建议的技术通过将可再生太阳能和射频辐射同时转换为可用的直流电源，实现低功耗电子设备和传感器的无电池运行，以确保在不同应用领域连续、全天候运行。RF-EHS由一个采用SMS7630肖特基二极管的单二极管整流电路（SDRC）、一个支持LTE、WLAN/Wi-Fi和蓝牙频段的全向分形天线和一个匹配网络组成，该匹配网络将整流电路和接收天线耦合起来，以匹配其阻抗以实现最大功率传输。采用FR-4和ito涂层PET+丙烯酸作为透明基材和不透明基材，对所提出系统的性能进行了评估，并对模拟结果进行了物理验证。实验结果表明，在输入功率为10 dBm时，系统产生的平均峰值电压为1.15 V，匹配的直流额定功率为0.58 mW， RF-DC转换效率大于67%。对于FR-4和ito涂层PET基板，建议的接收天线分别获得4.82 dBi和5.02 dBi增益。根据实验结果，ito涂层的PET基板提供了超过75%的光学透明度和灵活性，可以在不损失光伏效率的情况下顺利集成到薄膜太阳能电池板中。

{"title":"A dual-source energy harvester for battery-less agricultural IoT-sensor networks","authors":"Satendra Pathak , D. Venkata Sai Reddy , Anil Kumar Gautam , Tushar Goel","doi":"10.1016/j.aeue.2026.156243","DOIUrl":"10.1016/j.aeue.2026.156243","url":null,"abstract":"<div><div>A dual-source Solar-RF Energy Harvesting (DS-S-RFEH) system is designed and developed to offer battery-free power solutions for IoT-based sensor networks in agricultural applications. This article demonstrates a transparent, omnidirectional antenna-based Radio Frequency Energy harvesting system (RF-EHS) designed to be integrated onto a thin-film solar panel. The suggested technique enables battery-free operation of low-power electronic devices and sensors by concurrently converting renewable solar and RF radiation into usable DC power, for ensuring continuous, round-the-clock operation across diverse application domains. The RF-EHS consists of a single diode rectifier circuit (SDRC) featuring an SMS7630 Schottky diode, an omnidirectional fractal antenna that supports LTE, WLAN/Wi-Fi, and Bluetooth frequency bands, and a matching network that couples the rectifier circuit and receiving antenna to match their impedances for maximum power transmission. The performance of the proposed system was evaluated, and the simulated outcomes were physically verified using FR-4 and ITO-coated PET+ acrylic as transparent and opaque substrate materials. The system produces an average peak voltage of 1.15 V and a matching DC power rating of 0.58 mW at 10 dBm input power, resulting in an RF–DC conversion efficiency greater than 67%, according to the results of the experiment. For the FR-4 and ITO-coated PET substrates, the suggested receiving antennas show achieved gains of 4.82 dBi and 5.02 dBi, respectively. The ITO-coated PET substrate provides over 75% optical transparency and flexibility, which allows for smooth integration into thin-film solar panels without losing their photovoltaic efficiency, according to experimental results.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"208 ","pages":"Article 156243"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146192925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A survey on analog memristor emulators and their applications 模拟忆阻器仿真器及其应用综述

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-24 DOI: 10.1016/j.aeue.2026.156223

Fayrouz Shaheen, Eman Azab, Amr Hassan

This paper provides a comprehensive review of analog memristor emulators (Memulators), starting with the theoretical foundation of memristors, historical development, and their physical structures. It then investigates their design methodologies and operational principles in various circuit topologies, encompassing both MOS-based and Active Building Block (ABB)-based designs, which are critically examined, highlighting their unique characteristics, performance trade-offs (including power consumption, layout area, and maximum operating frequency), and inherent design considerations. Addressing the lack of standardisation in the field, a concrete, minimal benchmark suite is proposed, specifying test signals and robustness tests to ensure reproducible characterisation. A detailed comparative analysis of recent analog memulator circuits is presented, employing a defined Figure of Merit (FoM) and introducing a novel framework of qualitative comparison tables. Unlike traditional performance listings, this framework meticulously evaluates designs based on validation rigour (distinguishing simulation from experimental silicon), architectural versatility, and electronic tunability, providing a systematic metric for practical deployment readiness. Furthermore, a critical analysis of implementation challenges — including sneak paths, device variability, and forming-free operation — synthesises how different topologies mitigate these issues. Key case studies of fabricated memulator designs are also highlighted, illustrating practical realisation and system-level application. The paper further explores a wide range of applications, with particular emphasis on neuromorphic computing and chaotic oscillators for secure communications, demonstrating their practical significance in modern electronics. Finally, recent advancements and innovations from the literature are summarised, alongside a thorough discussion of prevailing research trends and promising future research directions aimed at overcoming existing limitations and unlocking new capabilities.

本文从忆阻器的理论基础、历史发展和物理结构等方面对模拟忆阻器仿真器（Memulators）进行了全面的综述。然后，研究他们在各种电路拓扑中的设计方法和工作原理，包括基于mos和基于主动构建块（ABB）的设计，这些设计经过严格检查，突出其独特的特性，性能权衡（包括功耗，布局面积和最大工作频率），以及固有的设计考虑。为了解决该领域缺乏标准化的问题，提出了一个具体的、最小的基准套件，指定测试信号和鲁棒性测试，以确保可再现的特征。本文采用定义的优值图（FoM），并引入一种新的定性比较表框架，对最近的模拟模制器电路进行了详细的比较分析。与传统的性能清单不同，该框架根据验证的严谨性（将模拟与实验硅区分开来）、架构的通用性和电子可调性精心评估设计，为实际部署准备提供了系统的度量。此外，对实现挑战（包括潜行路径、设备可变性和无成形操作）进行了批判性分析，综合了不同拓扑结构如何缓解这些问题。本文还重点介绍了装配式memator设计的关键案例研究，说明了实际实现和系统级应用。本文进一步探讨了广泛的应用，特别强调了神经形态计算和混沌振荡器在安全通信中的应用，展示了它们在现代电子学中的实际意义。最后，总结了文献中的最新进展和创新，并深入讨论了当前的研究趋势和有希望的未来研究方向，旨在克服现有的限制和释放新的能力。

{"title":"A survey on analog memristor emulators and their applications","authors":"Fayrouz Shaheen, Eman Azab, Amr Hassan","doi":"10.1016/j.aeue.2026.156223","DOIUrl":"10.1016/j.aeue.2026.156223","url":null,"abstract":"<div><div>This paper provides a comprehensive review of analog memristor emulators (Memulators), starting with the theoretical foundation of memristors, historical development, and their physical structures. It then investigates their design methodologies and operational principles in various circuit topologies, encompassing both MOS-based and Active Building Block (ABB)-based designs, which are critically examined, highlighting their unique characteristics, performance trade-offs (including power consumption, layout area, and maximum operating frequency), and inherent design considerations. Addressing the lack of standardisation in the field, a concrete, minimal benchmark suite is proposed, specifying test signals and robustness tests to ensure reproducible characterisation. A detailed comparative analysis of recent analog memulator circuits is presented, employing a defined Figure of Merit (FoM) and introducing a novel framework of qualitative comparison tables. Unlike traditional performance listings, this framework meticulously evaluates designs based on validation rigour (distinguishing simulation from experimental silicon), architectural versatility, and electronic tunability, providing a systematic metric for practical deployment readiness. Furthermore, a critical analysis of implementation challenges — including sneak paths, device variability, and forming-free operation — synthesises how different topologies mitigate these issues. Key case studies of fabricated memulator designs are also highlighted, illustrating practical realisation and system-level application. The paper further explores a wide range of applications, with particular emphasis on neuromorphic computing and chaotic oscillators for secure communications, demonstrating their practical significance in modern electronics. Finally, recent advancements and innovations from the literature are summarised, alongside a thorough discussion of prevailing research trends and promising future research directions aimed at overcoming existing limitations and unlocking new capabilities.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156223"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Soft-constrained reinforcement learning for antenna optimization with feasibility prescreening 可行性预筛选天线优化的软约束强化学习

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-27 DOI: 10.1016/j.aeue.2026.156235

Bingjie Zhang , Qiao Chen , Yifan Yin , Hongxin Zhao , Qipeng Wang , Peng Liu , Xiaoxing Yin , Shunli Li

This work proposes a soft-constrained reinforcement learning (SC-RL) framework integrating feasibility prescreening and trust region mechanisms to address physical constraints in high-dimensional parameter space. By embedding penalty rules into the reward function, the framework transforms physical constraints into learnable optimization signals while leveraging proximal policy optimization (PPO) to stabilize policy updates. By establishing a unified abstraction where constraints are defined as mathematical penalty signals, the framework exhibits generalizability across varying antenna structures and radiation mechanisms. Experimental validation on a broadband antipodal linearly tapered slot antenna (ALTSA) and a wideband filtering patch antenna (FPA) demonstrates superior optimization performance and a favorable convergence rate compared to baseline methods. The ALTSA optimized by the proposed framework achieves a 21.1% impedance bandwidth, 6.90% axial ratio bandwidth, and 9.17 dBic peak gain, exceeding the original targets of 16%, 5%, and 8.8 dBic, respectively. While the optimized FPA attains a 23.1% impedance bandwidth and 9.96 dBi peak gain, surpassing its goals of 17% and 9.7 dBi. Furthermore, the convergence speed of this framework is 21.7% and 31.1% faster than standard PPO in the two cases, while outperforming traditional algorithms which are prone to either premature convergence or slower stabilization.

本研究提出了一个软约束强化学习（SC-RL）框架，该框架集成了可行性预筛选和信任域机制，以解决高维参数空间中的物理约束问题。该框架通过在奖励函数中嵌入惩罚规则，将物理约束转化为可学习的优化信号，同时利用近端策略优化（PPO）来稳定策略更新。通过建立一个统一的抽象，其中约束被定义为数学惩罚信号，该框架在不同的天线结构和辐射机制中显示出通用性。对宽带对跖线性锥形缝隙天线（ALTSA）和宽带滤波贴片天线（FPA）的实验验证表明，与基线方法相比，该方法具有优越的优化性能和良好的收敛速度。该框架优化后的ALTSA阻抗带宽为21.1%，轴比带宽为6.90%，峰值增益为9.17 dBic，分别超过了原目标的16%、5%和8.8 dBic。而优化后的FPA阻抗带宽为23.1%，峰值增益为9.96 dBi，超过了17%和9.7 dBi的目标。此外，在两种情况下，该框架的收敛速度分别比标准PPO快21.7%和31.1%，同时优于容易过早收敛或稳定较慢的传统算法。

{"title":"Soft-constrained reinforcement learning for antenna optimization with feasibility prescreening","authors":"Bingjie Zhang , Qiao Chen , Yifan Yin , Hongxin Zhao , Qipeng Wang , Peng Liu , Xiaoxing Yin , Shunli Li","doi":"10.1016/j.aeue.2026.156235","DOIUrl":"10.1016/j.aeue.2026.156235","url":null,"abstract":"<div><div>This work proposes a soft-constrained reinforcement learning (SC-RL) framework integrating feasibility prescreening and trust region mechanisms to address physical constraints in high-dimensional parameter space. By embedding penalty rules into the reward function, the framework transforms physical constraints into learnable optimization signals while leveraging proximal policy optimization (PPO) to stabilize policy updates. By establishing a unified abstraction where constraints are defined as mathematical penalty signals, the framework exhibits generalizability across varying antenna structures and radiation mechanisms. Experimental validation on a broadband antipodal linearly tapered slot antenna (ALTSA) and a wideband filtering patch antenna (FPA) demonstrates superior optimization performance and a favorable convergence rate compared to baseline methods. The ALTSA optimized by the proposed framework achieves a 21.1% impedance bandwidth, 6.90% axial ratio bandwidth, and 9.17 dBic peak gain, exceeding the original targets of 16%, 5%, and 8.8 dBic, respectively. While the optimized FPA attains a 23.1% impedance bandwidth and 9.96 dBi peak gain, surpassing its goals of 17% and 9.7 dBi. Furthermore, the convergence speed of this framework is 21.7% and 31.1% faster than standard PPO in the two cases, while outperforming traditional algorithms which are prone to either premature convergence or slower stabilization.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156235"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multi-task neural metamodel and NSGA-II for ultra-low-power OTA design in tunable vowel filters 基于多任务神经元模型和NSGA-II的可调元音滤波器超低功耗OTA设计

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-02-02 DOI: 10.1016/j.aeue.2026.156241

Savvas Karipidis , Julia Nako , Andi Buzo , Georg Pelz , Costas Psychalinos , Thomas Noulis

This work presents a complete deep-learning-driven automation flow for designing ultra-low-power subthreshold operational transconductance amplifiers used in electronically tunable gm-C resonator and anti-resonator circuits for speech vowel processing. A multi-task learning neural network is trained as an accurate and extremely fast metamodel (surrogate) of an 8-parameter operational transconductance amplifier topology in 350 nm CMOS process node. Using only 60000 Latin-hypercube-sampled circuit simulations for training, the metamodel predicts DC power consumption, total transistor area, and DC transconductance with average errors of 2.9%, 5.0%, and 7.3%, respectively. The trained model is then coupled with the NSGA-II multi-objective genetic algorithm to instantly generate Pareto-optimal trade-offs between power and area for any designer-specified gm value in the 45–55 nA/V range typical of vowel formant filters. Compared to conventional simulation-in-the-loop NSGA-II optimization, the proposed flow reduces the total design time from 25 h to 7 h, a 3.5 times speedup, and against the standard human design methodology, the acceleration is higher than 20 times. The methodology enables on-the-fly power/area optimization of all operational transconductance amplifiers in sixth-order tunable vowel filters without need for re-design.

这项工作提出了一个完整的深度学习驱动的自动化流程，用于设计用于语音元音处理的电子可调谐gm-C谐振器和反谐振器电路的超低功耗亚阈值操作跨导放大器。采用多任务学习神经网络作为350 nm CMOS工艺节点8参数运算跨导放大器拓扑结构的精确、快速元模型（代理）进行训练。仅使用60000个拉丁超立方体采样电路模拟进行训练，该元模型预测直流功耗、晶体管总面积和直流跨导的平均误差分别为2.9%、5.0%和7.3%。然后，将训练好的模型与NSGA-II多目标遗传算法相结合，在45-55 nA/V的元音形成峰滤波器的典型范围内，针对任何设计者指定的gm值，立即生成功率和面积之间的帕累托最优权衡。与传统的环中仿真NSGA-II优化相比，所提出的流程将总设计时间从25小时缩短到7小时，加速了3.5倍，与标准的人类设计方法相比，加速超过了20倍。该方法可以实时优化六阶可调元音滤波器中所有操作跨导放大器的功率/面积，而无需重新设计。

{"title":"Multi-task neural metamodel and NSGA-II for ultra-low-power OTA design in tunable vowel filters","authors":"Savvas Karipidis , Julia Nako , Andi Buzo , Georg Pelz , Costas Psychalinos , Thomas Noulis","doi":"10.1016/j.aeue.2026.156241","DOIUrl":"10.1016/j.aeue.2026.156241","url":null,"abstract":"<div><div>This work presents a complete deep-learning-driven automation flow for designing ultra-low-power subthreshold operational transconductance amplifiers used in electronically tunable gm-C resonator and anti-resonator circuits for speech vowel processing. A multi-task learning neural network is trained as an accurate and extremely fast metamodel (surrogate) of an 8-parameter operational transconductance amplifier topology in 350 nm CMOS process node. Using only 60000 Latin-hypercube-sampled circuit simulations for training, the metamodel predicts DC power consumption, total transistor area, and DC transconductance with average errors of 2.9%, 5.0%, and 7.3%, respectively. The trained model is then coupled with the NSGA-II multi-objective genetic algorithm to instantly generate Pareto-optimal trade-offs between power and area for any designer-specified gm value in the 45–55 nA/V range typical of vowel formant filters. Compared to conventional simulation-in-the-loop NSGA-II optimization, the proposed flow reduces the total design time from 25 h to 7 h, a 3.5 times speedup, and against the standard human design methodology, the acceleration is higher than 20 times. The methodology enables on-the-fly power/area optimization of all operational transconductance amplifiers in sixth-order tunable vowel filters without need for re-design.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156241"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147398921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Elliptical shape microstrip antennas loaded with plus shape slot for compact and wideband circular polarized response 椭圆微带天线加载正形槽以获得紧凑的宽带圆极化响应

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-31 DOI: 10.1016/j.aeue.2026.156239

Amit A. Deshmukh , Devika Panicker , Aarya Gaonkar , Venkata A.P. Chavali

Compact design of Elliptical shape microstrip antenna embedded with plus shape slot is presented for circular polarized response. Attributed to the reduction in orthogonal mode frequencies, slot cut elliptical patch yields circular polarized response in a lower frequency band. It yields axial ratio and reflection coefficient bandwidth of 92 MHz (6.27%) and 1002 MHz (60.1%), respectively, with 128 MHz (8.04%) reduction in the center frequency of axial ratio bandwidth. Similar design employing plus shape slot on the ground plane is proposed. This design yields axial ratio and reflection coefficient bandwidth of 46 MHz (3.27%) and 720 MHz (49.04%), respectively, and offers reduction in the center frequency of axial ratio bandwidth by 189 MHz (11.87%). Thus, slot on the ground plane achieves more frequency reduction and thus a more compact solution. Next, slot cut technique is extended to the wideband gap-coupled configuration. Multi-resonator plus shape slot cut elliptical patch design yields axial ratio bandwidth of 243 MHz (27.01%), and offers 86 MHz (8.73%) reduction in the center frequency of axial ratio bandwidth, thereby providing a compact wideband design. Resonant length formulation for the ground plane slot cut antenna and subsequent design methodology to realize reconfigurable compact dual band stub loaded elliptical patch design that addresses to GPS L3 and L2, L5 bands, is presented. Thus, proposed work not just presents a slot cut circular polarized configuration, but puts forward a technique that achieves reduction in the center frequency of axial ratio bandwidth and an equivalent patch area reduction.

针对圆极化响应，提出了一种嵌入正形槽的椭圆微带天线的紧凑设计。由于正交模频率的降低，槽切椭圆贴片在较低频段产生圆极化响应。轴比和反射系数带宽分别为92 MHz（6.27%）和1002 MHz(60.1%)，轴比带宽中心频率降低128 MHz（8.04%）。提出了类似的设计，在接地面上采用正形槽。该设计的轴比带宽和反射系数带宽分别为46 MHz（3.27%）和720 MHz(49.04%)，轴比带宽中心频率降低189 MHz（11.87%）。因此，地平面上的插槽实现了更多的频率降低，从而更紧凑的解决方案。然后，将狭缝切割技术扩展到宽带隙耦合结构。多谐振器加形状槽切椭圆贴片设计的轴比带宽为243 MHz(27.01%)，轴比带宽中心频率降低86 MHz(8.73%)，从而提供了紧凑的宽带设计。提出了地平面槽切天线的谐振长度公式，以及实现GPS L3、L2、L5频段可重构紧凑双频短段加载椭圆贴片设计的设计方法。因此，本文不仅提出了一种狭缝切割的圆极化结构，而且提出了一种降低轴比带宽中心频率和等效贴片面积的技术。

{"title":"Elliptical shape microstrip antennas loaded with plus shape slot for compact and wideband circular polarized response","authors":"Amit A. Deshmukh , Devika Panicker , Aarya Gaonkar , Venkata A.P. Chavali","doi":"10.1016/j.aeue.2026.156239","DOIUrl":"10.1016/j.aeue.2026.156239","url":null,"abstract":"<div><div>Compact design of Elliptical shape microstrip antenna embedded with plus shape slot is presented for circular polarized response. Attributed to the reduction in orthogonal mode frequencies, slot cut elliptical patch yields circular polarized response in a lower frequency band. It yields axial ratio and reflection coefficient bandwidth of 92 MHz (6.27%) and 1002 MHz (60.1%), respectively, with 128 MHz (8.04%) reduction in the center frequency of axial ratio bandwidth. Similar design employing plus shape slot on the ground plane is proposed. This design yields axial ratio and reflection coefficient bandwidth of 46 MHz (3.27%) and 720 MHz (49.04%), respectively, and offers reduction in the center frequency of axial ratio bandwidth by 189 MHz (11.87%). Thus, slot on the ground plane achieves more frequency reduction and thus a more compact solution. Next, slot cut technique is extended to the wideband gap-coupled configuration. Multi-resonator plus shape slot cut elliptical patch design yields axial ratio bandwidth of 243 MHz (27.01%), and offers 86 MHz (8.73%) reduction in the center frequency of axial ratio bandwidth, thereby providing a compact wideband design. Resonant length formulation for the ground plane slot cut antenna and subsequent design methodology to realize reconfigurable compact dual band stub loaded elliptical patch design that addresses to GPS L3 and L2, L5 bands, is presented. Thus, proposed work not just presents a slot cut circular polarized configuration, but puts forward a technique that achieves reduction in the center frequency of axial ratio bandwidth and an equivalent patch area reduction.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156239"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147398923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Corrigendum to “Design of SFMSIW MIMO antenna with low mutual coupling using notch filter” [AEU - Int. J. Electron. Commun. 201 (2025) 155968] 《利用陷波滤波器设计低互耦SFMSIW MIMO天线》的勘误表[AEU - Int]。j .电子。common . 201 (2025) 155968]

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-02-08 DOI: 10.1016/j.aeue.2026.156245

Mansour H. Almalki , Mohammad Awedh , Mohammed N. Ajour , Avez Syed

引用次数: 0

A fully-integrated GaAs MMIC ultra-broadband distributed efficient power amplifier chip with 107% fractional bandwidth 具有107%分数带宽的全集成GaAs MMIC超宽带分布式高效功率放大器芯片

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-02-06 DOI: 10.1016/j.aeue.2026.156249

Zhuoyin Chen, Yongle Wu, Xiaopan Chen, Wei Zhao, Shuchen Zhen, Weimin Wang

This paper proposes a novel compact ultra-broadband distributed efficient power amplifier (BDEPA) structure in a GaAs pHEMT process. Conventional distributed efficient power amplifiers (DEPAs) are often limited in bandwidth by their input power splitting and phase-shifting networks. To overcome this limitation, the proposed architecture introduces an (N+1) section fully-distributed input matching network (FDIMN), which replaces the conventional input network to significantly extend the operational bandwidth while maintaining high power back-off (PBO) efficiency. To validate the proposed concept, a monolithic microwave integrated circuit (MMIC) was fabricated and measured. The measurement results demonstrate a state-of-the-art fractional bandwidth of 107% from 3.5 to 11.5 GHz. Across this band, the BDEPA delivers a saturated output power of 21.5–24.0 dBm with a corresponding drain efficiency (DE) of 28.3–39.1%. At a 6-dB PBO, the DE remains high at 23.1–33.9%. Under a 100-MHz 64-QAM modulated signal, the PA achieves an average output power of 16.5/15.5 dBm and −32.3/-31.4 dBc ACLR at 5/10 GHz in −25 dB EVM level. The entire chip occupies a compact area of 3.2 mm

^{2}

.

提出了一种新型的GaAs pHEMT超宽带分布式高效功率放大器结构。传统的分布式高效功率放大器（depa）由于其输入分频和移相网络而受到带宽限制。为了克服这一限制，所提出的架构引入了一个（N+1）分段全分布式输入匹配网络（FDIMN），它取代了传统的输入网络，在保持高功率回退（PBO）效率的同时显着扩展了操作带宽。为了验证提出的概念，制作了一个单片微波集成电路（MMIC）并进行了测量。测量结果表明，在3.5至11.5 GHz范围内，最先进的分数带宽为107%。在该频段内，BDEPA的饱和输出功率为21.5-24.0 dBm，相应的漏极效率（DE）为28.3-39.1%。在6 db PBO下，DE保持在23.1-33.9%的高位。在100mhz 64-QAM调制信号下，在5/10 GHz、−25 dB EVM电平下，平均输出功率为16.5/15.5 dBm， ACLR为- 32.3/-31.4 dBc。整个芯片占地3.2平方毫米的紧凑面积。

{"title":"A fully-integrated GaAs MMIC ultra-broadband distributed efficient power amplifier chip with 107% fractional bandwidth","authors":"Zhuoyin Chen, Yongle Wu, Xiaopan Chen, Wei Zhao, Shuchen Zhen, Weimin Wang","doi":"10.1016/j.aeue.2026.156249","DOIUrl":"10.1016/j.aeue.2026.156249","url":null,"abstract":"<div><div>This paper proposes a novel compact ultra-broadband distributed efficient power amplifier (BDEPA) structure in a GaAs pHEMT process. Conventional distributed efficient power amplifiers (DEPAs) are often limited in bandwidth by their input power splitting and phase-shifting networks. To overcome this limitation, the proposed architecture introduces an (N+1) section fully-distributed input matching network (FDIMN), which replaces the conventional input network to significantly extend the operational bandwidth while maintaining high power back-off (PBO) efficiency. To validate the proposed concept, a monolithic microwave integrated circuit (MMIC) was fabricated and measured. The measurement results demonstrate a state-of-the-art fractional bandwidth of 107% from 3.5 to 11.5 GHz. Across this band, the BDEPA delivers a saturated output power of 21.5–24.0 dBm with a corresponding drain efficiency (DE) of 28.3–39.1%. At a 6-dB PBO, the DE remains high at 23.1–33.9%. Under a 100-MHz 64-QAM modulated signal, the PA achieves an average output power of 16.5/15.5 dBm and −32.3/-31.4 dBc ACLR at 5/10 GHz in −25 dB EVM level. The entire chip occupies a compact area of 3.2 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"208 ","pages":"Article 156249"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146147573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of wideband resistive continuous class-J Doherty power amplifier with harmonic load modulation suppression 谐波负载调制抑制的宽带阻性连续j类多尔蒂功率放大器设计

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-22 DOI: 10.1016/j.aeue.2026.156226

Wa Kong, Wenya Liu, Hongyan Fu, Hui Ma, Wence Zhang, Jing Xia

This paper proposes a design method of a wideband Doherty power amplifier (DPA) using resistive continuous class-J mode with harmonic load modulation suppression, aiming to achieve high efficiency at back-off output powers (BOPs) across a wide frequency band. Firstly, based on theoretical impedance analysis of the resistive continuous class-J mode, the optimum load impedances under both saturation and BOP conditions are identified for DPA design. Then, combined with the load modulation theory, optimization objective functions are formulated for the peaking output matching networks (OMNs) design and optimization. In addition, to control the carrier second harmonic impedance during the load modulation, the peaking OMN using fragment-type matching circuit is used to suppress harmonic load modulation. For verification, a DPA operating at 2.0–3.4 GHz is designed and measured. The results show that the DPA achieves saturated output power of 43.1–44.4 dBm across the entire frequency band, with drain efficiencies of 59.1%–72% at saturation and 50%–58.9% at 6 dB BOP.

本文提出了一种采用谐波负载调制抑制的电阻连续j类模式的宽带Doherty功率放大器（DPA）的设计方法，目的是在宽频带内实现高效率的回退输出功率（BOPs）。首先，基于电阻连续j类模式的理论阻抗分析，确定了饱和和防喷工况下DPA设计的最佳负载阻抗；然后，结合负载调制理论，建立了调峰输出匹配网络的优化目标函数，用于调峰输出匹配网络的设计与优化。此外，为了控制负载调制过程中的载波二次谐波阻抗，采用分段匹配的调峰OMN抑制谐波负载调制。为了验证，设计并测量了工作在2.0-3.4 GHz的DPA。结果表明，该DPA在整个频段的饱和输出功率为43.1 ~ 44.4 dBm，饱和时漏极效率为59.1% ~ 72%，6 dB BOP时漏极效率为50% ~ 58.9%。

{"title":"Design of wideband resistive continuous class-J Doherty power amplifier with harmonic load modulation suppression","authors":"Wa Kong, Wenya Liu, Hongyan Fu, Hui Ma, Wence Zhang, Jing Xia","doi":"10.1016/j.aeue.2026.156226","DOIUrl":"10.1016/j.aeue.2026.156226","url":null,"abstract":"<div><div>This paper proposes a design method of a wideband Doherty power amplifier (DPA) using resistive continuous class-J mode with harmonic load modulation suppression, aiming to achieve high efficiency at back-off output powers (BOPs) across a wide frequency band. Firstly, based on theoretical impedance analysis of the resistive continuous class-J mode, the optimum load impedances under both saturation and BOP conditions are identified for DPA design. Then, combined with the load modulation theory, optimization objective functions are formulated for the peaking output matching networks (OMNs) design and optimization. In addition, to control the carrier second harmonic impedance during the load modulation, the peaking OMN using fragment-type matching circuit is used to suppress harmonic load modulation. For verification, a DPA operating at 2.0–3.4 GHz is designed and measured. The results show that the DPA achieves saturated output power of 43.1–44.4 dBm across the entire frequency band, with drain efficiencies of 59.1%–72% at saturation and 50%–58.9% at 6 dB BOP.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156226"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Generation of OAM beams with multiple modes with concentric spiral sub-array 同轴螺旋子阵列多模OAM波束的产生

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-27 DOI: 10.1016/j.aeue.2026.156236

Uğur Yeşilyurt, Elif Yaman

The vortex electromagnetic wave carrying orbital angular momentum (OAM) increases the spectral efficiency of communication systems. This is achieved by multiplexing the OAM waves in different modes in the same frequency channel due to their orthogonality. A concentric uniform circular array (CUCA) is generally used as a classical method for multiplexing OAM beams. However, CUCA employs a large number of phase-shifting units, which results in a complex feed network. In this paper, a concentric spiral array (CSA) is proposed, which eliminates the need for a complex feed network. CSA utilizes step height to obtain different OAM modes. To make the CSA configuration more compact to achieve high-mode OAM, a concentric spiral sub-array (CSSA) is used, which results in more uniform multiple OAM modes. Additionally, mode purity analyses of the CSA, CSSA, and rearranged CSSA configurations are carried out, and their mode purity performances are evaluated comparatively. Simulation results demonstrate that the proposed method both eliminates the need for external phase shifters and is effective in achieving high-purity OAM multiplexing at the equal divergence angle.

涡旋电磁波携带轨道角动量（OAM）提高了通信系统的频谱效率。由于正交性，这是通过在同一频率通道中以不同模式复用OAM波来实现的。同心均匀圆阵列（CUCA）是OAM波束复用的经典方法。然而，CUCA采用了大量的移相单元，导致馈电网络复杂。本文提出了一种同轴螺旋阵列（CSA），消除了复杂馈电网络的需要。CSA利用阶跃高度获得不同的OAM模式。为了使CSA结构更紧凑以实现高模OAM，采用了同心螺旋子阵列（CSSA），从而实现更均匀的多模OAM。此外，还对CSA、CSSA和重排CSSA结构进行了模式纯度分析，并对其模式纯度性能进行了比较。仿真结果表明，该方法既不需要外部移相器，又能在等发散角下实现高纯度的OAM复用。

{"title":"Generation of OAM beams with multiple modes with concentric spiral sub-array","authors":"Uğur Yeşilyurt, Elif Yaman","doi":"10.1016/j.aeue.2026.156236","DOIUrl":"10.1016/j.aeue.2026.156236","url":null,"abstract":"<div><div>The vortex electromagnetic wave carrying orbital angular momentum (OAM) increases the spectral efficiency of communication systems. This is achieved by multiplexing the OAM waves in different modes in the same frequency channel due to their orthogonality. A concentric uniform circular array (CUCA) is generally used as a classical method for multiplexing OAM beams. However, CUCA employs a large number of phase-shifting units, which results in a complex feed network. In this paper, a concentric spiral array (CSA) is proposed, which eliminates the need for a complex feed network. CSA utilizes step height to obtain different OAM modes. To make the CSA configuration more compact to achieve high-mode OAM, a concentric spiral sub-array (CSSA) is used, which results in more uniform multiple OAM modes. Additionally, mode purity analyses of the CSA, CSSA, and rearranged CSSA configurations are carried out, and their mode purity performances are evaluated comparatively. Simulation results demonstrate that the proposed method both eliminates the need for external phase shifters and is effective in achieving high-purity OAM multiplexing at the equal divergence angle.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156236"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An improved frequency compensation strategy for class AB headphone drivers 一种改进的AB类耳机驱动器频率补偿策略

IF 3.2 3区计算机科学 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

Aeu-International Journal of Electronics and Communications

Pub Date : 2026-03-01 Epub Date: 2026-01-16 DOI: 10.1016/j.aeue.2026.156217

Masoud Rostampour Koushkghazi , Hamed Aminzadeh , Abbas Kamali , Ali Emam Ghorashi

This paper presents a low-power, highly-linear three-stage Class AB headphone capable of driving a wide load capacitor (C_L) range using an advanced frequency compensation network. A local AC feedback network replaces the classical transconductor-based quality factor control, enabling to reduce the silicon area and quiescent power by implementing the intermediate stage as a simple inverting common-source amplifier. Miller capacitance is split and each portion is coupled to an embedded current buffer, thereby moving non-dominant poles to higher frequencies without requiring new gain stages or bias-dependent elements. The proposed approach combines the wide-range load driving capability and high linearity under reduced power and area, making it suitable for high-fidelity headphone drivers. Post-layout simulation results of a prototype in a standard 65-nm CMOS process demonstrate a robust operation for the capacitive loads from 0 to 22 nF, achieving more than 114 dB DC gain and a minimum phase margin of 45°. It delivers 89.9 mW peak power into a 16 Ω load while consuming 0.52 mW power in 0.22 mm² silicon area. The THD + N of full-scale output is −104.6 dB at 20 KHz.

本文介绍了一种低功耗，高线性三级AB类耳机，能够使用先进的频率补偿网络驱动宽负载电容（CL）范围。局部交流反馈网络取代了经典的基于跨导体的质量因数控制，通过将中间级实现为简单的反相共源放大器，可以减少硅面积和静态功率。米勒电容被拆分，每个部分都耦合到嵌入式电流缓冲器，从而将非主导极移动到更高的频率，而不需要新的增益级或偏置相关元件。该方法结合了宽范围负载驱动能力和低功耗和低面积下的高线性度，适用于高保真耳机驱动器。在标准65纳米CMOS工艺中，原型的布局后仿真结果表明，在0至22 nF的容性负载下，原型具有稳健的工作性能，实现了超过114 dB的直流增益和45°的最小相位裕度。它为16 Ω负载提供89.9 mW的峰值功率，同时在0.22 mm2硅面积上消耗0.52 mW的功率。在20khz时，满量程输出的THD + N为−104.6 dB。

{"title":"An improved frequency compensation strategy for class AB headphone drivers","authors":"Masoud Rostampour Koushkghazi , Hamed Aminzadeh , Abbas Kamali , Ali Emam Ghorashi","doi":"10.1016/j.aeue.2026.156217","DOIUrl":"10.1016/j.aeue.2026.156217","url":null,"abstract":"<div><div>This paper presents a low-power, highly-linear three-stage Class AB headphone capable of driving a wide load capacitor (<em>C</em><sub><em>L</em></sub>) range using an advanced frequency compensation network. A local AC feedback network replaces the classical transconductor-based quality factor control, enabling to reduce the silicon area and quiescent power by implementing the intermediate stage as a simple inverting common-source amplifier. Miller capacitance is split and each portion is coupled to an embedded current buffer, thereby moving non-dominant poles to higher frequencies without requiring new gain stages or bias-dependent elements. The proposed approach combines the wide-range load driving capability and high linearity under reduced power and area, making it suitable for high-fidelity headphone drivers. Post-layout simulation results of a prototype in a standard 65-nm CMOS process demonstrate a robust operation for the capacitive loads from 0 to 22 nF, achieving more than 114 dB DC gain and a minimum phase margin of 45°. It delivers 89.9 mW peak power into a 16 Ω load while consuming 0.52 mW power in 0.22 mm<sup>2</sup> silicon area. The THD + N of full-scale output is −104.6 dB at 20 KHz.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156217"},"PeriodicalIF":3.2,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147398930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0