This paper proposes a design method of a wideband Doherty power amplifier (DPA) using resistive continuous class-J mode with harmonic load modulation suppression, aiming to achieve high efficiency at back-off output powers (BOPs) across a wide frequency band. Firstly, based on theoretical impedance analysis of the resistive continuous class-J mode, the optimum load impedances under both saturation and BOP conditions are identified for DPA design. Then, combined with the load modulation theory, optimization objective functions are formulated for the peaking output matching networks (OMNs) design and optimization. In addition, to control the carrier second harmonic impedance during the load modulation, the peaking OMN using fragment-type matching circuit is used to suppress harmonic load modulation. For verification, a DPA operating at 2.0–3.4 GHz is designed and measured. The results show that the DPA achieves saturated output power of 43.1–44.4 dBm across the entire frequency band, with drain efficiencies of 59.1%–72% at saturation and 50%–58.9% at 6 dB BOP.
{"title":"Design of wideband resistive continuous class-J Doherty power amplifier with harmonic load modulation suppression","authors":"Wa Kong, Wenya Liu, Hongyan Fu, Hui Ma, Wence Zhang, Jing Xia","doi":"10.1016/j.aeue.2026.156226","DOIUrl":"10.1016/j.aeue.2026.156226","url":null,"abstract":"<div><div>This paper proposes a design method of a wideband Doherty power amplifier (DPA) using resistive continuous class-J mode with harmonic load modulation suppression, aiming to achieve high efficiency at back-off output powers (BOPs) across a wide frequency band. Firstly, based on theoretical impedance analysis of the resistive continuous class-J mode, the optimum load impedances under both saturation and BOP conditions are identified for DPA design. Then, combined with the load modulation theory, optimization objective functions are formulated for the peaking output matching networks (OMNs) design and optimization. In addition, to control the carrier second harmonic impedance during the load modulation, the peaking OMN using fragment-type matching circuit is used to suppress harmonic load modulation. For verification, a DPA operating at 2.0–3.4 GHz is designed and measured. The results show that the DPA achieves saturated output power of 43.1–44.4 dBm across the entire frequency band, with drain efficiencies of 59.1%–72% at saturation and 50%–58.9% at 6 dB BOP.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156226"},"PeriodicalIF":3.2,"publicationDate":"2026-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a novel Phase Frequency Detector (PFD) based on Dynamic MOS Current Mode Logic (DyCML), designed for low-power, high-speed frequency synthesizers. The proposed PFD eliminates the need for a reset path, thereby removing dead and blind zones and improving output linearity across a full phase range from –π to π. The DyCML approach offers inherent advantages such as low static power dissipation, high-speed switching, and enhanced noise immunity through differential, current-mode operation. Design parameters were optimized using Taguchi Design of Experiments (DoE) and Analysis of Variance (ANOVA) techniques to achieve optimal performance. The optimized PFD achieves a phase noise of –159.41 dBc/Hz, power consumption of 5.822 μW, maximum operating frequency of 6.91 GHz, and a delay of 42.76 ps. The layout area is 793.27 μm2, and the design attains a figure-of-merit of –168.55 dBc/Hz. Robustness is validated through Process-Voltage-Temperature and Monte Carlo analysis, showing close agreement between post-layout and pre-layout results. Integrated into a PLL frequency synthesizer, the PFD achieves a lock time of 500 ns at output frequency 3.8 GHz, with low jitter and minimal reference spur. The design is implemented in Cadence Virtuoso using a 0.18 μm SCL CMOS process at a 1.8 V supply.
{"title":"Design and optimization of a low-power dynamic MCML-based phase-frequency detector using Taguchi DoE and ANOVA for frequency synthesizers with fast-locking of 0.5 μs","authors":"Dheeraj Singh Rajput , Bharat Choudhary , Archana Singhal , Dharmendar Boolchandani","doi":"10.1016/j.aeue.2026.156214","DOIUrl":"10.1016/j.aeue.2026.156214","url":null,"abstract":"<div><div>This paper introduces a novel Phase Frequency Detector (PFD) based on Dynamic MOS Current Mode Logic (DyCML), designed for low-power, high-speed frequency synthesizers. The proposed PFD eliminates the need for a reset path, thereby removing dead and blind zones and improving output linearity across a full phase range from –π to π. The DyCML approach offers inherent advantages such as low static power dissipation, high-speed switching, and enhanced noise immunity through differential, current-mode operation. Design parameters were optimized using Taguchi Design of Experiments (DoE) and Analysis of Variance (ANOVA) techniques to achieve optimal performance. The optimized PFD achieves a phase noise of –159.41 dBc/Hz, power consumption of 5.822 μW, maximum operating frequency of 6.91 GHz, and a delay of 42.76 ps. The layout area is 793.27 μm<sup>2</sup>, and the design attains a figure-of-merit of –168.55 dBc/Hz. Robustness is validated through Process-Voltage-Temperature and Monte Carlo analysis, showing close agreement between post-layout and pre-layout results. Integrated into a PLL frequency synthesizer, the PFD achieves a lock time of 500 ns at output frequency 3.8 GHz, with low jitter and minimal reference spur. The design is implemented in Cadence Virtuoso using a 0.18 μm SCL CMOS process at a 1.8 V supply.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156214"},"PeriodicalIF":3.2,"publicationDate":"2026-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-16DOI: 10.1016/j.aeue.2026.156212
Jianhong Xiang, Nan Zhang, Linyu Wang
In massive multiple-input multiple-output (MIMO) systems, accurate downlink channel state information (CSI) is essential for signal preprocessing, yet achieving high-fidelity feedback under limited overhead remains challenging. To address this issue, and motivated by the sparsity and strong local spatial structure of CSI, we propose an all-domain joint CSI feedback network based on multi-scale pooling, termed APCNet. The encoder of this network introduces a spatial–frequency domain branch on the basis of the classical angle–delay domain (ADD) convolution branch, aiming to provide complete physical feature priors for the reconstruction process, fundamentally solving the information loss issue caused by single-domain modeling. On the decoder side, we propose a PCformer architecture, constructing a physically aligned extraction–reconstruction pipeline: utilizing the multi-scale pooling module for statistical extraction of multipath features, and combining the ConvNeXt Block for fine-grained restoration of spatial details. This compensates for the shortcomings of the universal self-attention mechanism in local structure representation. Experimental results demonstrate that APCNet achieves an average improvement of 7.96% in reconstruction accuracy across various compression rates for outdoor scenes, while delivering leading or competitive performance for most compression rates in indoor scenes.
{"title":"APCNet: A multi-scale pooling enhanced all-domain joint CSI feedback network for massive MIMO systems","authors":"Jianhong Xiang, Nan Zhang, Linyu Wang","doi":"10.1016/j.aeue.2026.156212","DOIUrl":"10.1016/j.aeue.2026.156212","url":null,"abstract":"<div><div>In massive multiple-input multiple-output (MIMO) systems, accurate downlink channel state information (CSI) is essential for signal preprocessing, yet achieving high-fidelity feedback under limited overhead remains challenging. To address this issue, and motivated by the sparsity and strong local spatial structure of CSI, we propose an all-domain joint CSI feedback network based on multi-scale pooling, termed APCNet. The encoder of this network introduces a spatial–frequency domain branch on the basis of the classical angle–delay domain (ADD) convolution branch, aiming to provide complete physical feature priors for the reconstruction process, fundamentally solving the information loss issue caused by single-domain modeling. On the decoder side, we propose a PCformer architecture, constructing a physically aligned extraction–reconstruction pipeline: utilizing the multi-scale pooling module for statistical extraction of multipath features, and combining the ConvNeXt Block for fine-grained restoration of spatial details. This compensates for the shortcomings of the universal self-attention mechanism in local structure representation. Experimental results demonstrate that APCNet achieves an average improvement of 7.96% in reconstruction accuracy across various compression rates for outdoor scenes, while delivering leading or competitive performance for most compression rates in indoor scenes.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156212"},"PeriodicalIF":3.2,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-16DOI: 10.1016/j.aeue.2026.156216
P. Manikandan
This work proposes a fast transient, dynamically biased cascoded flipped voltage follower low-dropout (LDO) regulator. The proposed LDO is constructed based on a single-stage error amplifier (EA) and a cascoded flipped voltage follower. The proposed error amplifier dynamically biases the CAFVF and enhances the transient and stability performance of the LDO regulator. This work uses three different feed-forward transconductors along with one miller and two feed-forward small compensatory capacitors. Two of these feed-forward transconductors and three small compensation capacitors generate two low-frequency left-half-plane (LHP) zeros in conjunction with the self-feed-forward path. These LHP zeros are unaffected by load conditions and provide consistent phase lead for all the load cases. Another feed-forward transconductor converts the load-dependent right-half-plane (RHP) Miller zero to an LHP zero. The load-dependent LHP zero appears closer to the unity gain frequency (UGF) for a lightly loaded LDO, improving its stability under light load situations. The proposed frequency compensation technique stabilizes the LDO for load currents ranging from 0 to , with a maximum load capacitor of . The proposed LDO is designed using UMC CMOS technology and implemented with the Cadence Virtuoso tool. With a maximum quiescent current of , the proposed LDO achieves a minimum good slew rate (SR) of and minimum unity gain frequency of , allowing it to settle faster with a settling time of . The reliability and robustness of the proposed LDO are verified using the process corners with an extreme temperature range and 200-point Monte Carlo simulations.
{"title":"A fast transient dynamically biased output capacitor-less cascoded flipped voltage follower (CAFVF) LDO regulator","authors":"P. Manikandan","doi":"10.1016/j.aeue.2026.156216","DOIUrl":"10.1016/j.aeue.2026.156216","url":null,"abstract":"<div><div>This work proposes a fast transient, dynamically biased cascoded flipped voltage follower low-dropout (LDO) regulator. The proposed LDO is constructed based on a single-stage error amplifier (EA) and a cascoded flipped voltage follower. The proposed error amplifier dynamically biases the CAFVF and enhances the transient and stability performance of the LDO regulator. This work uses three different feed-forward transconductors along with one miller and two feed-forward small compensatory capacitors. Two of these feed-forward transconductors and three small compensation capacitors generate two low-frequency left-half-plane (LHP) zeros in conjunction with the self-feed-forward path. These LHP zeros are unaffected by load conditions and provide consistent phase lead for all the load cases. Another feed-forward transconductor converts the load-dependent right-half-plane (RHP) Miller zero to an LHP zero. The load-dependent LHP zero appears closer to the unity gain frequency (UGF) for a lightly loaded LDO, improving its stability under light load situations. The proposed frequency compensation technique stabilizes the LDO for load currents ranging from 0 to <span><math><mrow><mn>30</mn><mspace></mspace><mi>mA</mi></mrow></math></span>, with a maximum load capacitor of <span><math><mrow><mn>50</mn><mspace></mspace><mi>pF</mi></mrow></math></span>. The proposed LDO is designed using UMC <span><math><mrow><mn>90</mn><mspace></mspace><mi>nm</mi></mrow></math></span> CMOS technology and implemented with the Cadence Virtuoso tool. With a maximum quiescent current of <span><math><mrow><mn>91</mn><mo>.</mo><mn>3</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span>, the proposed LDO achieves a minimum good slew rate (SR) of <span><math><mrow><mn>30</mn><mspace></mspace><mi>V</mi><mo>/</mo><mi>μ</mi><mi>s</mi></mrow></math></span> and minimum unity gain frequency of <span><math><mrow><mn>15</mn><mo>.</mo><mn>7</mn><mspace></mspace><mi>MHz</mi></mrow></math></span>, allowing it to settle faster with a settling time of <span><math><mrow><mn>30</mn><mspace></mspace><mi>ns</mi></mrow></math></span>. The reliability and robustness of the proposed LDO are verified using the process corners with an extreme temperature range and 200-point Monte Carlo simulations.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156216"},"PeriodicalIF":3.2,"publicationDate":"2026-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-15DOI: 10.1016/j.aeue.2026.156218
Wan-Hao Xu , Junbing Duan , Lei Zhu , Cheng Liao , You-Feng Cheng , Ting Shi
This article investigates and analyzes the high-gain condition based on a vertically polarized (VP) endfire leaky-wave antenna by periodically loading parallel inductive elements on both sides of the double-sided parallel strip line. A radiation model of the employed leaky-wave antenna is firstly established to explore the effects of period length as well as propagation constants on the radiation gains and efficiencies. To achieve the high gain and efficiency, the structural influences of the antenna are then analyzed to explore the proper loading stub model to meet those requirements for the propagation characteristics. A prototype antenna is in final designed and fabricated to verify its performance in achieving high gain and efficiency radiation. The simulation results are in good agreement with the measured results, demonstrating the effectiveness of the resulted high-gain radiation condition for the VP endfire leaky-wave antenna.
{"title":"Proposal and analysis of high-gain vertically-polarized endfire leaky-wave antenna","authors":"Wan-Hao Xu , Junbing Duan , Lei Zhu , Cheng Liao , You-Feng Cheng , Ting Shi","doi":"10.1016/j.aeue.2026.156218","DOIUrl":"10.1016/j.aeue.2026.156218","url":null,"abstract":"<div><div>This article investigates and analyzes the high-gain condition based on a vertically polarized (VP) endfire leaky-wave antenna by periodically loading parallel inductive elements on both sides of the double-sided parallel strip line. A radiation model of the employed leaky-wave antenna is firstly established to explore the effects of period length as well as propagation constants on the radiation gains and efficiencies. To achieve the high gain and efficiency, the structural influences of the antenna are then analyzed to explore the proper loading stub model to meet those requirements for the propagation characteristics. A prototype antenna is in final designed and fabricated to verify its performance in achieving high gain and efficiency radiation. The simulation results are in good agreement with the measured results, demonstrating the effectiveness of the resulted high-gain radiation condition for the VP endfire leaky-wave antenna.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156218"},"PeriodicalIF":3.2,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145982035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vivaldi antennas used in Ground Penetrating Radar (GPR) systems often experience performance degradation at low frequencies due to inefficient radiation and impedance mismatch between the feedline and the tapered slot structure. To address these limitations, this paper presents a compact Vivaldi antenna employing a coplanar waveguide (CPW) feedline integrated with a single-stub matching technique. The stub position is analytically optimized to improve impedance matching over a broad frequency range. The CPW configuration simplifies the antenna structure by placing both the feedline and ground plane on the same substrate layer, resulting in a compact layout and facilitating broadband operation. The proposed antenna is fabricated on an FR-4 substrate with a thickness of and a relative permittivity of , with overall dimensions of . The measured results demonstrate broadband operation from 1.13 to 5 GHz. The antenna achieves a peak gain of 10.89 dBi in simulation and 10.36 dBi in measurement at 1.9 GHz, with a measured radiation efficiency of approximately 90.16% at the resonant frequency. The corresponding simulated and measured values of dB and dB indicate effective impedance matching at resonance, with minor discrepancies attributed to fabrication tolerances and measurement conditions. To assess practical feasibility, a preliminary sandbox-based GPR experiment was conducted using a pair of identical antennas in a bistatic configuration. The resulting A-scan response shows a distinct reflection corresponding to a buried metallic target at an estimated depth of 37.7 cm, which agrees well with the actual burial depth. These results indicate that the proposed antenna can support broadband GPR sensing within the investigated frequency range, while further system-level and field validations are recommended.
{"title":"CPW feed and stub optimization for Vivaldi antennas in broadband ground-penetrating radar applications","authors":"Kurnia Paranita Kartika Riyanti , Eko Setijadi , Gamantyo Hendrantoro , Nurhayati","doi":"10.1016/j.aeue.2026.156219","DOIUrl":"10.1016/j.aeue.2026.156219","url":null,"abstract":"<div><div>Vivaldi antennas used in Ground Penetrating Radar (GPR) systems often experience performance degradation at low frequencies due to inefficient radiation and impedance mismatch between the feedline and the tapered slot structure. To address these limitations, this paper presents a compact Vivaldi antenna employing a coplanar waveguide (CPW) feedline integrated with a single-stub matching technique. The stub position is analytically optimized to improve impedance matching over a broad frequency range. The CPW configuration simplifies the antenna structure by placing both the feedline and ground plane on the same substrate layer, resulting in a compact layout and facilitating broadband operation. The proposed antenna is fabricated on an FR-4 substrate with a thickness of <span><math><mrow><mn>1</mn><mo>.</mo><mn>6</mn><mspace></mspace><mi>mm</mi></mrow></math></span> and a relative permittivity of <span><math><mrow><msub><mrow><mi>ϵ</mi></mrow><mrow><mi>r</mi></mrow></msub><mo>=</mo><mn>4</mn><mo>.</mo><mn>3</mn></mrow></math></span>, with overall dimensions of <span><math><mrow><mn>80</mn><mo>×</mo><mn>80</mn><mo>×</mo><mn>1</mn><mo>.</mo><mn>635</mn></mrow></math></span> <span><math><msup><mrow><mi>mm</mi></mrow><mrow><mn>3</mn></mrow></msup></math></span>. The measured results demonstrate broadband operation from 1.13 to 5 GHz. The antenna achieves a peak gain of 10.89 dBi in simulation and 10.36 dBi in measurement at 1.9 GHz, with a measured radiation efficiency of approximately 90.16% at the resonant frequency. The corresponding simulated and measured <span><math><msub><mrow><mi>S</mi></mrow><mrow><mn>11</mn></mrow></msub></math></span> values of <span><math><mrow><mo>−</mo><mn>61</mn><mo>.</mo><mn>21</mn></mrow></math></span> dB and <span><math><mrow><mo>−</mo><mn>39</mn><mo>.</mo><mn>13</mn></mrow></math></span> dB indicate effective impedance matching at resonance, with minor discrepancies attributed to fabrication tolerances and measurement conditions. To assess practical feasibility, a preliminary sandbox-based GPR experiment was conducted using a pair of identical antennas in a bistatic configuration. The resulting A-scan response shows a distinct reflection corresponding to a buried metallic target at an estimated depth of 37.7 cm, which agrees well with the actual burial depth. These results indicate that the proposed antenna can support broadband GPR sensing within the investigated frequency range, while further system-level and field validations are recommended.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156219"},"PeriodicalIF":3.2,"publicationDate":"2026-01-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146080292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-13DOI: 10.1016/j.aeue.2026.156215
Dongqi Chen , Kun Ye , Chuanxi Xing , Lang Zhou , Haixin Sun
This paper proposes a novel nested array (IAMDNA) by defining the positions of array elements through a special subarray design. This array can maintain the degrees of freedom (DOF) at a better level while greatly reducing the mutual coupling effect of the array. The paper presents closed-form expressions for the sensor positions and their corresponding DOFs in the novel nested array structure. Furthermore, through rigorous proof, the optimal array position expression for a specific number of sensors is derived. Array structure analysis and numerical simulation results show that, without considering array mutual coupling effects, the array’s estimation performance depends only on the DOFs. Based on this, the estimation accuracy of IAMDNA is slightly inferior to that of the comparison array. However, once the mutual coupling effect that must be considered in practical applications is introduced, the estimation accuracy of the IAMDNA array is significantly better than that of the comparison array, achieving a performance reversal. In conclusion, the physical structure of the IAMDNA array is sparser, which enables it to maintain excellent DOF while having greater practical application capabilities to resist mutual coupling effects.
{"title":"An improved sparse array design for improving DOA estimation performance under mutual coupling effect","authors":"Dongqi Chen , Kun Ye , Chuanxi Xing , Lang Zhou , Haixin Sun","doi":"10.1016/j.aeue.2026.156215","DOIUrl":"10.1016/j.aeue.2026.156215","url":null,"abstract":"<div><div>This paper proposes a novel nested array (IAMDNA) by defining the positions of array elements through a special subarray design. This array can maintain the degrees of freedom (DOF) at a better level while greatly reducing the mutual coupling effect of the array. The paper presents closed-form expressions for the sensor positions and their corresponding DOFs in the novel nested array structure. Furthermore, through rigorous proof, the optimal array position expression for a specific number of sensors is derived. Array structure analysis and numerical simulation results show that, without considering array mutual coupling effects, the array’s estimation performance depends only on the DOFs. Based on this, the estimation accuracy of IAMDNA is slightly inferior to that of the comparison array. However, once the mutual coupling effect that must be considered in practical applications is introduced, the estimation accuracy of the IAMDNA array is significantly better than that of the comparison array, achieving a performance reversal. In conclusion, the physical structure of the IAMDNA array is sparser, which enables it to maintain excellent DOF while having greater practical application capabilities to resist mutual coupling effects.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"206 ","pages":"Article 156215"},"PeriodicalIF":3.2,"publicationDate":"2026-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145977979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-12DOI: 10.1016/j.aeue.2026.156213
Shuaishuai Pan, Zhiyong Luo
Direction of Arrival (DOA) estimation has been applied in satellite applications. However, the growing demand for data volume has driven the gradual expansion of signal bandwidth, making broadband DOA estimation a critical challenge. Existing subspace-based DOA estimation algorithms usually exhibit weak performance and require prior information about the number of signals, limiting their practical applications. To address this issue, this paper proposes a novel broadband DOA estimation method based on covariance matrix reconstruction. First, focusing processing is applied to sampled data at different frequency points, and Eigenvalue Decomposition (EVD) is performed after obtaining the sample covariance matrix (SCM). Subsequently, a new clustering technique is developed by combining Gaussian Mixture Model (GMM) and Markov Random Field (MRF) theory to classify eigenvalues into signal and noise classes, thereby determining the number of signals. Then, a metric based on Kullback–Leibler (KL) divergence is constructed to measure subspace similarity and reconstruct the covariance matrix. Finally, DOA estimation is conducted using the reconstructed covariance matrix. Simulation results show that the proposed algorithms outperform other methods.
{"title":"Broadband DOA estimation with KL divergence for covariance matrix reconstruction","authors":"Shuaishuai Pan, Zhiyong Luo","doi":"10.1016/j.aeue.2026.156213","DOIUrl":"10.1016/j.aeue.2026.156213","url":null,"abstract":"<div><div>Direction of Arrival (DOA) estimation has been applied in satellite applications. However, the growing demand for data volume has driven the gradual expansion of signal bandwidth, making broadband DOA estimation a critical challenge. Existing subspace-based DOA estimation algorithms usually exhibit weak performance and require prior information about the number of signals, limiting their practical applications. To address this issue, this paper proposes a novel broadband DOA estimation method based on covariance matrix reconstruction. First, focusing processing is applied to sampled data at different frequency points, and Eigenvalue Decomposition (EVD) is performed after obtaining the sample covariance matrix (SCM). Subsequently, a new clustering technique is developed by combining Gaussian Mixture Model (GMM) and Markov Random Field (MRF) theory to classify eigenvalues into signal and noise classes, thereby determining the number of signals. Then, a metric based on Kullback–Leibler (KL) divergence is constructed to measure subspace similarity and reconstruct the covariance matrix. Finally, DOA estimation is conducted using the reconstructed covariance matrix. Simulation results show that the proposed algorithms outperform other methods.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"206 ","pages":"Article 156213"},"PeriodicalIF":3.2,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145977981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2026-01-10DOI: 10.1016/j.aeue.2026.156209
Xinyu Zhang , Lijuan Zhong , Shidang Li , Yanping Zhou , Jianbin Cao , Chunguo Li
In practical wireless systems, transceiver hardware impairments (HWIs) introduce additional noise and nonlinear distortions, leading to degradation in physical layer security performance. In integrated sensing and communication (ISAC) systems, the transmitted waveform carrying communication information is susceptible to eavesdropping by sensing targets. To address this challenge, this paper investigates a reconfigurable intelligent surface (RIS)-assisted ISAC system that accounts for hardware impairments at both the transmitter and receiver. To enhance physical layer security and reduce information leakage to unauthorized users, we propose the strategic injection of artificial noise (AN) under certain conditions to degrade the signal quality at potential eavesdroppers. Specifically, we formulate a joint optimization problem involving sensing beamforming, artificial noise design, and RIS reflection coefficients, aiming to maximize the achievable secrecy rate while satisfying constraints on total transmit power, minimum communication rate, minimum radar sensing signal-to-noise ratio (SINR), and unit-modulus reflection coefficients. To solve the resulting non-convex problem, we first perform an equivalent transformation and decouple it into two non-convex subproblems. We then apply successive convex approximation (SCA) and semidefinite relaxation (SDR) to approximate the subproblems as convex programs. Finally, an alternating optimization (AO) algorithm is developed to efficiently solve the reformulated problem. Simulation results demonstrate that the proposed scheme effectively mitigates the performance degradation caused by hardware impairments and achieves an optimal trade-off between interference shaping and privacy preservation, outperforming conventional schemes without AN, RIS, or hardware impairment considerations.
{"title":"Joint robust beamforming design for RIS-assisted ISAC systems with hardware impairments","authors":"Xinyu Zhang , Lijuan Zhong , Shidang Li , Yanping Zhou , Jianbin Cao , Chunguo Li","doi":"10.1016/j.aeue.2026.156209","DOIUrl":"10.1016/j.aeue.2026.156209","url":null,"abstract":"<div><div>In practical wireless systems, transceiver hardware impairments (HWIs) introduce additional noise and nonlinear distortions, leading to degradation in physical layer security performance. In integrated sensing and communication (ISAC) systems, the transmitted waveform carrying communication information is susceptible to eavesdropping by sensing targets. To address this challenge, this paper investigates a reconfigurable intelligent surface (RIS)-assisted ISAC system that accounts for hardware impairments at both the transmitter and receiver. To enhance physical layer security and reduce information leakage to unauthorized users, we propose the strategic injection of artificial noise (AN) under certain conditions to degrade the signal quality at potential eavesdroppers. Specifically, we formulate a joint optimization problem involving sensing beamforming, artificial noise design, and RIS reflection coefficients, aiming to maximize the achievable secrecy rate while satisfying constraints on total transmit power, minimum communication rate, minimum radar sensing signal-to-noise ratio (SINR), and unit-modulus reflection coefficients. To solve the resulting non-convex problem, we first perform an equivalent transformation and decouple it into two non-convex subproblems. We then apply successive convex approximation (SCA) and semidefinite relaxation (SDR) to approximate the subproblems as convex programs. Finally, an alternating optimization (AO) algorithm is developed to efficiently solve the reformulated problem. Simulation results demonstrate that the proposed scheme effectively mitigates the performance degradation caused by hardware impairments and achieves an optimal trade-off between interference shaping and privacy preservation, outperforming conventional schemes without AN, RIS, or hardware impairment considerations.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"206 ","pages":"Article 156209"},"PeriodicalIF":3.2,"publicationDate":"2026-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145927444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes a broadband and compact filtering power divider (FPD) based on quarter circular/cambered (QCC) substrate integrated waveguide (SIW) and coplanar waveguide (CPW) resonators. Firstly, the impact of the CPW slot length on the quality factor (Q) of the QCC SIW resonator is analyzed. Subsequently, the CPW resonator is integrated into the QCC SIW to form a third-order bandpass filter (BPF) with a cascaded trisection (CT) topology. A transmission zero is located in the upper stopband. Finally, two third-order hybrid QCC SIW and CPW filtering power dividers (FPDs) with and without isolation resistors are designed. Furthermore, this paper introduces a new method for rapidly determining the quantity and value of isolation resistors. All the designs presented in this paper are simulated, manufactured, and experimentally validated. The measured results indicate that the proposed third-order FPD with isolation resistors operates at a center frequency of 5.08 GHz with a 3-dB FBW of 41.3% (2.1 GHz). The insertion loss (IL) is approximately (3 + 1.1) dB. The isolation between two output ports is better than 16 dB. A transmission zero (TZ) can be observed at 6.75 GHz in the right side of the passband attributing to the cross-coupling scheme, which enhances the out-of-band selectivity. The overall size of the proposed FPD with isolation resistors is 1.71λg × 1.49λg, and it features advantages of broad operating bandwidth, compact physical size, and low insertion loss.
{"title":"Broadband and compact filtering power divider employing quarter circular/cambered SIW and CPW structures","authors":"Ke-Long Sheng, Xiang Wang, Song-Song Qian, Zhi-Yuan Zong, Huangyan Li, Boyu Sima, Wen Wu","doi":"10.1016/j.aeue.2026.156196","DOIUrl":"10.1016/j.aeue.2026.156196","url":null,"abstract":"<div><div>This paper proposes a broadband and compact filtering power divider (FPD) based on quarter circular/cambered (QCC) substrate integrated waveguide (SIW) and coplanar waveguide (CPW) resonators. Firstly, the impact of the CPW slot length on the quality factor (<em>Q</em>) of the QCC SIW resonator is analyzed. Subsequently, the CPW resonator is integrated into the QCC SIW to form a third-order bandpass filter (BPF) with a cascaded trisection (CT) topology. A transmission zero is located in the upper stopband. Finally, two third-order hybrid QCC SIW and CPW filtering power dividers (FPDs) with and without isolation resistors are designed. Furthermore, this paper introduces a new method for rapidly determining the quantity and value of isolation resistors. All the designs presented in this paper are simulated, manufactured, and experimentally validated. The measured results indicate that the proposed third-order FPD with isolation resistors operates at a center frequency of 5.08 GHz with a 3-dB FBW of 41.3% (2.1 GHz). The insertion loss (IL) is approximately (3 + 1.1) dB. The isolation between two output ports is better than 16 dB. A transmission zero (TZ) can be observed at 6.75 GHz in the right side of the passband attributing to the cross-coupling scheme, which enhances the out-of-band selectivity. The overall size of the proposed FPD with isolation resistors is 1.71<em>λ</em><sub><em>g</em></sub> × 1.49<em>λ</em><sub><em>g</em></sub>, and it features advantages of broad operating bandwidth, compact physical size, and low insertion loss.</div></div>","PeriodicalId":50844,"journal":{"name":"Aeu-International Journal of Electronics and Communications","volume":"207 ","pages":"Article 156196"},"PeriodicalIF":3.2,"publicationDate":"2026-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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