Pub Date : 2023-10-05DOI: 10.1080/00207217.2023.2267220
Seyed Jalil Hosseini, Mohammad Khalaj-Amirhosseini
ABSTRACTIn this paper, a compact leaky-wave planer antenna is proposed. The proposed antenna fabricated by the printed circuit broad technology can scan a large part of its upper half-space. The proposed antenna consists of a metallic six-pointed star on a regular hexagon. The back of the hexagon is wholly covered with a conductor. The structure’s detailed design and analysis have been done using the dispersion diagram. In the proposed antenna, changing the frequency can steer the main beam in elevation at six-step angles of azimuth. The simulation and measurement results confirm the theory well. The leaky wave structure is an attractive and economical method to scan half-space.KEYWORDS: Beam scanning antennafrequency steering antennahalf-space scanningleaky-wave antennaplanar antennaDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. AcknowledgementsThe authors thank the Editor-in-Chief, the Associate Editor, and the reviewers for their constructive comments that are important for improving this study.Declaration of Interest statementThere are no relevant financial or non-financial competing interests to report.
{"title":"A compact star-shaped leaky-wave antenna for half-space steering","authors":"Seyed Jalil Hosseini, Mohammad Khalaj-Amirhosseini","doi":"10.1080/00207217.2023.2267220","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267220","url":null,"abstract":"ABSTRACTIn this paper, a compact leaky-wave planer antenna is proposed. The proposed antenna fabricated by the printed circuit broad technology can scan a large part of its upper half-space. The proposed antenna consists of a metallic six-pointed star on a regular hexagon. The back of the hexagon is wholly covered with a conductor. The structure’s detailed design and analysis have been done using the dispersion diagram. In the proposed antenna, changing the frequency can steer the main beam in elevation at six-step angles of azimuth. The simulation and measurement results confirm the theory well. The leaky wave structure is an attractive and economical method to scan half-space.KEYWORDS: Beam scanning antennafrequency steering antennahalf-space scanningleaky-wave antennaplanar antennaDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also. AcknowledgementsThe authors thank the Editor-in-Chief, the Associate Editor, and the reviewers for their constructive comments that are important for improving this study.Declaration of Interest statementThere are no relevant financial or non-financial competing interests to report.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135483327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-04DOI: 10.1080/00207217.2023.2267215
Tian-Bo Deng
ABSTRACTThis paper first develops a novel transformation-based strategy for guaranteeing the stability of recursive-type variable digital filters, and then presents a new type of functions called less-than-unity (LTU) functions required in performing stability-guaranteed parameter transformations (LTU transformations). The LTU transformations can be viewed as the generalised existing one. Based on the LTU transformations, a recursive bandpass filter with variable passband-width (PBW) is attained using the minimax criterion so that the stability is ensured. The recursive bandpass filter has continuously PBW and fixed passband centre frequency. To meet the stability condition of the recursive variable PBW bandpass filter (variable-PBW filter), the LTU parameter transformations are incorporated into the minimisation of the maximum amplitude-response error. It can be proved that incorporating the LTU transformations into the design process definitely produces a recursive variable-PBW filter whose stability is absolutely guaranteed. For verifying the ensured stability and demonstrating the high design accuracy, detailed computer simulations are included. The illustrative example verifies that the obtained variable-PBW filter not only has definitely ensured stability, but also its approximation accuracy is extremely high.KEYWORDS: Variable passband-width (PBW)stability guaranteeLess-than-unity (LTU) transformationLTU functionDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"Generalized strategy for stabilizing minimax-type variable bandpass filter","authors":"Tian-Bo Deng","doi":"10.1080/00207217.2023.2267215","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267215","url":null,"abstract":"ABSTRACTThis paper first develops a novel transformation-based strategy for guaranteeing the stability of recursive-type variable digital filters, and then presents a new type of functions called less-than-unity (LTU) functions required in performing stability-guaranteed parameter transformations (LTU transformations). The LTU transformations can be viewed as the generalised existing one. Based on the LTU transformations, a recursive bandpass filter with variable passband-width (PBW) is attained using the minimax criterion so that the stability is ensured. The recursive bandpass filter has continuously PBW and fixed passband centre frequency. To meet the stability condition of the recursive variable PBW bandpass filter (variable-PBW filter), the LTU parameter transformations are incorporated into the minimisation of the maximum amplitude-response error. It can be proved that incorporating the LTU transformations into the design process definitely produces a recursive variable-PBW filter whose stability is absolutely guaranteed. For verifying the ensured stability and demonstrating the high design accuracy, detailed computer simulations are included. The illustrative example verifies that the obtained variable-PBW filter not only has definitely ensured stability, but also its approximation accuracy is extremely high.KEYWORDS: Variable passband-width (PBW)stability guaranteeLess-than-unity (LTU) transformationLTU functionDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135646123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-04DOI: 10.1080/00207217.2023.2267213
Kadhim Jawad Abdulkarim Al-Khafaji, Hamed Abbasi
ABSTRACTIn this paper, a Wilkinson power divider based on a new harmonic suppressor structure is proposed with suppressed harmonics and improved operating band parameters. The proposed suppressor structure consists of three resonators. The first resonator is an elliptic rectangular shaped resonator with a short base line and two slots. These slots decrease the resonant frequency location, without changing the dimensions of the resonator. This mode has been fully analysed by investigating the effect of surface current density. The second resonator is an elliptic resonator with a long base length to suppress the second harmonic. The third resonator is a rectangular suppressor to suppress higher order harmonics. The proposed power divider is fabricated and measured. The operating frequency of this power divider is 1.26 GHz, the return loss is 31.5 dB and the insertion loss is 3.1 dB. The operating bandwidth is from 0.99 to 1.4 GHz with a return loss better than 15 dB which shows the fractional bandwidth of FBW = 34%. The second to sixth harmonics have suppression level better than 50 dB, and for higher harmonics up to the 14th harmonic, they have suppression level better than 25 dB.KEYWORDS: Improved passband parametersHigh suppression levelWilkinson Power DividerWide rejection bandharmonic suppressionDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"Design a Wilkinson power divider with improved passband and rejection band","authors":"Kadhim Jawad Abdulkarim Al-Khafaji, Hamed Abbasi","doi":"10.1080/00207217.2023.2267213","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267213","url":null,"abstract":"ABSTRACTIn this paper, a Wilkinson power divider based on a new harmonic suppressor structure is proposed with suppressed harmonics and improved operating band parameters. The proposed suppressor structure consists of three resonators. The first resonator is an elliptic rectangular shaped resonator with a short base line and two slots. These slots decrease the resonant frequency location, without changing the dimensions of the resonator. This mode has been fully analysed by investigating the effect of surface current density. The second resonator is an elliptic resonator with a long base length to suppress the second harmonic. The third resonator is a rectangular suppressor to suppress higher order harmonics. The proposed power divider is fabricated and measured. The operating frequency of this power divider is 1.26 GHz, the return loss is 31.5 dB and the insertion loss is 3.1 dB. The operating bandwidth is from 0.99 to 1.4 GHz with a return loss better than 15 dB which shows the fractional bandwidth of FBW = 34%. The second to sixth harmonics have suppression level better than 50 dB, and for higher harmonics up to the 14th harmonic, they have suppression level better than 25 dB.KEYWORDS: Improved passband parametersHigh suppression levelWilkinson Power DividerWide rejection bandharmonic suppressionDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135549219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-04DOI: 10.1080/00207217.2023.2267209
Aruna Pathak, Manoj Kumar Tiwari, Neeta Pandey, Sajal K Paul, Saiyid Mohammad Irshad Rizvi
ABSTRACTIn the existing dual output resistance tunable current controlled conveyor (DO-RTCCCII), a resistance trimming block is added at the X terminal (RXdig) which is controlled by programmable bits. RXdig includes the variations due to bias current (i.e. intrinsic resistance, RX) and due to setting of digital bits. However, the PVT variations may cause deviations in bias current, thus leading to inaccuracies in the design parameters. To address this, a programmable PVT compensated DO-RTCCCII (PPC-DO-RTCCCII) is proposed. It uses a reference generation section along with DO-RTCCCII. The reference generation section uses bias compensation bits for PVT independent bias current generation and also provides flexibility to get desired bias current through current multiplication bits. The operation of the proposed PPC-DO-RTCCCII has been designed and simulated using 28 nm CMOS technology through the simulator ELDO (AMS) tool of Mentor graphics. The post layout simulations closely match with pre layout simulations. A filter circuit is also included to illustrate the usefulness of the proposal.KEYWORDS: Analoguecurrent controlled current conveyorPVTElectronic tunabilityDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"Programmable PVT compensated dual output resistance tunable current controlled conveyor","authors":"Aruna Pathak, Manoj Kumar Tiwari, Neeta Pandey, Sajal K Paul, Saiyid Mohammad Irshad Rizvi","doi":"10.1080/00207217.2023.2267209","DOIUrl":"https://doi.org/10.1080/00207217.2023.2267209","url":null,"abstract":"ABSTRACTIn the existing dual output resistance tunable current controlled conveyor (DO-RTCCCII), a resistance trimming block is added at the X terminal (RXdig) which is controlled by programmable bits. RXdig includes the variations due to bias current (i.e. intrinsic resistance, RX) and due to setting of digital bits. However, the PVT variations may cause deviations in bias current, thus leading to inaccuracies in the design parameters. To address this, a programmable PVT compensated DO-RTCCCII (PPC-DO-RTCCCII) is proposed. It uses a reference generation section along with DO-RTCCCII. The reference generation section uses bias compensation bits for PVT independent bias current generation and also provides flexibility to get desired bias current through current multiplication bits. The operation of the proposed PPC-DO-RTCCCII has been designed and simulated using 28 nm CMOS technology through the simulator ELDO (AMS) tool of Mentor graphics. The post layout simulations closely match with pre layout simulations. A filter circuit is also included to illustrate the usefulness of the proposal.KEYWORDS: Analoguecurrent controlled current conveyorPVTElectronic tunabilityDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135549286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
ABSTRACTThe increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor ;(CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, Gate Oxide Tunneling Leakage Current, Sub threshold Leakage Current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS Technology(SLC-SG-FinFET- INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET- INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using Noise Margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS Technology (SLC-SCLSB-22 nm CMOS),and static logic circuit using computational digital low dropout in 22 nm CMOS Technology(SLC-CDLDO-22 nm CMOS) methods respectively.KEYWORDS: Complementary metal-oxide semiconductor (CMOS)leakage power dissipation22nm CMOS technologystatic logic gatesInput dependent (INDEP) FinFETDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.
{"title":"Design of high efficient low power static logic circuit using SG fin FET","authors":"Venkatesan RameyaSridharan, Manjunathan Alagarsamy, Balamurugan Rajangam, Lalitha Sekar","doi":"10.1080/00207217.2023.2261081","DOIUrl":"https://doi.org/10.1080/00207217.2023.2261081","url":null,"abstract":"ABSTRACTThe increasing demand of integration density improvement and battery-powered device efficiency reduced complementary metal-oxide semiconductor ;(CMOS) technology node. In the technology of CMOS, the components are mainly affected with leakage power, dynamic switching power, short circuit power, Gate Oxide Tunneling Leakage Current, Sub threshold Leakage Current, and so on. To reduce the above limitations, design of high efficient low power static logic circuit using shorted-gate (SG) fin field-effect transistor (FinFET) based INput DEPendent (INDEP) in 22 nm CMOS Technology(SLC-SG-FinFET- INDEP-22 nm CMOS) approach is proposed in this manuscript. The better selection of inputs to proposed INDEP FinFETs model is used for reducing leakage power. The efficiency of the proposed SLC-SG-FinFET- INDEP-22 nm CMOS technique is analysed using delay, power, power delay product, and stability analysis using Noise Margin. Thus, the proposed SLC-SG-FinFET-INDEP-22 nm CMOS has attained 21.31%, 41.47% and 12.7% lower delay, 20.87%, 34.5% and 22.41% lower power and 4.5%, 25.7% and 32.11% higher speed than existing methods static logic circuit input-controlled leakage restrainer transistor in 22 nm CMOS (SLC-ICLRT-22 nm CMOS), static logic circuit using self-control leakage-suppression block in 22 nm CMOS Technology (SLC-SCLSB-22 nm CMOS),and static logic circuit using computational digital low dropout in 22 nm CMOS Technology(SLC-CDLDO-22 nm CMOS) methods respectively.KEYWORDS: Complementary metal-oxide semiconductor (CMOS)leakage power dissipation22nm CMOS technologystatic logic gatesInput dependent (INDEP) FinFETDisclaimerAs a service to authors and researchers we are providing this version of an accepted manuscript (AM). Copyediting, typesetting, and review of the resulting proofs will be undertaken on this manuscript before final publication of the Version of Record (VoR). During production and pre-press, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal relate to these versions also.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136154829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A QCA placement and routing algorithm based on the SA algorithm","authors":"Gaisheng Li, Fei Peng, Bing Zhang, Yanshuai Li, Guangjun Xie","doi":"10.1080/00207217.2023.2248666","DOIUrl":"https://doi.org/10.1080/00207217.2023.2248666","url":null,"abstract":"","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"6 1","pages":""},"PeriodicalIF":1.3,"publicationDate":"2023-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79611941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-01DOI: 10.1080/00207217.2023.2245195
P. Balakrishnan, S. Gopinath
{"title":"A hybrid approach for enhancing the dynamic stability in power system","authors":"P. Balakrishnan, S. Gopinath","doi":"10.1080/00207217.2023.2245195","DOIUrl":"https://doi.org/10.1080/00207217.2023.2245195","url":null,"abstract":"","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"5 1","pages":""},"PeriodicalIF":1.3,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72978887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-29DOI: 10.1080/00207217.2023.2248662
Jagadeesh Babu Kamili, Tathababu Addepalli, Bhaskara Rao Perli, K. Bandi, Y. T. Mohammed
{"title":"Design of a Novel Four-element Koch-Sierpinski fractal mmwave antenna for 5G applications","authors":"Jagadeesh Babu Kamili, Tathababu Addepalli, Bhaskara Rao Perli, K. Bandi, Y. T. Mohammed","doi":"10.1080/00207217.2023.2248662","DOIUrl":"https://doi.org/10.1080/00207217.2023.2248662","url":null,"abstract":"","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"14 1","pages":""},"PeriodicalIF":1.3,"publicationDate":"2023-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89846229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-22DOI: 10.1080/00207217.2023.2248664
T. Roy, Sitakant Debata, P. Sadhu
{"title":"A High Boost Switched capacitor multilevel inverter with Reduced Components","authors":"T. Roy, Sitakant Debata, P. Sadhu","doi":"10.1080/00207217.2023.2248664","DOIUrl":"https://doi.org/10.1080/00207217.2023.2248664","url":null,"abstract":"","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"286 1","pages":""},"PeriodicalIF":1.3,"publicationDate":"2023-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79523675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-08-22DOI: 10.1080/00207217.2023.2248665
K. Jayasudha, S. Vijayalakshmi, M. Marimuthu
ABSTRACT Novel cascaded multilevel converters fed multilevel inverter for the AC load is presented here. In an inverter, total harmonic distortion plays a vital role. With the aim of reducing the harmonic value, the number of levels of an inverter should be increased. This circuit consists of two multilevel converters, two level controllers and two H-Bridge inverters. The advantage of this topology is to obtain more number of levels in an output, fewer significant number of switches, voltage sources and passive components like capacitors and diodes. This circuit could be operated in two ways as symmetric, & asymmetric configurations. As a result of this topology, 19-level output can be obtained. The performance of this circuit is simulated by means of MATLAB, and the hardware result is proved with the simulation results.
{"title":"A Novel Cascaded Multilevel Boost converter fed Multilevel inverter with reduced switch count","authors":"K. Jayasudha, S. Vijayalakshmi, M. Marimuthu","doi":"10.1080/00207217.2023.2248665","DOIUrl":"https://doi.org/10.1080/00207217.2023.2248665","url":null,"abstract":"ABSTRACT Novel cascaded multilevel converters fed multilevel inverter for the AC load is presented here. In an inverter, total harmonic distortion plays a vital role. With the aim of reducing the harmonic value, the number of levels of an inverter should be increased. This circuit consists of two multilevel converters, two level controllers and two H-Bridge inverters. The advantage of this topology is to obtain more number of levels in an output, fewer significant number of switches, voltage sources and passive components like capacitors and diodes. This circuit could be operated in two ways as symmetric, & asymmetric configurations. As a result of this topology, 19-level output can be obtained. The performance of this circuit is simulated by means of MATLAB, and the hardware result is proved with the simulation results.","PeriodicalId":54961,"journal":{"name":"International Journal of Electronics","volume":"7 1","pages":""},"PeriodicalIF":1.3,"publicationDate":"2023-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90037763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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